1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1999-2006 Helge Deller <[email protected]> (07-13-1999) 7 * Copyright (C) 1999 SuSE GmbH Nuernberg 8 * Copyright (C) 2000 Philipp Rumpf ([email protected]) 9 * 10 * Cache and TLB management 11 * 12 */ 13 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/mm.h> 17 #include <linux/module.h> 18 #include <linux/seq_file.h> 19 #include <linux/pagemap.h> 20 #include <linux/sched.h> 21 #include <linux/sched/mm.h> 22 #include <asm/pdc.h> 23 #include <asm/cache.h> 24 #include <asm/cacheflush.h> 25 #include <asm/tlbflush.h> 26 #include <asm/page.h> 27 #include <asm/pgalloc.h> 28 #include <asm/processor.h> 29 #include <asm/sections.h> 30 #include <asm/shmparam.h> 31 32 int split_tlb __read_mostly; 33 int dcache_stride __read_mostly; 34 int icache_stride __read_mostly; 35 EXPORT_SYMBOL(dcache_stride); 36 37 void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr); 38 EXPORT_SYMBOL(flush_dcache_page_asm); 39 void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr); 40 41 42 /* On some machines (e.g. ones with the Merced bus), there can be 43 * only a single PxTLB broadcast at a time; this must be guaranteed 44 * by software. We put a spinlock around all TLB flushes to 45 * ensure this. 46 */ 47 DEFINE_SPINLOCK(pa_tlb_lock); 48 49 struct pdc_cache_info cache_info __read_mostly; 50 #ifndef CONFIG_PA20 51 static struct pdc_btlb_info btlb_info __read_mostly; 52 #endif 53 54 #ifdef CONFIG_SMP 55 void 56 flush_data_cache(void) 57 { 58 on_each_cpu(flush_data_cache_local, NULL, 1); 59 } 60 void 61 flush_instruction_cache(void) 62 { 63 on_each_cpu(flush_instruction_cache_local, NULL, 1); 64 } 65 #endif 66 67 void 68 flush_cache_all_local(void) 69 { 70 flush_instruction_cache_local(NULL); 71 flush_data_cache_local(NULL); 72 } 73 EXPORT_SYMBOL(flush_cache_all_local); 74 75 /* Virtual address of pfn. */ 76 #define pfn_va(pfn) __va(PFN_PHYS(pfn)) 77 78 void 79 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) 80 { 81 unsigned long pfn = pte_pfn(*ptep); 82 struct page *page; 83 84 /* We don't have pte special. As a result, we can be called with 85 an invalid pfn and we don't need to flush the kernel dcache page. 86 This occurs with FireGL card in C8000. */ 87 if (!pfn_valid(pfn)) 88 return; 89 90 page = pfn_to_page(pfn); 91 if (page_mapping_file(page) && 92 test_bit(PG_dcache_dirty, &page->flags)) { 93 flush_kernel_dcache_page_addr(pfn_va(pfn)); 94 clear_bit(PG_dcache_dirty, &page->flags); 95 } else if (parisc_requires_coherency()) 96 flush_kernel_dcache_page_addr(pfn_va(pfn)); 97 } 98 99 void 100 show_cache_info(struct seq_file *m) 101 { 102 char buf[32]; 103 104 seq_printf(m, "I-cache\t\t: %ld KB\n", 105 cache_info.ic_size/1024 ); 106 if (cache_info.dc_loop != 1) 107 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop); 108 seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n", 109 cache_info.dc_size/1024, 110 (cache_info.dc_conf.cc_wt ? "WT":"WB"), 111 (cache_info.dc_conf.cc_sh ? ", shared I/D":""), 112 ((cache_info.dc_loop == 1) ? "direct mapped" : buf)); 113 seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n", 114 cache_info.it_size, 115 cache_info.dt_size, 116 cache_info.dt_conf.tc_sh ? " - shared with ITLB":"" 117 ); 118 119 #ifndef CONFIG_PA20 120 /* BTLB - Block TLB */ 121 if (btlb_info.max_size==0) { 122 seq_printf(m, "BTLB\t\t: not supported\n" ); 123 } else { 124 seq_printf(m, 125 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n" 126 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n" 127 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n", 128 btlb_info.max_size, (int)4096, 129 btlb_info.max_size>>8, 130 btlb_info.fixed_range_info.num_i, 131 btlb_info.fixed_range_info.num_d, 132 btlb_info.fixed_range_info.num_comb, 133 btlb_info.variable_range_info.num_i, 134 btlb_info.variable_range_info.num_d, 135 btlb_info.variable_range_info.num_comb 136 ); 137 } 138 #endif 139 } 140 141 void __init 142 parisc_cache_init(void) 143 { 144 if (pdc_cache_info(&cache_info) < 0) 145 panic("parisc_cache_init: pdc_cache_info failed"); 146 147 #if 0 148 printk("ic_size %lx dc_size %lx it_size %lx\n", 149 cache_info.ic_size, 150 cache_info.dc_size, 151 cache_info.it_size); 152 153 printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n", 154 cache_info.dc_base, 155 cache_info.dc_stride, 156 cache_info.dc_count, 157 cache_info.dc_loop); 158 159 printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n", 160 *(unsigned long *) (&cache_info.dc_conf), 161 cache_info.dc_conf.cc_alias, 162 cache_info.dc_conf.cc_block, 163 cache_info.dc_conf.cc_line, 164 cache_info.dc_conf.cc_shift); 165 printk(" wt %d sh %d cst %d hv %d\n", 166 cache_info.dc_conf.cc_wt, 167 cache_info.dc_conf.cc_sh, 168 cache_info.dc_conf.cc_cst, 169 cache_info.dc_conf.cc_hv); 170 171 printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n", 172 cache_info.ic_base, 173 cache_info.ic_stride, 174 cache_info.ic_count, 175 cache_info.ic_loop); 176 177 printk("IT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n", 178 cache_info.it_sp_base, 179 cache_info.it_sp_stride, 180 cache_info.it_sp_count, 181 cache_info.it_loop, 182 cache_info.it_off_base, 183 cache_info.it_off_stride, 184 cache_info.it_off_count); 185 186 printk("DT base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx off_base 0x%lx off_stride 0x%lx off_count 0x%lx\n", 187 cache_info.dt_sp_base, 188 cache_info.dt_sp_stride, 189 cache_info.dt_sp_count, 190 cache_info.dt_loop, 191 cache_info.dt_off_base, 192 cache_info.dt_off_stride, 193 cache_info.dt_off_count); 194 195 printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n", 196 *(unsigned long *) (&cache_info.ic_conf), 197 cache_info.ic_conf.cc_alias, 198 cache_info.ic_conf.cc_block, 199 cache_info.ic_conf.cc_line, 200 cache_info.ic_conf.cc_shift); 201 printk(" wt %d sh %d cst %d hv %d\n", 202 cache_info.ic_conf.cc_wt, 203 cache_info.ic_conf.cc_sh, 204 cache_info.ic_conf.cc_cst, 205 cache_info.ic_conf.cc_hv); 206 207 printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n", 208 cache_info.dt_conf.tc_sh, 209 cache_info.dt_conf.tc_page, 210 cache_info.dt_conf.tc_cst, 211 cache_info.dt_conf.tc_aid, 212 cache_info.dt_conf.tc_sr); 213 214 printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n", 215 cache_info.it_conf.tc_sh, 216 cache_info.it_conf.tc_page, 217 cache_info.it_conf.tc_cst, 218 cache_info.it_conf.tc_aid, 219 cache_info.it_conf.tc_sr); 220 #endif 221 222 split_tlb = 0; 223 if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) { 224 if (cache_info.dt_conf.tc_sh == 2) 225 printk(KERN_WARNING "Unexpected TLB configuration. " 226 "Will flush I/D separately (could be optimized).\n"); 227 228 split_tlb = 1; 229 } 230 231 /* "New and Improved" version from Jim Hull 232 * (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift)) 233 * The following CAFL_STRIDE is an optimized version, see 234 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html 235 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html 236 */ 237 #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift)) 238 dcache_stride = CAFL_STRIDE(cache_info.dc_conf); 239 icache_stride = CAFL_STRIDE(cache_info.ic_conf); 240 #undef CAFL_STRIDE 241 242 #ifndef CONFIG_PA20 243 if (pdc_btlb_info(&btlb_info) < 0) { 244 memset(&btlb_info, 0, sizeof btlb_info); 245 } 246 #endif 247 248 if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) == 249 PDC_MODEL_NVA_UNSUPPORTED) { 250 printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n"); 251 #if 0 252 panic("SMP kernel required to avoid non-equivalent aliasing"); 253 #endif 254 } 255 } 256 257 void __init disable_sr_hashing(void) 258 { 259 int srhash_type, retval; 260 unsigned long space_bits; 261 262 switch (boot_cpu_data.cpu_type) { 263 case pcx: /* We shouldn't get this far. setup.c should prevent it. */ 264 BUG(); 265 return; 266 267 case pcxs: 268 case pcxt: 269 case pcxt_: 270 srhash_type = SRHASH_PCXST; 271 break; 272 273 case pcxl: 274 srhash_type = SRHASH_PCXL; 275 break; 276 277 case pcxl2: /* pcxl2 doesn't support space register hashing */ 278 return; 279 280 default: /* Currently all PA2.0 machines use the same ins. sequence */ 281 srhash_type = SRHASH_PA20; 282 break; 283 } 284 285 disable_sr_hashing_asm(srhash_type); 286 287 retval = pdc_spaceid_bits(&space_bits); 288 /* If this procedure isn't implemented, don't panic. */ 289 if (retval < 0 && retval != PDC_BAD_OPTION) 290 panic("pdc_spaceid_bits call failed.\n"); 291 if (space_bits != 0) 292 panic("SpaceID hashing is still on!\n"); 293 } 294 295 static inline void 296 __flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, 297 unsigned long physaddr) 298 { 299 preempt_disable(); 300 flush_dcache_page_asm(physaddr, vmaddr); 301 if (vma->vm_flags & VM_EXEC) 302 flush_icache_page_asm(physaddr, vmaddr); 303 preempt_enable(); 304 } 305 306 void flush_dcache_page(struct page *page) 307 { 308 struct address_space *mapping = page_mapping_file(page); 309 struct vm_area_struct *mpnt; 310 unsigned long offset; 311 unsigned long addr, old_addr = 0; 312 pgoff_t pgoff; 313 314 if (mapping && !mapping_mapped(mapping)) { 315 set_bit(PG_dcache_dirty, &page->flags); 316 return; 317 } 318 319 flush_kernel_dcache_page(page); 320 321 if (!mapping) 322 return; 323 324 pgoff = page->index; 325 326 /* We have carefully arranged in arch_get_unmapped_area() that 327 * *any* mappings of a file are always congruently mapped (whether 328 * declared as MAP_PRIVATE or MAP_SHARED), so we only need 329 * to flush one address here for them all to become coherent */ 330 331 flush_dcache_mmap_lock(mapping); 332 vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) { 333 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; 334 addr = mpnt->vm_start + offset; 335 336 /* The TLB is the engine of coherence on parisc: The 337 * CPU is entitled to speculate any page with a TLB 338 * mapping, so here we kill the mapping then flush the 339 * page along a special flush only alias mapping. 340 * This guarantees that the page is no-longer in the 341 * cache for any process and nor may it be 342 * speculatively read in (until the user or kernel 343 * specifically accesses it, of course) */ 344 345 flush_tlb_page(mpnt, addr); 346 if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1)) 347 != (addr & (SHM_COLOUR - 1))) { 348 __flush_cache_page(mpnt, addr, page_to_phys(page)); 349 if (old_addr) 350 printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %pD\n", old_addr, addr, mpnt->vm_file); 351 old_addr = addr; 352 } 353 } 354 flush_dcache_mmap_unlock(mapping); 355 } 356 EXPORT_SYMBOL(flush_dcache_page); 357 358 /* Defined in arch/parisc/kernel/pacache.S */ 359 EXPORT_SYMBOL(flush_kernel_dcache_range_asm); 360 EXPORT_SYMBOL(flush_kernel_dcache_page_asm); 361 EXPORT_SYMBOL(flush_data_cache_local); 362 EXPORT_SYMBOL(flush_kernel_icache_range_asm); 363 364 #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */ 365 static unsigned long parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD; 366 367 #define FLUSH_TLB_THRESHOLD (16*1024) /* 16 KiB minimum TLB threshold */ 368 static unsigned long parisc_tlb_flush_threshold __read_mostly = FLUSH_TLB_THRESHOLD; 369 370 void __init parisc_setup_cache_timing(void) 371 { 372 unsigned long rangetime, alltime; 373 unsigned long size, start; 374 unsigned long threshold; 375 376 alltime = mfctl(16); 377 flush_data_cache(); 378 alltime = mfctl(16) - alltime; 379 380 size = (unsigned long)(_end - _text); 381 rangetime = mfctl(16); 382 flush_kernel_dcache_range((unsigned long)_text, size); 383 rangetime = mfctl(16) - rangetime; 384 385 printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n", 386 alltime, size, rangetime); 387 388 threshold = L1_CACHE_ALIGN(size * alltime / rangetime); 389 if (threshold > cache_info.dc_size) 390 threshold = cache_info.dc_size; 391 if (threshold) 392 parisc_cache_flush_threshold = threshold; 393 printk(KERN_INFO "Cache flush threshold set to %lu KiB\n", 394 parisc_cache_flush_threshold/1024); 395 396 /* calculate TLB flush threshold */ 397 398 /* On SMP machines, skip the TLB measure of kernel text which 399 * has been mapped as huge pages. */ 400 if (num_online_cpus() > 1 && !parisc_requires_coherency()) { 401 threshold = max(cache_info.it_size, cache_info.dt_size); 402 threshold *= PAGE_SIZE; 403 threshold /= num_online_cpus(); 404 goto set_tlb_threshold; 405 } 406 407 size = 0; 408 start = (unsigned long) _text; 409 rangetime = mfctl(16); 410 while (start < (unsigned long) _end) { 411 flush_tlb_kernel_range(start, start + PAGE_SIZE); 412 start += PAGE_SIZE; 413 size += PAGE_SIZE; 414 } 415 rangetime = mfctl(16) - rangetime; 416 417 alltime = mfctl(16); 418 flush_tlb_all(); 419 alltime = mfctl(16) - alltime; 420 421 printk(KERN_INFO "Whole TLB flush %lu cycles, Range flush %lu bytes %lu cycles\n", 422 alltime, size, rangetime); 423 424 threshold = PAGE_ALIGN((num_online_cpus() * size * alltime) / rangetime); 425 printk(KERN_INFO "Calculated TLB flush threshold %lu KiB\n", 426 threshold/1024); 427 428 set_tlb_threshold: 429 if (threshold > parisc_tlb_flush_threshold) 430 parisc_tlb_flush_threshold = threshold; 431 printk(KERN_INFO "TLB flush threshold set to %lu KiB\n", 432 parisc_tlb_flush_threshold/1024); 433 } 434 435 extern void purge_kernel_dcache_page_asm(unsigned long); 436 extern void clear_user_page_asm(void *, unsigned long); 437 extern void copy_user_page_asm(void *, void *, unsigned long); 438 439 void flush_kernel_dcache_page_addr(void *addr) 440 { 441 unsigned long flags; 442 443 flush_kernel_dcache_page_asm(addr); 444 purge_tlb_start(flags); 445 pdtlb_kernel(addr); 446 purge_tlb_end(flags); 447 } 448 EXPORT_SYMBOL(flush_kernel_dcache_page_addr); 449 450 void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, 451 struct page *pg) 452 { 453 /* Copy using kernel mapping. No coherency is needed (all in 454 kunmap) for the `to' page. However, the `from' page needs to 455 be flushed through a mapping equivalent to the user mapping 456 before it can be accessed through the kernel mapping. */ 457 preempt_disable(); 458 flush_dcache_page_asm(__pa(vfrom), vaddr); 459 copy_page_asm(vto, vfrom); 460 preempt_enable(); 461 } 462 EXPORT_SYMBOL(copy_user_page); 463 464 /* __flush_tlb_range() 465 * 466 * returns 1 if all TLBs were flushed. 467 */ 468 int __flush_tlb_range(unsigned long sid, unsigned long start, 469 unsigned long end) 470 { 471 unsigned long flags; 472 473 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) && 474 end - start >= parisc_tlb_flush_threshold) { 475 flush_tlb_all(); 476 return 1; 477 } 478 479 /* Purge TLB entries for small ranges using the pdtlb and 480 pitlb instructions. These instructions execute locally 481 but cause a purge request to be broadcast to other TLBs. */ 482 if (likely(!split_tlb)) { 483 while (start < end) { 484 purge_tlb_start(flags); 485 mtsp(sid, 1); 486 pdtlb(start); 487 purge_tlb_end(flags); 488 start += PAGE_SIZE; 489 } 490 return 0; 491 } 492 493 /* split TLB case */ 494 while (start < end) { 495 purge_tlb_start(flags); 496 mtsp(sid, 1); 497 pdtlb(start); 498 pitlb(start); 499 purge_tlb_end(flags); 500 start += PAGE_SIZE; 501 } 502 return 0; 503 } 504 505 static void cacheflush_h_tmp_function(void *dummy) 506 { 507 flush_cache_all_local(); 508 } 509 510 void flush_cache_all(void) 511 { 512 on_each_cpu(cacheflush_h_tmp_function, NULL, 1); 513 } 514 515 static inline unsigned long mm_total_size(struct mm_struct *mm) 516 { 517 struct vm_area_struct *vma; 518 unsigned long usize = 0; 519 520 for (vma = mm->mmap; vma; vma = vma->vm_next) 521 usize += vma->vm_end - vma->vm_start; 522 return usize; 523 } 524 525 static inline pte_t *get_ptep(pgd_t *pgd, unsigned long addr) 526 { 527 pte_t *ptep = NULL; 528 529 if (!pgd_none(*pgd)) { 530 pud_t *pud = pud_offset(pgd, addr); 531 if (!pud_none(*pud)) { 532 pmd_t *pmd = pmd_offset(pud, addr); 533 if (!pmd_none(*pmd)) 534 ptep = pte_offset_map(pmd, addr); 535 } 536 } 537 return ptep; 538 } 539 540 void flush_cache_mm(struct mm_struct *mm) 541 { 542 struct vm_area_struct *vma; 543 pgd_t *pgd; 544 545 /* Flushing the whole cache on each cpu takes forever on 546 rp3440, etc. So, avoid it if the mm isn't too big. */ 547 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) && 548 mm_total_size(mm) >= parisc_cache_flush_threshold) { 549 if (mm->context) 550 flush_tlb_all(); 551 flush_cache_all(); 552 return; 553 } 554 555 if (mm->context == mfsp(3)) { 556 for (vma = mm->mmap; vma; vma = vma->vm_next) { 557 flush_user_dcache_range_asm(vma->vm_start, vma->vm_end); 558 if (vma->vm_flags & VM_EXEC) 559 flush_user_icache_range_asm(vma->vm_start, vma->vm_end); 560 flush_tlb_range(vma, vma->vm_start, vma->vm_end); 561 } 562 return; 563 } 564 565 pgd = mm->pgd; 566 for (vma = mm->mmap; vma; vma = vma->vm_next) { 567 unsigned long addr; 568 569 for (addr = vma->vm_start; addr < vma->vm_end; 570 addr += PAGE_SIZE) { 571 unsigned long pfn; 572 pte_t *ptep = get_ptep(pgd, addr); 573 if (!ptep) 574 continue; 575 pfn = pte_pfn(*ptep); 576 if (!pfn_valid(pfn)) 577 continue; 578 if (unlikely(mm->context)) 579 flush_tlb_page(vma, addr); 580 __flush_cache_page(vma, addr, PFN_PHYS(pfn)); 581 } 582 } 583 } 584 585 void flush_cache_range(struct vm_area_struct *vma, 586 unsigned long start, unsigned long end) 587 { 588 pgd_t *pgd; 589 unsigned long addr; 590 591 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) && 592 end - start >= parisc_cache_flush_threshold) { 593 if (vma->vm_mm->context) 594 flush_tlb_range(vma, start, end); 595 flush_cache_all(); 596 return; 597 } 598 599 if (vma->vm_mm->context == mfsp(3)) { 600 flush_user_dcache_range_asm(start, end); 601 if (vma->vm_flags & VM_EXEC) 602 flush_user_icache_range_asm(start, end); 603 flush_tlb_range(vma, start, end); 604 return; 605 } 606 607 pgd = vma->vm_mm->pgd; 608 for (addr = vma->vm_start; addr < vma->vm_end; addr += PAGE_SIZE) { 609 unsigned long pfn; 610 pte_t *ptep = get_ptep(pgd, addr); 611 if (!ptep) 612 continue; 613 pfn = pte_pfn(*ptep); 614 if (pfn_valid(pfn)) { 615 if (unlikely(vma->vm_mm->context)) 616 flush_tlb_page(vma, addr); 617 __flush_cache_page(vma, addr, PFN_PHYS(pfn)); 618 } 619 } 620 } 621 622 void 623 flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn) 624 { 625 if (pfn_valid(pfn)) { 626 if (likely(vma->vm_mm->context)) 627 flush_tlb_page(vma, vmaddr); 628 __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn)); 629 } 630 } 631 632 void flush_kernel_vmap_range(void *vaddr, int size) 633 { 634 unsigned long start = (unsigned long)vaddr; 635 unsigned long end = start + size; 636 637 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) && 638 (unsigned long)size >= parisc_cache_flush_threshold) { 639 flush_tlb_kernel_range(start, end); 640 flush_data_cache(); 641 return; 642 } 643 644 flush_kernel_dcache_range_asm(start, end); 645 flush_tlb_kernel_range(start, end); 646 } 647 EXPORT_SYMBOL(flush_kernel_vmap_range); 648 649 void invalidate_kernel_vmap_range(void *vaddr, int size) 650 { 651 unsigned long start = (unsigned long)vaddr; 652 unsigned long end = start + size; 653 654 if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) && 655 (unsigned long)size >= parisc_cache_flush_threshold) { 656 flush_tlb_kernel_range(start, end); 657 flush_data_cache(); 658 return; 659 } 660 661 purge_kernel_dcache_range_asm(start, end); 662 flush_tlb_kernel_range(start, end); 663 } 664 EXPORT_SYMBOL(invalidate_kernel_vmap_range); 665