1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ralink RT2880 timer 4 * Author: John Crispin 5 * 6 * Copyright (C) 2013 John Crispin <[email protected]> 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/interrupt.h> 11 #include <linux/timer.h> 12 #include <linux/clk.h> 13 14 #include <asm/mach-ralink/ralink_regs.h> 15 16 #define TIMER_REG_TMRSTAT 0x00 17 #define TIMER_REG_TMR0LOAD 0x10 18 #define TIMER_REG_TMR0CTL 0x18 19 20 #define TMRSTAT_TMR0INT BIT(0) 21 22 #define TMR0CTL_ENABLE BIT(7) 23 #define TMR0CTL_MODE_PERIODIC BIT(4) 24 #define TMR0CTL_PRESCALER 1 25 #define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER) 26 #define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER)) 27 28 struct rt_timer { 29 struct device *dev; 30 void __iomem *membase; 31 int irq; 32 unsigned long timer_freq; 33 unsigned long timer_div; 34 }; 35 36 static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val) 37 { 38 __raw_writel(val, rt->membase + reg); 39 } 40 41 static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg) 42 { 43 return __raw_readl(rt->membase + reg); 44 } 45 46 static irqreturn_t rt_timer_irq(int irq, void *_rt) 47 { 48 struct rt_timer *rt = (struct rt_timer *) _rt; 49 50 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div); 51 rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT); 52 53 return IRQ_HANDLED; 54 } 55 56 57 static int rt_timer_request(struct rt_timer *rt) 58 { 59 int err = request_irq(rt->irq, rt_timer_irq, 0, 60 dev_name(rt->dev), rt); 61 if (err) { 62 dev_err(rt->dev, "failed to request irq\n"); 63 } else { 64 u32 t = TMR0CTL_MODE_PERIODIC | TMR0CTL_PRESCALE_VAL; 65 rt_timer_w32(rt, TIMER_REG_TMR0CTL, t); 66 } 67 return err; 68 } 69 70 static int rt_timer_config(struct rt_timer *rt, unsigned long divisor) 71 { 72 if (rt->timer_freq < divisor) 73 rt->timer_div = rt->timer_freq; 74 else 75 rt->timer_div = divisor; 76 77 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div); 78 79 return 0; 80 } 81 82 static int rt_timer_enable(struct rt_timer *rt) 83 { 84 u32 t; 85 86 rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div); 87 88 t = rt_timer_r32(rt, TIMER_REG_TMR0CTL); 89 t |= TMR0CTL_ENABLE; 90 rt_timer_w32(rt, TIMER_REG_TMR0CTL, t); 91 92 return 0; 93 } 94 95 static int rt_timer_probe(struct platform_device *pdev) 96 { 97 struct rt_timer *rt; 98 struct clk *clk; 99 100 rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL); 101 if (!rt) { 102 dev_err(&pdev->dev, "failed to allocate memory\n"); 103 return -ENOMEM; 104 } 105 106 rt->irq = platform_get_irq(pdev, 0); 107 if (rt->irq < 0) 108 return rt->irq; 109 110 rt->membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 111 if (IS_ERR(rt->membase)) 112 return PTR_ERR(rt->membase); 113 114 clk = devm_clk_get(&pdev->dev, NULL); 115 if (IS_ERR(clk)) { 116 dev_err(&pdev->dev, "failed get clock rate\n"); 117 return PTR_ERR(clk); 118 } 119 120 rt->timer_freq = clk_get_rate(clk) / TMR0CTL_PRESCALE_DIV; 121 if (!rt->timer_freq) 122 return -EINVAL; 123 124 rt->dev = &pdev->dev; 125 platform_set_drvdata(pdev, rt); 126 127 rt_timer_request(rt); 128 rt_timer_config(rt, 2); 129 rt_timer_enable(rt); 130 131 dev_info(&pdev->dev, "maximum frequency is %luHz\n", rt->timer_freq); 132 133 return 0; 134 } 135 136 static const struct of_device_id rt_timer_match[] = { 137 { .compatible = "ralink,rt2880-timer" }, 138 {}, 139 }; 140 141 static struct platform_driver rt_timer_driver = { 142 .probe = rt_timer_probe, 143 .driver = { 144 .name = "rt-timer", 145 .of_match_table = rt_timer_match, 146 .suppress_bind_attrs = true, 147 }, 148 }; 149 builtin_platform_driver(rt_timer_driver); 150