1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Quick'n'dirty IP checksum ... 7 * 8 * Copyright (C) 1998, 1999 Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Copyright (C) 2007 Maciej W. Rozycki 11 * Copyright (C) 2014 Imagination Technologies Ltd. 12 */ 13#include <linux/errno.h> 14#include <asm/asm.h> 15#include <asm/asm-offsets.h> 16#include <asm/regdef.h> 17 18#ifdef CONFIG_64BIT 19/* 20 * As we are sharing code base with the mips32 tree (which use the o32 ABI 21 * register definitions). We need to redefine the register definitions from 22 * the n64 ABI register naming to the o32 ABI register naming. 23 */ 24#undef t0 25#undef t1 26#undef t2 27#undef t3 28#define t0 $8 29#define t1 $9 30#define t2 $10 31#define t3 $11 32#define t4 $12 33#define t5 $13 34#define t6 $14 35#define t7 $15 36 37#define USE_DOUBLE 38#endif 39 40#ifdef USE_DOUBLE 41 42#define LOAD ld 43#define LOAD32 lwu 44#define ADD daddu 45#define NBYTES 8 46 47#else 48 49#define LOAD lw 50#define LOAD32 lw 51#define ADD addu 52#define NBYTES 4 53 54#endif /* USE_DOUBLE */ 55 56#define UNIT(unit) ((unit)*NBYTES) 57 58#define ADDC(sum,reg) \ 59 ADD sum, reg; \ 60 sltu v1, sum, reg; \ 61 ADD sum, v1; \ 62 63#define ADDC32(sum,reg) \ 64 addu sum, reg; \ 65 sltu v1, sum, reg; \ 66 addu sum, v1; \ 67 68#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \ 69 LOAD _t0, (offset + UNIT(0))(src); \ 70 LOAD _t1, (offset + UNIT(1))(src); \ 71 LOAD _t2, (offset + UNIT(2))(src); \ 72 LOAD _t3, (offset + UNIT(3))(src); \ 73 ADDC(sum, _t0); \ 74 ADDC(sum, _t1); \ 75 ADDC(sum, _t2); \ 76 ADDC(sum, _t3) 77 78#ifdef USE_DOUBLE 79#define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3) \ 80 CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) 81#else 82#define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3) \ 83 CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3); \ 84 CSUM_BIGCHUNK1(src, offset + 0x10, sum, _t0, _t1, _t2, _t3) 85#endif 86 87/* 88 * a0: source address 89 * a1: length of the area to checksum 90 * a2: partial checksum 91 */ 92 93#define src a0 94#define sum v0 95 96 .text 97 .set noreorder 98 .align 5 99LEAF(csum_partial) 100 move sum, zero 101 move t7, zero 102 103 sltiu t8, a1, 0x8 104 bnez t8, .Lsmall_csumcpy /* < 8 bytes to copy */ 105 move t2, a1 106 107 andi t7, src, 0x1 /* odd buffer? */ 108 109.Lhword_align: 110 beqz t7, .Lword_align 111 andi t8, src, 0x2 112 113 lbu t0, (src) 114 LONG_SUBU a1, a1, 0x1 115#ifdef __MIPSEL__ 116 sll t0, t0, 8 117#endif 118 ADDC(sum, t0) 119 PTR_ADDU src, src, 0x1 120 andi t8, src, 0x2 121 122.Lword_align: 123 beqz t8, .Ldword_align 124 sltiu t8, a1, 56 125 126 lhu t0, (src) 127 LONG_SUBU a1, a1, 0x2 128 ADDC(sum, t0) 129 sltiu t8, a1, 56 130 PTR_ADDU src, src, 0x2 131 132.Ldword_align: 133 bnez t8, .Ldo_end_words 134 move t8, a1 135 136 andi t8, src, 0x4 137 beqz t8, .Lqword_align 138 andi t8, src, 0x8 139 140 LOAD32 t0, 0x00(src) 141 LONG_SUBU a1, a1, 0x4 142 ADDC(sum, t0) 143 PTR_ADDU src, src, 0x4 144 andi t8, src, 0x8 145 146.Lqword_align: 147 beqz t8, .Loword_align 148 andi t8, src, 0x10 149 150#ifdef USE_DOUBLE 151 ld t0, 0x00(src) 152 LONG_SUBU a1, a1, 0x8 153 ADDC(sum, t0) 154#else 155 lw t0, 0x00(src) 156 lw t1, 0x04(src) 157 LONG_SUBU a1, a1, 0x8 158 ADDC(sum, t0) 159 ADDC(sum, t1) 160#endif 161 PTR_ADDU src, src, 0x8 162 andi t8, src, 0x10 163 164.Loword_align: 165 beqz t8, .Lbegin_movement 166 LONG_SRL t8, a1, 0x7 167 168#ifdef USE_DOUBLE 169 ld t0, 0x00(src) 170 ld t1, 0x08(src) 171 ADDC(sum, t0) 172 ADDC(sum, t1) 173#else 174 CSUM_BIGCHUNK1(src, 0x00, sum, t0, t1, t3, t4) 175#endif 176 LONG_SUBU a1, a1, 0x10 177 PTR_ADDU src, src, 0x10 178 LONG_SRL t8, a1, 0x7 179 180.Lbegin_movement: 181 beqz t8, 1f 182 andi t2, a1, 0x40 183 184.Lmove_128bytes: 185 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) 186 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4) 187 CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4) 188 CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4) 189 LONG_SUBU t8, t8, 0x01 190 .set reorder /* DADDI_WAR */ 191 PTR_ADDU src, src, 0x80 192 bnez t8, .Lmove_128bytes 193 .set noreorder 194 1951: 196 beqz t2, 1f 197 andi t2, a1, 0x20 198 199.Lmove_64bytes: 200 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) 201 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4) 202 PTR_ADDU src, src, 0x40 203 2041: 205 beqz t2, .Ldo_end_words 206 andi t8, a1, 0x1c 207 208.Lmove_32bytes: 209 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) 210 andi t8, a1, 0x1c 211 PTR_ADDU src, src, 0x20 212 213.Ldo_end_words: 214 beqz t8, .Lsmall_csumcpy 215 andi t2, a1, 0x3 216 LONG_SRL t8, t8, 0x2 217 218.Lend_words: 219 LOAD32 t0, (src) 220 LONG_SUBU t8, t8, 0x1 221 ADDC(sum, t0) 222 .set reorder /* DADDI_WAR */ 223 PTR_ADDU src, src, 0x4 224 bnez t8, .Lend_words 225 .set noreorder 226 227/* unknown src alignment and < 8 bytes to go */ 228.Lsmall_csumcpy: 229 move a1, t2 230 231 andi t0, a1, 4 232 beqz t0, 1f 233 andi t0, a1, 2 234 235 /* Still a full word to go */ 236 ulw t1, (src) 237 PTR_ADDIU src, 4 238#ifdef USE_DOUBLE 239 dsll t1, t1, 32 /* clear lower 32bit */ 240#endif 241 ADDC(sum, t1) 242 2431: move t1, zero 244 beqz t0, 1f 245 andi t0, a1, 1 246 247 /* Still a halfword to go */ 248 ulhu t1, (src) 249 PTR_ADDIU src, 2 250 2511: beqz t0, 1f 252 sll t1, t1, 16 253 254 lbu t2, (src) 255 nop 256 257#ifdef __MIPSEB__ 258 sll t2, t2, 8 259#endif 260 or t1, t2 261 2621: ADDC(sum, t1) 263 264 /* fold checksum */ 265#ifdef USE_DOUBLE 266 dsll32 v1, sum, 0 267 daddu sum, v1 268 sltu v1, sum, v1 269 dsra32 sum, sum, 0 270 addu sum, v1 271#endif 272 273 /* odd buffer alignment? */ 274#ifdef CONFIG_CPU_MIPSR2 275 wsbh v1, sum 276 movn sum, v1, t7 277#else 278 beqz t7, 1f /* odd buffer alignment? */ 279 lui v1, 0x00ff 280 addu v1, 0x00ff 281 and t0, sum, v1 282 sll t0, t0, 8 283 srl sum, sum, 8 284 and sum, sum, v1 285 or sum, sum, t0 2861: 287#endif 288 .set reorder 289 /* Add the passed partial csum. */ 290 ADDC32(sum, a2) 291 jr ra 292 .set noreorder 293 END(csum_partial) 294 295 296/* 297 * checksum and copy routines based on memcpy.S 298 * 299 * csum_partial_copy_nocheck(src, dst, len, sum) 300 * __csum_partial_copy_kernel(src, dst, len, sum, errp) 301 * 302 * See "Spec" in memcpy.S for details. Unlike __copy_user, all 303 * function in this file use the standard calling convention. 304 */ 305 306#define src a0 307#define dst a1 308#define len a2 309#define psum a3 310#define sum v0 311#define odd t8 312#define errptr t9 313 314/* 315 * The exception handler for loads requires that: 316 * 1- AT contain the address of the byte just past the end of the source 317 * of the copy, 318 * 2- src_entry <= src < AT, and 319 * 3- (dst - src) == (dst_entry - src_entry), 320 * The _entry suffix denotes values when __copy_user was called. 321 * 322 * (1) is set up up by __csum_partial_copy_from_user and maintained by 323 * not writing AT in __csum_partial_copy 324 * (2) is met by incrementing src by the number of bytes copied 325 * (3) is met by not doing loads between a pair of increments of dst and src 326 * 327 * The exception handlers for stores stores -EFAULT to errptr and return. 328 * These handlers do not need to overwrite any data. 329 */ 330 331/* Instruction type */ 332#define LD_INSN 1 333#define ST_INSN 2 334 335/* 336 * Wrapper to add an entry in the exception table 337 * in case the insn causes a memory exception. 338 * Arguments: 339 * insn : Load/store instruction 340 * type : Instruction type 341 * reg : Register 342 * addr : Address 343 * handler : Exception handler 344 */ 345#define EXC(insn, type, reg, addr, handler) \ 3469: insn reg, addr; \ 347 .section __ex_table,"a"; \ 348 PTR 9b, handler; \ 349 .previous 350 351#undef LOAD 352 353#ifdef USE_DOUBLE 354 355#define LOADK ld /* No exception */ 356#define LOAD(reg, addr, handler) EXC(ld, LD_INSN, reg, addr, handler) 357#define LOADBU(reg, addr, handler) EXC(lbu, LD_INSN, reg, addr, handler) 358#define LOADL(reg, addr, handler) EXC(ldl, LD_INSN, reg, addr, handler) 359#define LOADR(reg, addr, handler) EXC(ldr, LD_INSN, reg, addr, handler) 360#define STOREB(reg, addr, handler) EXC(sb, ST_INSN, reg, addr, handler) 361#define STOREL(reg, addr, handler) EXC(sdl, ST_INSN, reg, addr, handler) 362#define STORER(reg, addr, handler) EXC(sdr, ST_INSN, reg, addr, handler) 363#define STORE(reg, addr, handler) EXC(sd, ST_INSN, reg, addr, handler) 364#define ADD daddu 365#define SUB dsubu 366#define SRL dsrl 367#define SLL dsll 368#define SLLV dsllv 369#define SRLV dsrlv 370#define NBYTES 8 371#define LOG_NBYTES 3 372 373#else 374 375#define LOADK lw /* No exception */ 376#define LOAD(reg, addr, handler) EXC(lw, LD_INSN, reg, addr, handler) 377#define LOADBU(reg, addr, handler) EXC(lbu, LD_INSN, reg, addr, handler) 378#define LOADL(reg, addr, handler) EXC(lwl, LD_INSN, reg, addr, handler) 379#define LOADR(reg, addr, handler) EXC(lwr, LD_INSN, reg, addr, handler) 380#define STOREB(reg, addr, handler) EXC(sb, ST_INSN, reg, addr, handler) 381#define STOREL(reg, addr, handler) EXC(swl, ST_INSN, reg, addr, handler) 382#define STORER(reg, addr, handler) EXC(swr, ST_INSN, reg, addr, handler) 383#define STORE(reg, addr, handler) EXC(sw, ST_INSN, reg, addr, handler) 384#define ADD addu 385#define SUB subu 386#define SRL srl 387#define SLL sll 388#define SLLV sllv 389#define SRLV srlv 390#define NBYTES 4 391#define LOG_NBYTES 2 392 393#endif /* USE_DOUBLE */ 394 395#ifdef CONFIG_CPU_LITTLE_ENDIAN 396#define LDFIRST LOADR 397#define LDREST LOADL 398#define STFIRST STORER 399#define STREST STOREL 400#define SHIFT_DISCARD SLLV 401#define SHIFT_DISCARD_REVERT SRLV 402#else 403#define LDFIRST LOADL 404#define LDREST LOADR 405#define STFIRST STOREL 406#define STREST STORER 407#define SHIFT_DISCARD SRLV 408#define SHIFT_DISCARD_REVERT SLLV 409#endif 410 411#define FIRST(unit) ((unit)*NBYTES) 412#define REST(unit) (FIRST(unit)+NBYTES-1) 413 414#define ADDRMASK (NBYTES-1) 415 416#ifndef CONFIG_CPU_DADDI_WORKAROUNDS 417 .set noat 418#else 419 .set at=v1 420#endif 421 422LEAF(__csum_partial_copy_kernel) 423FEXPORT(__csum_partial_copy_to_user) 424FEXPORT(__csum_partial_copy_from_user) 425 PTR_ADDU AT, src, len /* See (1) above. */ 426#ifdef CONFIG_64BIT 427 move errptr, a4 428#else 429 lw errptr, 16(sp) 430#endif 431FEXPORT(csum_partial_copy_nocheck) 432 move sum, zero 433 move odd, zero 434 /* 435 * Note: dst & src may be unaligned, len may be 0 436 * Temps 437 */ 438 /* 439 * The "issue break"s below are very approximate. 440 * Issue delays for dcache fills will perturb the schedule, as will 441 * load queue full replay traps, etc. 442 * 443 * If len < NBYTES use byte operations. 444 */ 445 sltu t2, len, NBYTES 446 and t1, dst, ADDRMASK 447 bnez t2, .Lcopy_bytes_checklen 448 and t0, src, ADDRMASK 449 andi odd, dst, 0x1 /* odd buffer? */ 450 bnez t1, .Ldst_unaligned 451 nop 452 bnez t0, .Lsrc_unaligned_dst_aligned 453 /* 454 * use delay slot for fall-through 455 * src and dst are aligned; need to compute rem 456 */ 457.Lboth_aligned: 458 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter 459 beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES 460 nop 461 SUB len, 8*NBYTES # subtract here for bgez loop 462 .align 4 4631: 464 LOAD(t0, UNIT(0)(src), .Ll_exc) 465 LOAD(t1, UNIT(1)(src), .Ll_exc_copy) 466 LOAD(t2, UNIT(2)(src), .Ll_exc_copy) 467 LOAD(t3, UNIT(3)(src), .Ll_exc_copy) 468 LOAD(t4, UNIT(4)(src), .Ll_exc_copy) 469 LOAD(t5, UNIT(5)(src), .Ll_exc_copy) 470 LOAD(t6, UNIT(6)(src), .Ll_exc_copy) 471 LOAD(t7, UNIT(7)(src), .Ll_exc_copy) 472 SUB len, len, 8*NBYTES 473 ADD src, src, 8*NBYTES 474 STORE(t0, UNIT(0)(dst), .Ls_exc) 475 ADDC(sum, t0) 476 STORE(t1, UNIT(1)(dst), .Ls_exc) 477 ADDC(sum, t1) 478 STORE(t2, UNIT(2)(dst), .Ls_exc) 479 ADDC(sum, t2) 480 STORE(t3, UNIT(3)(dst), .Ls_exc) 481 ADDC(sum, t3) 482 STORE(t4, UNIT(4)(dst), .Ls_exc) 483 ADDC(sum, t4) 484 STORE(t5, UNIT(5)(dst), .Ls_exc) 485 ADDC(sum, t5) 486 STORE(t6, UNIT(6)(dst), .Ls_exc) 487 ADDC(sum, t6) 488 STORE(t7, UNIT(7)(dst), .Ls_exc) 489 ADDC(sum, t7) 490 .set reorder /* DADDI_WAR */ 491 ADD dst, dst, 8*NBYTES 492 bgez len, 1b 493 .set noreorder 494 ADD len, 8*NBYTES # revert len (see above) 495 496 /* 497 * len == the number of bytes left to copy < 8*NBYTES 498 */ 499.Lcleanup_both_aligned: 500#define rem t7 501 beqz len, .Ldone 502 sltu t0, len, 4*NBYTES 503 bnez t0, .Lless_than_4units 504 and rem, len, (NBYTES-1) # rem = len % NBYTES 505 /* 506 * len >= 4*NBYTES 507 */ 508 LOAD(t0, UNIT(0)(src), .Ll_exc) 509 LOAD(t1, UNIT(1)(src), .Ll_exc_copy) 510 LOAD(t2, UNIT(2)(src), .Ll_exc_copy) 511 LOAD(t3, UNIT(3)(src), .Ll_exc_copy) 512 SUB len, len, 4*NBYTES 513 ADD src, src, 4*NBYTES 514 STORE(t0, UNIT(0)(dst), .Ls_exc) 515 ADDC(sum, t0) 516 STORE(t1, UNIT(1)(dst), .Ls_exc) 517 ADDC(sum, t1) 518 STORE(t2, UNIT(2)(dst), .Ls_exc) 519 ADDC(sum, t2) 520 STORE(t3, UNIT(3)(dst), .Ls_exc) 521 ADDC(sum, t3) 522 .set reorder /* DADDI_WAR */ 523 ADD dst, dst, 4*NBYTES 524 beqz len, .Ldone 525 .set noreorder 526.Lless_than_4units: 527 /* 528 * rem = len % NBYTES 529 */ 530 beq rem, len, .Lcopy_bytes 531 nop 5321: 533 LOAD(t0, 0(src), .Ll_exc) 534 ADD src, src, NBYTES 535 SUB len, len, NBYTES 536 STORE(t0, 0(dst), .Ls_exc) 537 ADDC(sum, t0) 538 .set reorder /* DADDI_WAR */ 539 ADD dst, dst, NBYTES 540 bne rem, len, 1b 541 .set noreorder 542 543 /* 544 * src and dst are aligned, need to copy rem bytes (rem < NBYTES) 545 * A loop would do only a byte at a time with possible branch 546 * mispredicts. Can't do an explicit LOAD dst,mask,or,STORE 547 * because can't assume read-access to dst. Instead, use 548 * STREST dst, which doesn't require read access to dst. 549 * 550 * This code should perform better than a simple loop on modern, 551 * wide-issue mips processors because the code has fewer branches and 552 * more instruction-level parallelism. 553 */ 554#define bits t2 555 beqz len, .Ldone 556 ADD t1, dst, len # t1 is just past last byte of dst 557 li bits, 8*NBYTES 558 SLL rem, len, 3 # rem = number of bits to keep 559 LOAD(t0, 0(src), .Ll_exc) 560 SUB bits, bits, rem # bits = number of bits to discard 561 SHIFT_DISCARD t0, t0, bits 562 STREST(t0, -1(t1), .Ls_exc) 563 SHIFT_DISCARD_REVERT t0, t0, bits 564 .set reorder 565 ADDC(sum, t0) 566 b .Ldone 567 .set noreorder 568.Ldst_unaligned: 569 /* 570 * dst is unaligned 571 * t0 = src & ADDRMASK 572 * t1 = dst & ADDRMASK; T1 > 0 573 * len >= NBYTES 574 * 575 * Copy enough bytes to align dst 576 * Set match = (src and dst have same alignment) 577 */ 578#define match rem 579 LDFIRST(t3, FIRST(0)(src), .Ll_exc) 580 ADD t2, zero, NBYTES 581 LDREST(t3, REST(0)(src), .Ll_exc_copy) 582 SUB t2, t2, t1 # t2 = number of bytes copied 583 xor match, t0, t1 584 STFIRST(t3, FIRST(0)(dst), .Ls_exc) 585 SLL t4, t1, 3 # t4 = number of bits to discard 586 SHIFT_DISCARD t3, t3, t4 587 /* no SHIFT_DISCARD_REVERT to handle odd buffer properly */ 588 ADDC(sum, t3) 589 beq len, t2, .Ldone 590 SUB len, len, t2 591 ADD dst, dst, t2 592 beqz match, .Lboth_aligned 593 ADD src, src, t2 594 595.Lsrc_unaligned_dst_aligned: 596 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter 597 beqz t0, .Lcleanup_src_unaligned 598 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES 5991: 600/* 601 * Avoid consecutive LD*'s to the same register since some mips 602 * implementations can't issue them in the same cycle. 603 * It's OK to load FIRST(N+1) before REST(N) because the two addresses 604 * are to the same unit (unless src is aligned, but it's not). 605 */ 606 LDFIRST(t0, FIRST(0)(src), .Ll_exc) 607 LDFIRST(t1, FIRST(1)(src), .Ll_exc_copy) 608 SUB len, len, 4*NBYTES 609 LDREST(t0, REST(0)(src), .Ll_exc_copy) 610 LDREST(t1, REST(1)(src), .Ll_exc_copy) 611 LDFIRST(t2, FIRST(2)(src), .Ll_exc_copy) 612 LDFIRST(t3, FIRST(3)(src), .Ll_exc_copy) 613 LDREST(t2, REST(2)(src), .Ll_exc_copy) 614 LDREST(t3, REST(3)(src), .Ll_exc_copy) 615 ADD src, src, 4*NBYTES 616#ifdef CONFIG_CPU_SB1 617 nop # improves slotting 618#endif 619 STORE(t0, UNIT(0)(dst), .Ls_exc) 620 ADDC(sum, t0) 621 STORE(t1, UNIT(1)(dst), .Ls_exc) 622 ADDC(sum, t1) 623 STORE(t2, UNIT(2)(dst), .Ls_exc) 624 ADDC(sum, t2) 625 STORE(t3, UNIT(3)(dst), .Ls_exc) 626 ADDC(sum, t3) 627 .set reorder /* DADDI_WAR */ 628 ADD dst, dst, 4*NBYTES 629 bne len, rem, 1b 630 .set noreorder 631 632.Lcleanup_src_unaligned: 633 beqz len, .Ldone 634 and rem, len, NBYTES-1 # rem = len % NBYTES 635 beq rem, len, .Lcopy_bytes 636 nop 6371: 638 LDFIRST(t0, FIRST(0)(src), .Ll_exc) 639 LDREST(t0, REST(0)(src), .Ll_exc_copy) 640 ADD src, src, NBYTES 641 SUB len, len, NBYTES 642 STORE(t0, 0(dst), .Ls_exc) 643 ADDC(sum, t0) 644 .set reorder /* DADDI_WAR */ 645 ADD dst, dst, NBYTES 646 bne len, rem, 1b 647 .set noreorder 648 649.Lcopy_bytes_checklen: 650 beqz len, .Ldone 651 nop 652.Lcopy_bytes: 653 /* 0 < len < NBYTES */ 654#ifdef CONFIG_CPU_LITTLE_ENDIAN 655#define SHIFT_START 0 656#define SHIFT_INC 8 657#else 658#define SHIFT_START 8*(NBYTES-1) 659#define SHIFT_INC -8 660#endif 661 move t2, zero # partial word 662 li t3, SHIFT_START # shift 663/* use .Ll_exc_copy here to return correct sum on fault */ 664#define COPY_BYTE(N) \ 665 LOADBU(t0, N(src), .Ll_exc_copy); \ 666 SUB len, len, 1; \ 667 STOREB(t0, N(dst), .Ls_exc); \ 668 SLLV t0, t0, t3; \ 669 addu t3, SHIFT_INC; \ 670 beqz len, .Lcopy_bytes_done; \ 671 or t2, t0 672 673 COPY_BYTE(0) 674 COPY_BYTE(1) 675#ifdef USE_DOUBLE 676 COPY_BYTE(2) 677 COPY_BYTE(3) 678 COPY_BYTE(4) 679 COPY_BYTE(5) 680#endif 681 LOADBU(t0, NBYTES-2(src), .Ll_exc_copy) 682 SUB len, len, 1 683 STOREB(t0, NBYTES-2(dst), .Ls_exc) 684 SLLV t0, t0, t3 685 or t2, t0 686.Lcopy_bytes_done: 687 ADDC(sum, t2) 688.Ldone: 689 /* fold checksum */ 690#ifdef USE_DOUBLE 691 dsll32 v1, sum, 0 692 daddu sum, v1 693 sltu v1, sum, v1 694 dsra32 sum, sum, 0 695 addu sum, v1 696#endif 697 698#ifdef CONFIG_CPU_MIPSR2 699 wsbh v1, sum 700 movn sum, v1, odd 701#else 702 beqz odd, 1f /* odd buffer alignment? */ 703 lui v1, 0x00ff 704 addu v1, 0x00ff 705 and t0, sum, v1 706 sll t0, t0, 8 707 srl sum, sum, 8 708 and sum, sum, v1 709 or sum, sum, t0 7101: 711#endif 712 .set reorder 713 ADDC32(sum, psum) 714 jr ra 715 .set noreorder 716 717.Ll_exc_copy: 718 /* 719 * Copy bytes from src until faulting load address (or until a 720 * lb faults) 721 * 722 * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28) 723 * may be more than a byte beyond the last address. 724 * Hence, the lb below may get an exception. 725 * 726 * Assumes src < THREAD_BUADDR($28) 727 */ 728 LOADK t0, TI_TASK($28) 729 li t2, SHIFT_START 730 LOADK t0, THREAD_BUADDR(t0) 7311: 732 LOADBU(t1, 0(src), .Ll_exc) 733 ADD src, src, 1 734 sb t1, 0(dst) # can't fault -- we're copy_from_user 735 SLLV t1, t1, t2 736 addu t2, SHIFT_INC 737 ADDC(sum, t1) 738 .set reorder /* DADDI_WAR */ 739 ADD dst, dst, 1 740 bne src, t0, 1b 741 .set noreorder 742.Ll_exc: 743 LOADK t0, TI_TASK($28) 744 nop 745 LOADK t0, THREAD_BUADDR(t0) # t0 is just past last good address 746 nop 747 SUB len, AT, t0 # len number of uncopied bytes 748 /* 749 * Here's where we rely on src and dst being incremented in tandem, 750 * See (3) above. 751 * dst += (fault addr - src) to put dst at first byte to clear 752 */ 753 ADD dst, t0 # compute start address in a1 754 SUB dst, src 755 /* 756 * Clear len bytes starting at dst. Can't call __bzero because it 757 * might modify len. An inefficient loop for these rare times... 758 */ 759 .set reorder /* DADDI_WAR */ 760 SUB src, len, 1 761 beqz len, .Ldone 762 .set noreorder 7631: sb zero, 0(dst) 764 ADD dst, dst, 1 765 .set push 766 .set noat 767#ifndef CONFIG_CPU_DADDI_WORKAROUNDS 768 bnez src, 1b 769 SUB src, src, 1 770#else 771 li v1, 1 772 bnez src, 1b 773 SUB src, src, v1 774#endif 775 li v1, -EFAULT 776 b .Ldone 777 sw v1, (errptr) 778 779.Ls_exc: 780 li v0, -1 /* invalid checksum */ 781 li v1, -EFAULT 782 jr ra 783 sw v1, (errptr) 784 .set pop 785 END(__csum_partial_copy_kernel) 786