1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * Cache operations for the cache instruction. 3384740dcSRalf Baechle * 4384740dcSRalf Baechle * This file is subject to the terms and conditions of the GNU General Public 5384740dcSRalf Baechle * License. See the file "COPYING" in the main directory of this archive 6384740dcSRalf Baechle * for more details. 7384740dcSRalf Baechle * 8384740dcSRalf Baechle * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle 9384740dcSRalf Baechle * (C) Copyright 1999 Silicon Graphics, Inc. 10384740dcSRalf Baechle */ 11384740dcSRalf Baechle #ifndef __ASM_CACHEOPS_H 12384740dcSRalf Baechle #define __ASM_CACHEOPS_H 13384740dcSRalf Baechle 14384740dcSRalf Baechle /* 15384740dcSRalf Baechle * Cache Operations available on all MIPS processors with R4000-style caches 16384740dcSRalf Baechle */ 17384740dcSRalf Baechle #define Index_Invalidate_I 0x00 18384740dcSRalf Baechle #define Index_Writeback_Inv_D 0x01 19384740dcSRalf Baechle #define Index_Load_Tag_I 0x04 20384740dcSRalf Baechle #define Index_Load_Tag_D 0x05 21384740dcSRalf Baechle #define Index_Store_Tag_I 0x08 22384740dcSRalf Baechle #define Index_Store_Tag_D 0x09 23384740dcSRalf Baechle #if defined(CONFIG_CPU_LOONGSON2) 24384740dcSRalf Baechle #define Hit_Invalidate_I 0x00 25384740dcSRalf Baechle #else 26384740dcSRalf Baechle #define Hit_Invalidate_I 0x10 27384740dcSRalf Baechle #endif 28384740dcSRalf Baechle #define Hit_Invalidate_D 0x11 29384740dcSRalf Baechle #define Hit_Writeback_Inv_D 0x15 30384740dcSRalf Baechle 31384740dcSRalf Baechle /* 32384740dcSRalf Baechle * R4000-specific cacheops 33384740dcSRalf Baechle */ 34384740dcSRalf Baechle #define Create_Dirty_Excl_D 0x0d 35384740dcSRalf Baechle #define Fill 0x14 36384740dcSRalf Baechle #define Hit_Writeback_I 0x18 37384740dcSRalf Baechle #define Hit_Writeback_D 0x19 38384740dcSRalf Baechle 39384740dcSRalf Baechle /* 40384740dcSRalf Baechle * R4000SC and R4400SC-specific cacheops 41384740dcSRalf Baechle */ 42384740dcSRalf Baechle #define Index_Invalidate_SI 0x02 43384740dcSRalf Baechle #define Index_Writeback_Inv_SD 0x03 44384740dcSRalf Baechle #define Index_Load_Tag_SI 0x06 45384740dcSRalf Baechle #define Index_Load_Tag_SD 0x07 46384740dcSRalf Baechle #define Index_Store_Tag_SI 0x0A 47384740dcSRalf Baechle #define Index_Store_Tag_SD 0x0B 48384740dcSRalf Baechle #define Create_Dirty_Excl_SD 0x0f 49384740dcSRalf Baechle #define Hit_Invalidate_SI 0x12 50384740dcSRalf Baechle #define Hit_Invalidate_SD 0x13 51384740dcSRalf Baechle #define Hit_Writeback_Inv_SD 0x17 52384740dcSRalf Baechle #define Hit_Writeback_SD 0x1b 53384740dcSRalf Baechle #define Hit_Set_Virtual_SI 0x1e 54384740dcSRalf Baechle #define Hit_Set_Virtual_SD 0x1f 55384740dcSRalf Baechle 56384740dcSRalf Baechle /* 57384740dcSRalf Baechle * R5000-specific cacheops 58384740dcSRalf Baechle */ 59384740dcSRalf Baechle #define R5K_Page_Invalidate_S 0x17 60384740dcSRalf Baechle 61384740dcSRalf Baechle /* 62384740dcSRalf Baechle * RM7000-specific cacheops 63384740dcSRalf Baechle */ 64384740dcSRalf Baechle #define Page_Invalidate_T 0x16 65*745aef5dSRicardo Mendoza #define Index_Store_Tag_T 0x0a 66*745aef5dSRicardo Mendoza #define Index_Load_Tag_T 0x06 67384740dcSRalf Baechle 68384740dcSRalf Baechle /* 69384740dcSRalf Baechle * R10000-specific cacheops 70384740dcSRalf Baechle * 71384740dcSRalf Baechle * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. 72384740dcSRalf Baechle * Most of the _S cacheops are identical to the R4000SC _SD cacheops. 73384740dcSRalf Baechle */ 74384740dcSRalf Baechle #define Index_Writeback_Inv_S 0x03 75384740dcSRalf Baechle #define Index_Load_Tag_S 0x07 76384740dcSRalf Baechle #define Index_Store_Tag_S 0x0B 77384740dcSRalf Baechle #define Hit_Invalidate_S 0x13 78384740dcSRalf Baechle #define Cache_Barrier 0x14 79384740dcSRalf Baechle #define Hit_Writeback_Inv_S 0x17 80384740dcSRalf Baechle #define Index_Load_Data_I 0x18 81384740dcSRalf Baechle #define Index_Load_Data_D 0x19 82384740dcSRalf Baechle #define Index_Load_Data_S 0x1b 83384740dcSRalf Baechle #define Index_Store_Data_I 0x1c 84384740dcSRalf Baechle #define Index_Store_Data_D 0x1d 85384740dcSRalf Baechle #define Index_Store_Data_S 0x1f 86384740dcSRalf Baechle 87384740dcSRalf Baechle #endif /* __ASM_CACHEOPS_H */ 88