1*384740dcSRalf Baechle /* 2*384740dcSRalf Baechle * Cache operations for the cache instruction. 3*384740dcSRalf Baechle * 4*384740dcSRalf Baechle * This file is subject to the terms and conditions of the GNU General Public 5*384740dcSRalf Baechle * License. See the file "COPYING" in the main directory of this archive 6*384740dcSRalf Baechle * for more details. 7*384740dcSRalf Baechle * 8*384740dcSRalf Baechle * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle 9*384740dcSRalf Baechle * (C) Copyright 1999 Silicon Graphics, Inc. 10*384740dcSRalf Baechle */ 11*384740dcSRalf Baechle #ifndef __ASM_CACHEOPS_H 12*384740dcSRalf Baechle #define __ASM_CACHEOPS_H 13*384740dcSRalf Baechle 14*384740dcSRalf Baechle /* 15*384740dcSRalf Baechle * Cache Operations available on all MIPS processors with R4000-style caches 16*384740dcSRalf Baechle */ 17*384740dcSRalf Baechle #define Index_Invalidate_I 0x00 18*384740dcSRalf Baechle #define Index_Writeback_Inv_D 0x01 19*384740dcSRalf Baechle #define Index_Load_Tag_I 0x04 20*384740dcSRalf Baechle #define Index_Load_Tag_D 0x05 21*384740dcSRalf Baechle #define Index_Store_Tag_I 0x08 22*384740dcSRalf Baechle #define Index_Store_Tag_D 0x09 23*384740dcSRalf Baechle #if defined(CONFIG_CPU_LOONGSON2) 24*384740dcSRalf Baechle #define Hit_Invalidate_I 0x00 25*384740dcSRalf Baechle #else 26*384740dcSRalf Baechle #define Hit_Invalidate_I 0x10 27*384740dcSRalf Baechle #endif 28*384740dcSRalf Baechle #define Hit_Invalidate_D 0x11 29*384740dcSRalf Baechle #define Hit_Writeback_Inv_D 0x15 30*384740dcSRalf Baechle 31*384740dcSRalf Baechle /* 32*384740dcSRalf Baechle * R4000-specific cacheops 33*384740dcSRalf Baechle */ 34*384740dcSRalf Baechle #define Create_Dirty_Excl_D 0x0d 35*384740dcSRalf Baechle #define Fill 0x14 36*384740dcSRalf Baechle #define Hit_Writeback_I 0x18 37*384740dcSRalf Baechle #define Hit_Writeback_D 0x19 38*384740dcSRalf Baechle 39*384740dcSRalf Baechle /* 40*384740dcSRalf Baechle * R4000SC and R4400SC-specific cacheops 41*384740dcSRalf Baechle */ 42*384740dcSRalf Baechle #define Index_Invalidate_SI 0x02 43*384740dcSRalf Baechle #define Index_Writeback_Inv_SD 0x03 44*384740dcSRalf Baechle #define Index_Load_Tag_SI 0x06 45*384740dcSRalf Baechle #define Index_Load_Tag_SD 0x07 46*384740dcSRalf Baechle #define Index_Store_Tag_SI 0x0A 47*384740dcSRalf Baechle #define Index_Store_Tag_SD 0x0B 48*384740dcSRalf Baechle #define Create_Dirty_Excl_SD 0x0f 49*384740dcSRalf Baechle #define Hit_Invalidate_SI 0x12 50*384740dcSRalf Baechle #define Hit_Invalidate_SD 0x13 51*384740dcSRalf Baechle #define Hit_Writeback_Inv_SD 0x17 52*384740dcSRalf Baechle #define Hit_Writeback_SD 0x1b 53*384740dcSRalf Baechle #define Hit_Set_Virtual_SI 0x1e 54*384740dcSRalf Baechle #define Hit_Set_Virtual_SD 0x1f 55*384740dcSRalf Baechle 56*384740dcSRalf Baechle /* 57*384740dcSRalf Baechle * R5000-specific cacheops 58*384740dcSRalf Baechle */ 59*384740dcSRalf Baechle #define R5K_Page_Invalidate_S 0x17 60*384740dcSRalf Baechle 61*384740dcSRalf Baechle /* 62*384740dcSRalf Baechle * RM7000-specific cacheops 63*384740dcSRalf Baechle */ 64*384740dcSRalf Baechle #define Page_Invalidate_T 0x16 65*384740dcSRalf Baechle 66*384740dcSRalf Baechle /* 67*384740dcSRalf Baechle * R10000-specific cacheops 68*384740dcSRalf Baechle * 69*384740dcSRalf Baechle * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. 70*384740dcSRalf Baechle * Most of the _S cacheops are identical to the R4000SC _SD cacheops. 71*384740dcSRalf Baechle */ 72*384740dcSRalf Baechle #define Index_Writeback_Inv_S 0x03 73*384740dcSRalf Baechle #define Index_Load_Tag_S 0x07 74*384740dcSRalf Baechle #define Index_Store_Tag_S 0x0B 75*384740dcSRalf Baechle #define Hit_Invalidate_S 0x13 76*384740dcSRalf Baechle #define Cache_Barrier 0x14 77*384740dcSRalf Baechle #define Hit_Writeback_Inv_S 0x17 78*384740dcSRalf Baechle #define Index_Load_Data_I 0x18 79*384740dcSRalf Baechle #define Index_Load_Data_D 0x19 80*384740dcSRalf Baechle #define Index_Load_Data_S 0x1b 81*384740dcSRalf Baechle #define Index_Store_Data_I 0x1c 82*384740dcSRalf Baechle #define Index_Store_Data_D 0x1d 83*384740dcSRalf Baechle #define Index_Store_Data_S 0x1f 84*384740dcSRalf Baechle 85*384740dcSRalf Baechle #endif /* __ASM_CACHEOPS_H */ 86