1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle 7 * Copyright (C) 1999 by Silicon Graphics, Inc. 8 * Copyright (C) 2001 MIPS Technologies, Inc. 9 * Copyright (C) 2002 Maciej W. Rozycki 10 * 11 * Some useful macros for MIPS assembler code 12 * 13 * Some of the routines below contain useless nops that will be optimized 14 * away by gas in -O mode. These nops are however required to fill delay 15 * slots in noreorder mode. 16 */ 17 #ifndef __ASM_ASM_H 18 #define __ASM_ASM_H 19 20 #include <asm/sgidefs.h> 21 #include <asm/asm-eva.h> 22 23 /* 24 * LEAF - declare leaf routine 25 */ 26 #define LEAF(symbol) \ 27 .globl symbol; \ 28 .align 2; \ 29 .type symbol, @function; \ 30 .ent symbol, 0; \ 31 symbol: .frame sp, 0, ra; \ 32 .cfi_startproc; \ 33 .insn 34 35 /* 36 * NESTED - declare nested routine entry point 37 */ 38 #define NESTED(symbol, framesize, rpc) \ 39 .globl symbol; \ 40 .align 2; \ 41 .type symbol, @function; \ 42 .ent symbol, 0; \ 43 symbol: .frame sp, framesize, rpc; \ 44 .cfi_startproc; \ 45 .insn 46 47 /* 48 * END - mark end of function 49 */ 50 #define END(function) \ 51 .cfi_endproc; \ 52 .end function; \ 53 .size function, .-function 54 55 /* 56 * EXPORT - export definition of symbol 57 */ 58 #define EXPORT(symbol) \ 59 .globl symbol; \ 60 symbol: 61 62 /* 63 * FEXPORT - export definition of a function symbol 64 */ 65 #define FEXPORT(symbol) \ 66 .globl symbol; \ 67 .type symbol, @function; \ 68 symbol: .insn 69 70 /* 71 * ABS - export absolute symbol 72 */ 73 #define ABS(symbol,value) \ 74 .globl symbol; \ 75 symbol = value 76 77 #define PANIC(msg) \ 78 .set push; \ 79 .set reorder; \ 80 PTR_LA a0, 8f; \ 81 jal panic; \ 82 9: b 9b; \ 83 .set pop; \ 84 TEXT(msg) 85 86 /* 87 * Print formatted string 88 */ 89 #ifdef CONFIG_PRINTK 90 #define PRINT(string) \ 91 .set push; \ 92 .set reorder; \ 93 PTR_LA a0, 8f; \ 94 jal printk; \ 95 .set pop; \ 96 TEXT(string) 97 #else 98 #define PRINT(string) 99 #endif 100 101 #define TEXT(msg) \ 102 .pushsection .data; \ 103 8: .asciiz msg; \ 104 .popsection; 105 106 /* 107 * MIPS IV pref instruction. 108 * Use with .set noreorder only! 109 * 110 * MIPS IV implementations are free to treat this as a nop. The R5000 111 * is one of them. So we should have an option not to use this instruction. 112 */ 113 #ifdef CONFIG_CPU_HAS_PREFETCH 114 115 #define PREF(hint,addr) \ 116 .set push; \ 117 .set arch=r5000; \ 118 pref hint, addr; \ 119 .set pop 120 121 #define PREFE(hint, addr) \ 122 .set push; \ 123 .set mips0; \ 124 .set eva; \ 125 prefe hint, addr; \ 126 .set pop 127 128 #define PREFX(hint,addr) \ 129 .set push; \ 130 .set arch=r5000; \ 131 prefx hint, addr; \ 132 .set pop 133 134 #else /* !CONFIG_CPU_HAS_PREFETCH */ 135 136 #define PREF(hint, addr) 137 #define PREFE(hint, addr) 138 #define PREFX(hint, addr) 139 140 #endif /* !CONFIG_CPU_HAS_PREFETCH */ 141 142 /* 143 * Stack alignment 144 */ 145 #if (_MIPS_SIM == _MIPS_SIM_ABI32) 146 #define ALSZ 7 147 #define ALMASK ~7 148 #endif 149 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) 150 #define ALSZ 15 151 #define ALMASK ~15 152 #endif 153 154 /* 155 * Macros to handle different pointer/register sizes for 32/64-bit code 156 */ 157 158 /* 159 * Size of a register 160 */ 161 #ifdef __mips64 162 #define SZREG 8 163 #else 164 #define SZREG 4 165 #endif 166 167 /* 168 * Use the following macros in assemblercode to load/store registers, 169 * pointers etc. 170 */ 171 #if (_MIPS_SIM == _MIPS_SIM_ABI32) 172 #define REG_S sw 173 #define REG_L lw 174 #define REG_SUBU subu 175 #define REG_ADDU addu 176 #endif 177 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) 178 #define REG_S sd 179 #define REG_L ld 180 #define REG_SUBU dsubu 181 #define REG_ADDU daddu 182 #endif 183 184 /* 185 * How to add/sub/load/store/shift C int variables. 186 */ 187 #if (_MIPS_SZINT == 32) 188 #define INT_ADD add 189 #define INT_ADDU addu 190 #define INT_ADDI addi 191 #define INT_ADDIU addiu 192 #define INT_SUB sub 193 #define INT_SUBU subu 194 #define INT_L lw 195 #define INT_S sw 196 #define INT_SLL sll 197 #define INT_SLLV sllv 198 #define INT_SRL srl 199 #define INT_SRLV srlv 200 #define INT_SRA sra 201 #define INT_SRAV srav 202 #endif 203 204 #if (_MIPS_SZINT == 64) 205 #define INT_ADD dadd 206 #define INT_ADDU daddu 207 #define INT_ADDI daddi 208 #define INT_ADDIU daddiu 209 #define INT_SUB dsub 210 #define INT_SUBU dsubu 211 #define INT_L ld 212 #define INT_S sd 213 #define INT_SLL dsll 214 #define INT_SLLV dsllv 215 #define INT_SRL dsrl 216 #define INT_SRLV dsrlv 217 #define INT_SRA dsra 218 #define INT_SRAV dsrav 219 #endif 220 221 /* 222 * How to add/sub/load/store/shift C long variables. 223 */ 224 #if (_MIPS_SZLONG == 32) 225 #define LONG_ADD add 226 #define LONG_ADDU addu 227 #define LONG_ADDI addi 228 #define LONG_ADDIU addiu 229 #define LONG_SUB sub 230 #define LONG_SUBU subu 231 #define LONG_L lw 232 #define LONG_S sw 233 #define LONG_SP swp 234 #define LONG_SLL sll 235 #define LONG_SLLV sllv 236 #define LONG_SRL srl 237 #define LONG_SRLV srlv 238 #define LONG_SRA sra 239 #define LONG_SRAV srav 240 241 #define LONG .word 242 #define LONGSIZE 4 243 #define LONGMASK 3 244 #define LONGLOG 2 245 #endif 246 247 #if (_MIPS_SZLONG == 64) 248 #define LONG_ADD dadd 249 #define LONG_ADDU daddu 250 #define LONG_ADDI daddi 251 #define LONG_ADDIU daddiu 252 #define LONG_SUB dsub 253 #define LONG_SUBU dsubu 254 #define LONG_L ld 255 #define LONG_S sd 256 #define LONG_SP sdp 257 #define LONG_SLL dsll 258 #define LONG_SLLV dsllv 259 #define LONG_SRL dsrl 260 #define LONG_SRLV dsrlv 261 #define LONG_SRA dsra 262 #define LONG_SRAV dsrav 263 264 #define LONG .dword 265 #define LONGSIZE 8 266 #define LONGMASK 7 267 #define LONGLOG 3 268 #endif 269 270 /* 271 * How to add/sub/load/store/shift pointers. 272 */ 273 #if (_MIPS_SZPTR == 32) 274 #define PTR_ADD add 275 #define PTR_ADDU addu 276 #define PTR_ADDI addi 277 #define PTR_ADDIU addiu 278 #define PTR_SUB sub 279 #define PTR_SUBU subu 280 #define PTR_L lw 281 #define PTR_S sw 282 #define PTR_LA la 283 #define PTR_LI li 284 #define PTR_SLL sll 285 #define PTR_SLLV sllv 286 #define PTR_SRL srl 287 #define PTR_SRLV srlv 288 #define PTR_SRA sra 289 #define PTR_SRAV srav 290 291 #define PTR_SCALESHIFT 2 292 293 #define PTR .word 294 #define PTRSIZE 4 295 #define PTRLOG 2 296 #endif 297 298 #if (_MIPS_SZPTR == 64) 299 #define PTR_ADD dadd 300 #define PTR_ADDU daddu 301 #define PTR_ADDI daddi 302 #define PTR_ADDIU daddiu 303 #define PTR_SUB dsub 304 #define PTR_SUBU dsubu 305 #define PTR_L ld 306 #define PTR_S sd 307 #define PTR_LA dla 308 #define PTR_LI dli 309 #define PTR_SLL dsll 310 #define PTR_SLLV dsllv 311 #define PTR_SRL dsrl 312 #define PTR_SRLV dsrlv 313 #define PTR_SRA dsra 314 #define PTR_SRAV dsrav 315 316 #define PTR_SCALESHIFT 3 317 318 #define PTR .dword 319 #define PTRSIZE 8 320 #define PTRLOG 3 321 #endif 322 323 /* 324 * Some cp0 registers were extended to 64bit for MIPS III. 325 */ 326 #if (_MIPS_SIM == _MIPS_SIM_ABI32) 327 #define MFC0 mfc0 328 #define MTC0 mtc0 329 #endif 330 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) 331 #define MFC0 dmfc0 332 #define MTC0 dmtc0 333 #endif 334 335 #define SSNOP sll zero, zero, 1 336 337 #ifdef CONFIG_SGI_IP28 338 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ 339 #include <asm/cacheops.h> 340 #define R10KCBARRIER(addr) cache Cache_Barrier, addr; 341 #else 342 #define R10KCBARRIER(addr) 343 #endif 344 345 #endif /* __ASM_ASM_H */ 346