1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLY__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <asm/por.h> 38 #include <linux/mmdebug.h> 39 #include <linux/mm_types.h> 40 #include <linux/sched.h> 41 #include <linux/page_table_check.h> 42 43 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 44 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 45 46 /* Set stride and tlb_level in flush_*_tlb_range */ 47 #define flush_pmd_tlb_range(vma, addr, end) \ 48 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 49 #define flush_pud_tlb_range(vma, addr, end) \ 50 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 51 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 52 53 /* 54 * Outside of a few very special situations (e.g. hibernation), we always 55 * use broadcast TLB invalidation instructions, therefore a spurious page 56 * fault on one CPU which has been handled concurrently by another CPU 57 * does not need to perform additional invalidation. 58 */ 59 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 60 61 /* 62 * ZERO_PAGE is a global shared page that is always zero: used 63 * for zero-mapped memory areas etc.. 64 */ 65 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 66 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 67 68 #define pte_ERROR(e) \ 69 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 70 71 /* 72 * Macros to convert between a physical address and its placement in a 73 * page table entry, taking care of 52-bit addresses. 74 */ 75 #ifdef CONFIG_ARM64_PA_BITS_52 76 static inline phys_addr_t __pte_to_phys(pte_t pte) 77 { 78 pte_val(pte) &= ~PTE_MAYBE_SHARED; 79 return (pte_val(pte) & PTE_ADDR_LOW) | 80 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 81 } 82 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 83 { 84 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 85 } 86 #else 87 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_LOW) 88 #define __phys_to_pte_val(phys) (phys) 89 #endif 90 91 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 92 #define pfn_pte(pfn,prot) \ 93 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 94 95 #define pte_none(pte) (!pte_val(pte)) 96 #define __pte_clear(mm, addr, ptep) \ 97 __set_pte(ptep, __pte(0)) 98 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 99 100 /* 101 * The following only work if pte_present(). Undefined behaviour otherwise. 102 */ 103 #define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte)) 104 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 105 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 106 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 107 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 108 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 109 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 110 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 111 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 112 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 113 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 114 115 #define pte_cont_addr_end(addr, end) \ 116 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 117 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 118 }) 119 120 #define pmd_cont_addr_end(addr, end) \ 121 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 122 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 123 }) 124 125 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 126 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 127 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 128 129 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 130 #define pte_present_invalid(pte) \ 131 ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID) 132 /* 133 * Execute-only user mappings do not have the PTE_USER bit set. All valid 134 * kernel mappings have the PTE_UXN bit set. 135 */ 136 #define pte_valid_not_user(pte) \ 137 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 138 /* 139 * Returns true if the pte is valid and has the contiguous bit set. 140 */ 141 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 142 /* 143 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 144 * so that we don't erroneously return false for pages that have been 145 * remapped as PROT_NONE but are yet to be flushed from the TLB. 146 * Note that we can't make any assumptions based on the state of the access 147 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 148 * TLB. 149 */ 150 #define pte_accessible(mm, pte) \ 151 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 152 153 static inline bool por_el0_allows_pkey(u8 pkey, bool write, bool execute) 154 { 155 u64 por; 156 157 if (!system_supports_poe()) 158 return true; 159 160 por = read_sysreg_s(SYS_POR_EL0); 161 162 if (write) 163 return por_elx_allows_write(por, pkey); 164 165 if (execute) 166 return por_elx_allows_exec(por, pkey); 167 168 return por_elx_allows_read(por, pkey); 169 } 170 171 /* 172 * p??_access_permitted() is true for valid user mappings (PTE_USER 173 * bit set, subject to the write permission check). For execute-only 174 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 175 * not set) must return false. PROT_NONE mappings do not have the 176 * PTE_VALID bit set. 177 */ 178 #define pte_access_permitted_no_overlay(pte, write) \ 179 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 180 #define pte_access_permitted(pte, write) \ 181 (pte_access_permitted_no_overlay(pte, write) && \ 182 por_el0_allows_pkey(FIELD_GET(PTE_PO_IDX_MASK, pte_val(pte)), write, false)) 183 #define pmd_access_permitted(pmd, write) \ 184 (pte_access_permitted(pmd_pte(pmd), (write))) 185 #define pud_access_permitted(pud, write) \ 186 (pte_access_permitted(pud_pte(pud), (write))) 187 188 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 189 { 190 pte_val(pte) &= ~pgprot_val(prot); 191 return pte; 192 } 193 194 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 195 { 196 pte_val(pte) |= pgprot_val(prot); 197 return pte; 198 } 199 200 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 201 { 202 pmd_val(pmd) &= ~pgprot_val(prot); 203 return pmd; 204 } 205 206 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 207 { 208 pmd_val(pmd) |= pgprot_val(prot); 209 return pmd; 210 } 211 212 static inline pte_t pte_mkwrite_novma(pte_t pte) 213 { 214 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 215 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 216 return pte; 217 } 218 219 static inline pte_t pte_mkclean(pte_t pte) 220 { 221 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 222 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 223 224 return pte; 225 } 226 227 static inline pte_t pte_mkdirty(pte_t pte) 228 { 229 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 230 231 if (pte_write(pte)) 232 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 233 234 return pte; 235 } 236 237 static inline pte_t pte_wrprotect(pte_t pte) 238 { 239 /* 240 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 241 * clear), set the PTE_DIRTY bit. 242 */ 243 if (pte_hw_dirty(pte)) 244 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 245 246 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 247 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 248 return pte; 249 } 250 251 static inline pte_t pte_mkold(pte_t pte) 252 { 253 return clear_pte_bit(pte, __pgprot(PTE_AF)); 254 } 255 256 static inline pte_t pte_mkyoung(pte_t pte) 257 { 258 return set_pte_bit(pte, __pgprot(PTE_AF)); 259 } 260 261 static inline pte_t pte_mkspecial(pte_t pte) 262 { 263 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 264 } 265 266 static inline pte_t pte_mkcont(pte_t pte) 267 { 268 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 269 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 270 } 271 272 static inline pte_t pte_mknoncont(pte_t pte) 273 { 274 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 275 } 276 277 static inline pte_t pte_mkpresent(pte_t pte) 278 { 279 return set_pte_bit(pte, __pgprot(PTE_VALID)); 280 } 281 282 static inline pte_t pte_mkinvalid(pte_t pte) 283 { 284 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 285 pte = clear_pte_bit(pte, __pgprot(PTE_VALID)); 286 return pte; 287 } 288 289 static inline pmd_t pmd_mkcont(pmd_t pmd) 290 { 291 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 292 } 293 294 static inline pte_t pte_mkdevmap(pte_t pte) 295 { 296 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 297 } 298 299 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 300 static inline int pte_uffd_wp(pte_t pte) 301 { 302 return !!(pte_val(pte) & PTE_UFFD_WP); 303 } 304 305 static inline pte_t pte_mkuffd_wp(pte_t pte) 306 { 307 return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD_WP))); 308 } 309 310 static inline pte_t pte_clear_uffd_wp(pte_t pte) 311 { 312 return clear_pte_bit(pte, __pgprot(PTE_UFFD_WP)); 313 } 314 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 315 316 static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 317 { 318 WRITE_ONCE(*ptep, pte); 319 } 320 321 static inline void __set_pte(pte_t *ptep, pte_t pte) 322 { 323 __set_pte_nosync(ptep, pte); 324 325 /* 326 * Only if the new pte is valid and kernel, otherwise TLB maintenance 327 * or update_mmu_cache() have the necessary barriers. 328 */ 329 if (pte_valid_not_user(pte)) { 330 dsb(ishst); 331 isb(); 332 } 333 } 334 335 static inline pte_t __ptep_get(pte_t *ptep) 336 { 337 return READ_ONCE(*ptep); 338 } 339 340 extern void __sync_icache_dcache(pte_t pteval); 341 bool pgattr_change_is_safe(pteval_t old, pteval_t new); 342 343 /* 344 * PTE bits configuration in the presence of hardware Dirty Bit Management 345 * (PTE_WRITE == PTE_DBM): 346 * 347 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 348 * 0 0 | 1 0 0 349 * 0 1 | 1 1 0 350 * 1 0 | 1 0 1 351 * 1 1 | 0 1 x 352 * 353 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 354 * the page fault mechanism. Checking the dirty status of a pte becomes: 355 * 356 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 357 */ 358 359 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 360 pte_t pte) 361 { 362 pte_t old_pte; 363 364 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 365 return; 366 367 old_pte = __ptep_get(ptep); 368 369 if (!pte_valid(old_pte) || !pte_valid(pte)) 370 return; 371 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 372 return; 373 374 /* 375 * Check for potential race with hardware updates of the pte 376 * (__ptep_set_access_flags safely changes valid ptes without going 377 * through an invalid entry). 378 */ 379 VM_WARN_ONCE(!pte_young(pte), 380 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 381 __func__, pte_val(old_pte), pte_val(pte)); 382 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 383 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 384 __func__, pte_val(old_pte), pte_val(pte)); 385 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 386 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 387 __func__, pte_val(old_pte), pte_val(pte)); 388 } 389 390 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 391 { 392 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 393 __sync_icache_dcache(pte); 394 395 /* 396 * If the PTE would provide user space access to the tags associated 397 * with it then ensure that the MTE tags are synchronised. Although 398 * pte_access_permitted_no_overlay() returns false for exec only 399 * mappings, they don't expose tags (instruction fetches don't check 400 * tags). 401 */ 402 if (system_supports_mte() && pte_access_permitted_no_overlay(pte, false) && 403 !pte_special(pte) && pte_tagged(pte)) 404 mte_sync_tags(pte, nr_pages); 405 } 406 407 /* 408 * Select all bits except the pfn 409 */ 410 #define pte_pgprot pte_pgprot 411 static inline pgprot_t pte_pgprot(pte_t pte) 412 { 413 unsigned long pfn = pte_pfn(pte); 414 415 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 416 } 417 418 #define pte_advance_pfn pte_advance_pfn 419 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 420 { 421 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 422 } 423 424 static inline void __set_ptes(struct mm_struct *mm, 425 unsigned long __always_unused addr, 426 pte_t *ptep, pte_t pte, unsigned int nr) 427 { 428 page_table_check_ptes_set(mm, ptep, pte, nr); 429 __sync_cache_and_tags(pte, nr); 430 431 for (;;) { 432 __check_safe_pte_update(mm, ptep, pte); 433 __set_pte(ptep, pte); 434 if (--nr == 0) 435 break; 436 ptep++; 437 pte = pte_advance_pfn(pte, 1); 438 } 439 } 440 441 /* 442 * Hugetlb definitions. 443 */ 444 #define HUGE_MAX_HSTATE 4 445 #define HPAGE_SHIFT PMD_SHIFT 446 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 447 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 448 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 449 450 static inline pte_t pgd_pte(pgd_t pgd) 451 { 452 return __pte(pgd_val(pgd)); 453 } 454 455 static inline pte_t p4d_pte(p4d_t p4d) 456 { 457 return __pte(p4d_val(p4d)); 458 } 459 460 static inline pte_t pud_pte(pud_t pud) 461 { 462 return __pte(pud_val(pud)); 463 } 464 465 static inline pud_t pte_pud(pte_t pte) 466 { 467 return __pud(pte_val(pte)); 468 } 469 470 static inline pmd_t pud_pmd(pud_t pud) 471 { 472 return __pmd(pud_val(pud)); 473 } 474 475 static inline pte_t pmd_pte(pmd_t pmd) 476 { 477 return __pte(pmd_val(pmd)); 478 } 479 480 static inline pmd_t pte_pmd(pte_t pte) 481 { 482 return __pmd(pte_val(pte)); 483 } 484 485 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 486 { 487 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 488 } 489 490 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 491 { 492 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 493 } 494 495 static inline pte_t pte_swp_mkexclusive(pte_t pte) 496 { 497 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 498 } 499 500 static inline int pte_swp_exclusive(pte_t pte) 501 { 502 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 503 } 504 505 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 506 { 507 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 508 } 509 510 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 511 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 512 { 513 return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 514 } 515 516 static inline int pte_swp_uffd_wp(pte_t pte) 517 { 518 return !!(pte_val(pte) & PTE_SWP_UFFD_WP); 519 } 520 521 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 522 { 523 return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 524 } 525 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 526 527 #ifdef CONFIG_NUMA_BALANCING 528 /* 529 * See the comment in include/linux/pgtable.h 530 */ 531 static inline int pte_protnone(pte_t pte) 532 { 533 /* 534 * pte_present_invalid() tells us that the pte is invalid from HW 535 * perspective but present from SW perspective, so the fields are to be 536 * interpretted as per the HW layout. The second 2 checks are the unique 537 * encoding that we use for PROT_NONE. It is insufficient to only use 538 * the first check because we share the same encoding scheme with pmds 539 * which support pmd_mkinvalid(), so can be present-invalid without 540 * being PROT_NONE. 541 */ 542 return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte); 543 } 544 545 static inline int pmd_protnone(pmd_t pmd) 546 { 547 return pte_protnone(pmd_pte(pmd)); 548 } 549 #endif 550 551 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 552 553 /* 554 * THP definitions. 555 */ 556 557 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 558 static inline int pmd_trans_huge(pmd_t pmd) 559 { 560 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 561 } 562 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 563 564 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 565 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 566 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 567 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 568 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 569 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 570 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 571 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 572 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 573 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 574 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 575 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 576 #define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd))) 577 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 578 #define pmd_uffd_wp(pmd) pte_uffd_wp(pmd_pte(pmd)) 579 #define pmd_mkuffd_wp(pmd) pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))) 580 #define pmd_clear_uffd_wp(pmd) pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))) 581 #define pmd_swp_uffd_wp(pmd) pte_swp_uffd_wp(pmd_pte(pmd)) 582 #define pmd_swp_mkuffd_wp(pmd) pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))) 583 #define pmd_swp_clear_uffd_wp(pmd) \ 584 pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))) 585 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 586 587 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 588 589 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 590 591 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 592 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 593 #endif 594 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 595 { 596 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 597 } 598 599 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 600 #define pmd_special(pte) (!!((pmd_val(pte) & PTE_SPECIAL))) 601 static inline pmd_t pmd_mkspecial(pmd_t pmd) 602 { 603 return set_pmd_bit(pmd, __pgprot(PTE_SPECIAL)); 604 } 605 #endif 606 607 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 608 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 609 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 610 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 611 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 612 613 #define pud_young(pud) pte_young(pud_pte(pud)) 614 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 615 #define pud_write(pud) pte_write(pud_pte(pud)) 616 617 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 618 619 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 620 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 621 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 622 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 623 624 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP 625 #define pud_special(pte) pte_special(pud_pte(pud)) 626 #define pud_mkspecial(pte) pte_pud(pte_mkspecial(pud_pte(pud))) 627 #endif 628 629 #define pmd_pgprot pmd_pgprot 630 static inline pgprot_t pmd_pgprot(pmd_t pmd) 631 { 632 unsigned long pfn = pmd_pfn(pmd); 633 634 return __pgprot(pmd_val(pfn_pmd(pfn, __pgprot(0))) ^ pmd_val(pmd)); 635 } 636 637 #define pud_pgprot pud_pgprot 638 static inline pgprot_t pud_pgprot(pud_t pud) 639 { 640 unsigned long pfn = pud_pfn(pud); 641 642 return __pgprot(pud_val(pfn_pud(pfn, __pgprot(0))) ^ pud_val(pud)); 643 } 644 645 static inline void __set_pte_at(struct mm_struct *mm, 646 unsigned long __always_unused addr, 647 pte_t *ptep, pte_t pte, unsigned int nr) 648 { 649 __sync_cache_and_tags(pte, nr); 650 __check_safe_pte_update(mm, ptep, pte); 651 __set_pte(ptep, pte); 652 } 653 654 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 655 pmd_t *pmdp, pmd_t pmd) 656 { 657 page_table_check_pmd_set(mm, pmdp, pmd); 658 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 659 PMD_SIZE >> PAGE_SHIFT); 660 } 661 662 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 663 pud_t *pudp, pud_t pud) 664 { 665 page_table_check_pud_set(mm, pudp, pud); 666 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 667 PUD_SIZE >> PAGE_SHIFT); 668 } 669 670 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 671 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 672 673 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 674 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 675 676 #define __pgprot_modify(prot,mask,bits) \ 677 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 678 679 #define pgprot_nx(prot) \ 680 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 681 682 /* 683 * Mark the prot value as uncacheable and unbufferable. 684 */ 685 #define pgprot_noncached(prot) \ 686 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 687 #define pgprot_writecombine(prot) \ 688 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 689 #define pgprot_device(prot) \ 690 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 691 #define pgprot_tagged(prot) \ 692 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 693 #define pgprot_mhp pgprot_tagged 694 /* 695 * DMA allocations for non-coherent devices use what the Arm architecture calls 696 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 697 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 698 * is intended for MMIO and thus forbids speculation, preserves access size, 699 * requires strict alignment and can also force write responses to come from the 700 * endpoint. 701 */ 702 #define pgprot_dmacoherent(prot) \ 703 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 704 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 705 706 #define __HAVE_PHYS_MEM_ACCESS_PROT 707 struct file; 708 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 709 unsigned long size, pgprot_t vma_prot); 710 711 #define pmd_none(pmd) (!pmd_val(pmd)) 712 713 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 714 PMD_TYPE_TABLE) 715 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 716 PMD_TYPE_SECT) 717 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 718 #define pmd_bad(pmd) (!pmd_table(pmd)) 719 720 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 721 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 722 723 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 724 static inline bool pud_sect(pud_t pud) { return false; } 725 static inline bool pud_table(pud_t pud) { return true; } 726 #else 727 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 728 PUD_TYPE_SECT) 729 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 730 PUD_TYPE_TABLE) 731 #endif 732 733 extern pgd_t init_pg_dir[]; 734 extern pgd_t init_pg_end[]; 735 extern pgd_t swapper_pg_dir[]; 736 extern pgd_t idmap_pg_dir[]; 737 extern pgd_t tramp_pg_dir[]; 738 extern pgd_t reserved_pg_dir[]; 739 740 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 741 742 static inline bool in_swapper_pgdir(void *addr) 743 { 744 return ((unsigned long)addr & PAGE_MASK) == 745 ((unsigned long)swapper_pg_dir & PAGE_MASK); 746 } 747 748 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 749 { 750 #ifdef __PAGETABLE_PMD_FOLDED 751 if (in_swapper_pgdir(pmdp)) { 752 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 753 return; 754 } 755 #endif /* __PAGETABLE_PMD_FOLDED */ 756 757 WRITE_ONCE(*pmdp, pmd); 758 759 if (pmd_valid(pmd)) { 760 dsb(ishst); 761 isb(); 762 } 763 } 764 765 static inline void pmd_clear(pmd_t *pmdp) 766 { 767 set_pmd(pmdp, __pmd(0)); 768 } 769 770 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 771 { 772 return __pmd_to_phys(pmd); 773 } 774 775 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 776 { 777 return (unsigned long)__va(pmd_page_paddr(pmd)); 778 } 779 780 /* Find an entry in the third-level page table. */ 781 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 782 783 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 784 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 785 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 786 787 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 788 789 /* use ONLY for statically allocated translation tables */ 790 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 791 792 /* 793 * Conversion functions: convert a page and protection to a page entry, 794 * and a page entry and page directory to the page they refer to. 795 */ 796 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 797 798 #if CONFIG_PGTABLE_LEVELS > 2 799 800 #define pmd_ERROR(e) \ 801 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 802 803 #define pud_none(pud) (!pud_val(pud)) 804 #define pud_bad(pud) (!pud_table(pud)) 805 #define pud_present(pud) pte_present(pud_pte(pud)) 806 #ifndef __PAGETABLE_PMD_FOLDED 807 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 808 #else 809 #define pud_leaf(pud) false 810 #endif 811 #define pud_valid(pud) pte_valid(pud_pte(pud)) 812 #define pud_user(pud) pte_user(pud_pte(pud)) 813 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 814 815 static inline bool pgtable_l4_enabled(void); 816 817 static inline void set_pud(pud_t *pudp, pud_t pud) 818 { 819 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 820 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 821 return; 822 } 823 824 WRITE_ONCE(*pudp, pud); 825 826 if (pud_valid(pud)) { 827 dsb(ishst); 828 isb(); 829 } 830 } 831 832 static inline void pud_clear(pud_t *pudp) 833 { 834 set_pud(pudp, __pud(0)); 835 } 836 837 static inline phys_addr_t pud_page_paddr(pud_t pud) 838 { 839 return __pud_to_phys(pud); 840 } 841 842 static inline pmd_t *pud_pgtable(pud_t pud) 843 { 844 return (pmd_t *)__va(pud_page_paddr(pud)); 845 } 846 847 /* Find an entry in the second-level page table. */ 848 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 849 850 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 851 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 852 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 853 854 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 855 856 /* use ONLY for statically allocated translation tables */ 857 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 858 859 #else 860 861 #define pud_valid(pud) false 862 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 863 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 864 865 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 866 #define pmd_set_fixmap(addr) NULL 867 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 868 #define pmd_clear_fixmap() 869 870 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 871 872 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 873 874 #if CONFIG_PGTABLE_LEVELS > 3 875 876 static __always_inline bool pgtable_l4_enabled(void) 877 { 878 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 879 return true; 880 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 881 return vabits_actual == VA_BITS; 882 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 883 } 884 885 static inline bool mm_pud_folded(const struct mm_struct *mm) 886 { 887 return !pgtable_l4_enabled(); 888 } 889 #define mm_pud_folded mm_pud_folded 890 891 #define pud_ERROR(e) \ 892 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 893 894 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 895 #define p4d_bad(p4d) (pgtable_l4_enabled() && !(p4d_val(p4d) & 2)) 896 #define p4d_present(p4d) (!p4d_none(p4d)) 897 898 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 899 { 900 if (in_swapper_pgdir(p4dp)) { 901 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 902 return; 903 } 904 905 WRITE_ONCE(*p4dp, p4d); 906 dsb(ishst); 907 isb(); 908 } 909 910 static inline void p4d_clear(p4d_t *p4dp) 911 { 912 if (pgtable_l4_enabled()) 913 set_p4d(p4dp, __p4d(0)); 914 } 915 916 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 917 { 918 return __p4d_to_phys(p4d); 919 } 920 921 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 922 923 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 924 { 925 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 926 } 927 928 static inline pud_t *p4d_pgtable(p4d_t p4d) 929 { 930 return (pud_t *)__va(p4d_page_paddr(p4d)); 931 } 932 933 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 934 { 935 BUG_ON(!pgtable_l4_enabled()); 936 937 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 938 } 939 940 static inline 941 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 942 { 943 if (!pgtable_l4_enabled()) 944 return p4d_to_folded_pud(p4dp, addr); 945 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 946 } 947 #define pud_offset_lockless pud_offset_lockless 948 949 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 950 { 951 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 952 } 953 #define pud_offset pud_offset 954 955 static inline pud_t *pud_set_fixmap(unsigned long addr) 956 { 957 if (!pgtable_l4_enabled()) 958 return NULL; 959 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 960 } 961 962 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 963 { 964 if (!pgtable_l4_enabled()) 965 return p4d_to_folded_pud(p4dp, addr); 966 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 967 } 968 969 static inline void pud_clear_fixmap(void) 970 { 971 if (pgtable_l4_enabled()) 972 clear_fixmap(FIX_PUD); 973 } 974 975 /* use ONLY for statically allocated translation tables */ 976 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 977 { 978 if (!pgtable_l4_enabled()) 979 return p4d_to_folded_pud(p4dp, addr); 980 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 981 } 982 983 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 984 985 #else 986 987 static inline bool pgtable_l4_enabled(void) { return false; } 988 989 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 990 991 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 992 #define pud_set_fixmap(addr) NULL 993 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 994 #define pud_clear_fixmap() 995 996 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 997 998 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 999 1000 #if CONFIG_PGTABLE_LEVELS > 4 1001 1002 static __always_inline bool pgtable_l5_enabled(void) 1003 { 1004 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 1005 return vabits_actual == VA_BITS; 1006 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 1007 } 1008 1009 static inline bool mm_p4d_folded(const struct mm_struct *mm) 1010 { 1011 return !pgtable_l5_enabled(); 1012 } 1013 #define mm_p4d_folded mm_p4d_folded 1014 1015 #define p4d_ERROR(e) \ 1016 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 1017 1018 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 1019 #define pgd_bad(pgd) (pgtable_l5_enabled() && !(pgd_val(pgd) & 2)) 1020 #define pgd_present(pgd) (!pgd_none(pgd)) 1021 1022 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 1023 { 1024 if (in_swapper_pgdir(pgdp)) { 1025 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 1026 return; 1027 } 1028 1029 WRITE_ONCE(*pgdp, pgd); 1030 dsb(ishst); 1031 isb(); 1032 } 1033 1034 static inline void pgd_clear(pgd_t *pgdp) 1035 { 1036 if (pgtable_l5_enabled()) 1037 set_pgd(pgdp, __pgd(0)); 1038 } 1039 1040 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 1041 { 1042 return __pgd_to_phys(pgd); 1043 } 1044 1045 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1046 1047 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 1048 { 1049 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 1050 } 1051 1052 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 1053 { 1054 BUG_ON(!pgtable_l5_enabled()); 1055 1056 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 1057 } 1058 1059 static inline 1060 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1061 { 1062 if (!pgtable_l5_enabled()) 1063 return pgd_to_folded_p4d(pgdp, addr); 1064 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 1065 } 1066 #define p4d_offset_lockless p4d_offset_lockless 1067 1068 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 1069 { 1070 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 1071 } 1072 1073 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 1074 { 1075 if (!pgtable_l5_enabled()) 1076 return NULL; 1077 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 1078 } 1079 1080 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 1081 { 1082 if (!pgtable_l5_enabled()) 1083 return pgd_to_folded_p4d(pgdp, addr); 1084 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 1085 } 1086 1087 static inline void p4d_clear_fixmap(void) 1088 { 1089 if (pgtable_l5_enabled()) 1090 clear_fixmap(FIX_P4D); 1091 } 1092 1093 /* use ONLY for statically allocated translation tables */ 1094 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 1095 { 1096 if (!pgtable_l5_enabled()) 1097 return pgd_to_folded_p4d(pgdp, addr); 1098 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 1099 } 1100 1101 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1102 1103 #else 1104 1105 static inline bool pgtable_l5_enabled(void) { return false; } 1106 1107 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1108 1109 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1110 #define p4d_set_fixmap(addr) NULL 1111 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1112 #define p4d_clear_fixmap() 1113 1114 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1115 1116 static inline 1117 p4d_t *p4d_offset_lockless_folded(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1118 { 1119 /* 1120 * With runtime folding of the pud, pud_offset_lockless() passes 1121 * the 'pgd_t *' we return here to p4d_to_folded_pud(), which 1122 * will offset the pointer assuming that it points into 1123 * a page-table page. However, the fast GUP path passes us a 1124 * pgd_t allocated on the stack and so we must use the original 1125 * pointer in 'pgdp' to construct the p4d pointer instead of 1126 * using the generic p4d_offset_lockless() implementation. 1127 * 1128 * Note: reusing the original pointer means that we may 1129 * dereference the same (live) page-table entry multiple times. 1130 * This is safe because it is still only loaded once in the 1131 * context of each level and the CPU guarantees same-address 1132 * read-after-read ordering. 1133 */ 1134 return p4d_offset(pgdp, addr); 1135 } 1136 #define p4d_offset_lockless p4d_offset_lockless_folded 1137 1138 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1139 1140 #define pgd_ERROR(e) \ 1141 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1142 1143 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1144 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1145 1146 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1147 { 1148 /* 1149 * Normal and Normal-Tagged are two different memory types and indices 1150 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1151 */ 1152 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1153 PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE | 1154 PTE_GP | PTE_ATTRINDX_MASK | PTE_PO_IDX_MASK; 1155 1156 /* preserve the hardware dirty information */ 1157 if (pte_hw_dirty(pte)) 1158 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1159 1160 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1161 /* 1162 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1163 * dirtiness again. 1164 */ 1165 if (pte_sw_dirty(pte)) 1166 pte = pte_mkdirty(pte); 1167 return pte; 1168 } 1169 1170 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1171 { 1172 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1173 } 1174 1175 extern int __ptep_set_access_flags(struct vm_area_struct *vma, 1176 unsigned long address, pte_t *ptep, 1177 pte_t entry, int dirty); 1178 1179 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1180 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1181 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1182 unsigned long address, pmd_t *pmdp, 1183 pmd_t entry, int dirty) 1184 { 1185 return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 1186 pmd_pte(entry), dirty); 1187 } 1188 1189 static inline int pud_devmap(pud_t pud) 1190 { 1191 return 0; 1192 } 1193 1194 static inline int pgd_devmap(pgd_t pgd) 1195 { 1196 return 0; 1197 } 1198 #endif 1199 1200 #ifdef CONFIG_PAGE_TABLE_CHECK 1201 static inline bool pte_user_accessible_page(pte_t pte) 1202 { 1203 return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte)); 1204 } 1205 1206 static inline bool pmd_user_accessible_page(pmd_t pmd) 1207 { 1208 return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1209 } 1210 1211 static inline bool pud_user_accessible_page(pud_t pud) 1212 { 1213 return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud)); 1214 } 1215 #endif 1216 1217 /* 1218 * Atomic pte/pmd modifications. 1219 */ 1220 static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 1221 unsigned long address, 1222 pte_t *ptep) 1223 { 1224 pte_t old_pte, pte; 1225 1226 pte = __ptep_get(ptep); 1227 do { 1228 old_pte = pte; 1229 pte = pte_mkold(pte); 1230 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1231 pte_val(old_pte), pte_val(pte)); 1232 } while (pte_val(pte) != pte_val(old_pte)); 1233 1234 return pte_young(pte); 1235 } 1236 1237 static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 1238 unsigned long address, pte_t *ptep) 1239 { 1240 int young = __ptep_test_and_clear_young(vma, address, ptep); 1241 1242 if (young) { 1243 /* 1244 * We can elide the trailing DSB here since the worst that can 1245 * happen is that a CPU continues to use the young entry in its 1246 * TLB and we mistakenly reclaim the associated page. The 1247 * window for such an event is bounded by the next 1248 * context-switch, which provides a DSB to complete the TLB 1249 * invalidation. 1250 */ 1251 flush_tlb_page_nosync(vma, address); 1252 } 1253 1254 return young; 1255 } 1256 1257 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1258 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1259 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1260 unsigned long address, 1261 pmd_t *pmdp) 1262 { 1263 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1264 } 1265 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1266 1267 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1268 unsigned long address, pte_t *ptep) 1269 { 1270 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1271 1272 page_table_check_pte_clear(mm, pte); 1273 1274 return pte; 1275 } 1276 1277 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1278 pte_t *ptep, unsigned int nr, int full) 1279 { 1280 for (;;) { 1281 __ptep_get_and_clear(mm, addr, ptep); 1282 if (--nr == 0) 1283 break; 1284 ptep++; 1285 addr += PAGE_SIZE; 1286 } 1287 } 1288 1289 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1290 unsigned long addr, pte_t *ptep, 1291 unsigned int nr, int full) 1292 { 1293 pte_t pte, tmp_pte; 1294 1295 pte = __ptep_get_and_clear(mm, addr, ptep); 1296 while (--nr) { 1297 ptep++; 1298 addr += PAGE_SIZE; 1299 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1300 if (pte_dirty(tmp_pte)) 1301 pte = pte_mkdirty(pte); 1302 if (pte_young(tmp_pte)) 1303 pte = pte_mkyoung(pte); 1304 } 1305 return pte; 1306 } 1307 1308 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1309 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1310 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1311 unsigned long address, pmd_t *pmdp) 1312 { 1313 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 1314 1315 page_table_check_pmd_clear(mm, pmd); 1316 1317 return pmd; 1318 } 1319 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1320 1321 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1322 unsigned long address, pte_t *ptep, 1323 pte_t pte) 1324 { 1325 pte_t old_pte; 1326 1327 do { 1328 old_pte = pte; 1329 pte = pte_wrprotect(pte); 1330 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1331 pte_val(old_pte), pte_val(pte)); 1332 } while (pte_val(pte) != pte_val(old_pte)); 1333 } 1334 1335 /* 1336 * __ptep_set_wrprotect - mark read-only while trasferring potential hardware 1337 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1338 */ 1339 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1340 unsigned long address, pte_t *ptep) 1341 { 1342 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1343 } 1344 1345 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1346 pte_t *ptep, unsigned int nr) 1347 { 1348 unsigned int i; 1349 1350 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1351 __ptep_set_wrprotect(mm, address, ptep); 1352 } 1353 1354 static inline void __clear_young_dirty_pte(struct vm_area_struct *vma, 1355 unsigned long addr, pte_t *ptep, 1356 pte_t pte, cydp_t flags) 1357 { 1358 pte_t old_pte; 1359 1360 do { 1361 old_pte = pte; 1362 1363 if (flags & CYDP_CLEAR_YOUNG) 1364 pte = pte_mkold(pte); 1365 if (flags & CYDP_CLEAR_DIRTY) 1366 pte = pte_mkclean(pte); 1367 1368 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1369 pte_val(old_pte), pte_val(pte)); 1370 } while (pte_val(pte) != pte_val(old_pte)); 1371 } 1372 1373 static inline void __clear_young_dirty_ptes(struct vm_area_struct *vma, 1374 unsigned long addr, pte_t *ptep, 1375 unsigned int nr, cydp_t flags) 1376 { 1377 pte_t pte; 1378 1379 for (;;) { 1380 pte = __ptep_get(ptep); 1381 1382 if (flags == (CYDP_CLEAR_YOUNG | CYDP_CLEAR_DIRTY)) 1383 __set_pte(ptep, pte_mkclean(pte_mkold(pte))); 1384 else 1385 __clear_young_dirty_pte(vma, addr, ptep, pte, flags); 1386 1387 if (--nr == 0) 1388 break; 1389 ptep++; 1390 addr += PAGE_SIZE; 1391 } 1392 } 1393 1394 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1395 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1396 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1397 unsigned long address, pmd_t *pmdp) 1398 { 1399 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1400 } 1401 1402 #define pmdp_establish pmdp_establish 1403 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1404 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1405 { 1406 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1407 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1408 } 1409 #endif 1410 1411 /* 1412 * Encode and decode a swap entry: 1413 * bits 0-1: present (must be zero) 1414 * bits 2: remember PG_anon_exclusive 1415 * bit 3: remember uffd-wp state 1416 * bits 6-10: swap type 1417 * bit 11: PTE_PRESENT_INVALID (must be zero) 1418 * bits 12-61: swap offset 1419 */ 1420 #define __SWP_TYPE_SHIFT 6 1421 #define __SWP_TYPE_BITS 5 1422 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1423 #define __SWP_OFFSET_SHIFT 12 1424 #define __SWP_OFFSET_BITS 50 1425 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1426 1427 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1428 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1429 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1430 1431 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1432 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1433 1434 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1435 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1436 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1437 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1438 1439 /* 1440 * Ensure that there are not more swap files than can be encoded in the kernel 1441 * PTEs. 1442 */ 1443 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1444 1445 #ifdef CONFIG_ARM64_MTE 1446 1447 #define __HAVE_ARCH_PREPARE_TO_SWAP 1448 extern int arch_prepare_to_swap(struct folio *folio); 1449 1450 #define __HAVE_ARCH_SWAP_INVALIDATE 1451 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1452 { 1453 if (system_supports_mte()) 1454 mte_invalidate_tags(type, offset); 1455 } 1456 1457 static inline void arch_swap_invalidate_area(int type) 1458 { 1459 if (system_supports_mte()) 1460 mte_invalidate_tags_area(type); 1461 } 1462 1463 #define __HAVE_ARCH_SWAP_RESTORE 1464 extern void arch_swap_restore(swp_entry_t entry, struct folio *folio); 1465 1466 #endif /* CONFIG_ARM64_MTE */ 1467 1468 /* 1469 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1470 */ 1471 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1472 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1473 unsigned int nr) 1474 { 1475 /* 1476 * We don't do anything here, so there's a very small chance of 1477 * us retaking a user fault which we just fixed up. The alternative 1478 * is doing a dsb(ishst), but that penalises the fastpath. 1479 */ 1480 } 1481 1482 #define update_mmu_cache(vma, addr, ptep) \ 1483 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1484 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1485 1486 #ifdef CONFIG_ARM64_PA_BITS_52 1487 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1488 #else 1489 #define phys_to_ttbr(addr) (addr) 1490 #endif 1491 1492 /* 1493 * On arm64 without hardware Access Flag, copying from user will fail because 1494 * the pte is old and cannot be marked young. So we always end up with zeroed 1495 * page after fork() + CoW for pfn mappings. We don't always have a 1496 * hardware-managed access flag on arm64. 1497 */ 1498 #define arch_has_hw_pte_young cpu_has_hw_af 1499 1500 /* 1501 * Experimentally, it's cheap to set the access flag in hardware and we 1502 * benefit from prefaulting mappings as 'old' to start with. 1503 */ 1504 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1505 1506 static inline bool pud_sect_supported(void) 1507 { 1508 return PAGE_SIZE == SZ_4K; 1509 } 1510 1511 1512 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1513 #define ptep_modify_prot_start ptep_modify_prot_start 1514 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1515 unsigned long addr, pte_t *ptep); 1516 1517 #define ptep_modify_prot_commit ptep_modify_prot_commit 1518 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1519 unsigned long addr, pte_t *ptep, 1520 pte_t old_pte, pte_t new_pte); 1521 1522 #ifdef CONFIG_ARM64_CONTPTE 1523 1524 /* 1525 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1526 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1527 * a private implementation detail of the public ptep API (see below). 1528 */ 1529 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1530 pte_t *ptep, pte_t pte); 1531 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1532 pte_t *ptep, pte_t pte); 1533 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1534 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1535 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1536 pte_t *ptep, pte_t pte, unsigned int nr); 1537 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1538 pte_t *ptep, unsigned int nr, int full); 1539 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1540 unsigned long addr, pte_t *ptep, 1541 unsigned int nr, int full); 1542 extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 1543 unsigned long addr, pte_t *ptep); 1544 extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 1545 unsigned long addr, pte_t *ptep); 1546 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1547 pte_t *ptep, unsigned int nr); 1548 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1549 unsigned long addr, pte_t *ptep, 1550 pte_t entry, int dirty); 1551 extern void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma, 1552 unsigned long addr, pte_t *ptep, 1553 unsigned int nr, cydp_t flags); 1554 1555 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1556 unsigned long addr, pte_t *ptep, pte_t pte) 1557 { 1558 /* 1559 * Only bother trying if both the virtual and physical addresses are 1560 * aligned and correspond to the last entry in a contig range. The core 1561 * code mostly modifies ranges from low to high, so this is the likely 1562 * the last modification in the contig range, so a good time to fold. 1563 * We can't fold special mappings, because there is no associated folio. 1564 */ 1565 1566 const unsigned long contmask = CONT_PTES - 1; 1567 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1568 1569 if (unlikely(valign)) { 1570 bool palign = (pte_pfn(pte) & contmask) == contmask; 1571 1572 if (unlikely(palign && 1573 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1574 __contpte_try_fold(mm, addr, ptep, pte); 1575 } 1576 } 1577 1578 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1579 unsigned long addr, pte_t *ptep, pte_t pte) 1580 { 1581 if (unlikely(pte_valid_cont(pte))) 1582 __contpte_try_unfold(mm, addr, ptep, pte); 1583 } 1584 1585 #define pte_batch_hint pte_batch_hint 1586 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1587 { 1588 if (!pte_valid_cont(pte)) 1589 return 1; 1590 1591 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1592 } 1593 1594 /* 1595 * The below functions constitute the public API that arm64 presents to the 1596 * core-mm to manipulate PTE entries within their page tables (or at least this 1597 * is the subset of the API that arm64 needs to implement). These public 1598 * versions will automatically and transparently apply the contiguous bit where 1599 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1600 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1601 * private versions, which are prefixed with double underscore. All of these 1602 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1603 * held. Although the contiguous bit is considered private to the 1604 * implementation, it is deliberately allowed to leak through the getters (e.g. 1605 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1606 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1607 * its possible a pte will be passed to a setter with the contiguous bit set, so 1608 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1609 * setting it in the pgtable. 1610 */ 1611 1612 #define ptep_get ptep_get 1613 static inline pte_t ptep_get(pte_t *ptep) 1614 { 1615 pte_t pte = __ptep_get(ptep); 1616 1617 if (likely(!pte_valid_cont(pte))) 1618 return pte; 1619 1620 return contpte_ptep_get(ptep, pte); 1621 } 1622 1623 #define ptep_get_lockless ptep_get_lockless 1624 static inline pte_t ptep_get_lockless(pte_t *ptep) 1625 { 1626 pte_t pte = __ptep_get(ptep); 1627 1628 if (likely(!pte_valid_cont(pte))) 1629 return pte; 1630 1631 return contpte_ptep_get_lockless(ptep); 1632 } 1633 1634 static inline void set_pte(pte_t *ptep, pte_t pte) 1635 { 1636 /* 1637 * We don't have the mm or vaddr so cannot unfold contig entries (since 1638 * it requires tlb maintenance). set_pte() is not used in core code, so 1639 * this should never even be called. Regardless do our best to service 1640 * any call and emit a warning if there is any attempt to set a pte on 1641 * top of an existing contig range. 1642 */ 1643 pte_t orig_pte = __ptep_get(ptep); 1644 1645 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1646 __set_pte(ptep, pte_mknoncont(pte)); 1647 } 1648 1649 #define set_ptes set_ptes 1650 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1651 pte_t *ptep, pte_t pte, unsigned int nr) 1652 { 1653 pte = pte_mknoncont(pte); 1654 1655 if (likely(nr == 1)) { 1656 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1657 __set_ptes(mm, addr, ptep, pte, 1); 1658 contpte_try_fold(mm, addr, ptep, pte); 1659 } else { 1660 contpte_set_ptes(mm, addr, ptep, pte, nr); 1661 } 1662 } 1663 1664 static inline void pte_clear(struct mm_struct *mm, 1665 unsigned long addr, pte_t *ptep) 1666 { 1667 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1668 __pte_clear(mm, addr, ptep); 1669 } 1670 1671 #define clear_full_ptes clear_full_ptes 1672 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1673 pte_t *ptep, unsigned int nr, int full) 1674 { 1675 if (likely(nr == 1)) { 1676 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1677 __clear_full_ptes(mm, addr, ptep, nr, full); 1678 } else { 1679 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1680 } 1681 } 1682 1683 #define get_and_clear_full_ptes get_and_clear_full_ptes 1684 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1685 unsigned long addr, pte_t *ptep, 1686 unsigned int nr, int full) 1687 { 1688 pte_t pte; 1689 1690 if (likely(nr == 1)) { 1691 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1692 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1693 } else { 1694 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1695 } 1696 1697 return pte; 1698 } 1699 1700 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1701 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1702 unsigned long addr, pte_t *ptep) 1703 { 1704 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1705 return __ptep_get_and_clear(mm, addr, ptep); 1706 } 1707 1708 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1709 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1710 unsigned long addr, pte_t *ptep) 1711 { 1712 pte_t orig_pte = __ptep_get(ptep); 1713 1714 if (likely(!pte_valid_cont(orig_pte))) 1715 return __ptep_test_and_clear_young(vma, addr, ptep); 1716 1717 return contpte_ptep_test_and_clear_young(vma, addr, ptep); 1718 } 1719 1720 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1721 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1722 unsigned long addr, pte_t *ptep) 1723 { 1724 pte_t orig_pte = __ptep_get(ptep); 1725 1726 if (likely(!pte_valid_cont(orig_pte))) 1727 return __ptep_clear_flush_young(vma, addr, ptep); 1728 1729 return contpte_ptep_clear_flush_young(vma, addr, ptep); 1730 } 1731 1732 #define wrprotect_ptes wrprotect_ptes 1733 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1734 unsigned long addr, pte_t *ptep, unsigned int nr) 1735 { 1736 if (likely(nr == 1)) { 1737 /* 1738 * Optimization: wrprotect_ptes() can only be called for present 1739 * ptes so we only need to check contig bit as condition for 1740 * unfold, and we can remove the contig bit from the pte we read 1741 * to avoid re-reading. This speeds up fork() which is sensitive 1742 * for order-0 folios. Equivalent to contpte_try_unfold(). 1743 */ 1744 pte_t orig_pte = __ptep_get(ptep); 1745 1746 if (unlikely(pte_cont(orig_pte))) { 1747 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1748 orig_pte = pte_mknoncont(orig_pte); 1749 } 1750 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1751 } else { 1752 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1753 } 1754 } 1755 1756 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1757 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1758 unsigned long addr, pte_t *ptep) 1759 { 1760 wrprotect_ptes(mm, addr, ptep, 1); 1761 } 1762 1763 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1764 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1765 unsigned long addr, pte_t *ptep, 1766 pte_t entry, int dirty) 1767 { 1768 pte_t orig_pte = __ptep_get(ptep); 1769 1770 entry = pte_mknoncont(entry); 1771 1772 if (likely(!pte_valid_cont(orig_pte))) 1773 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1774 1775 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1776 } 1777 1778 #define clear_young_dirty_ptes clear_young_dirty_ptes 1779 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 1780 unsigned long addr, pte_t *ptep, 1781 unsigned int nr, cydp_t flags) 1782 { 1783 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1784 __clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1785 else 1786 contpte_clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1787 } 1788 1789 #else /* CONFIG_ARM64_CONTPTE */ 1790 1791 #define ptep_get __ptep_get 1792 #define set_pte __set_pte 1793 #define set_ptes __set_ptes 1794 #define pte_clear __pte_clear 1795 #define clear_full_ptes __clear_full_ptes 1796 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1797 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1798 #define ptep_get_and_clear __ptep_get_and_clear 1799 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1800 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1801 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1802 #define ptep_clear_flush_young __ptep_clear_flush_young 1803 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1804 #define ptep_set_wrprotect __ptep_set_wrprotect 1805 #define wrprotect_ptes __wrprotect_ptes 1806 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1807 #define ptep_set_access_flags __ptep_set_access_flags 1808 #define clear_young_dirty_ptes __clear_young_dirty_ptes 1809 1810 #endif /* CONFIG_ARM64_CONTPTE */ 1811 1812 #endif /* !__ASSEMBLY__ */ 1813 1814 #endif /* __ASM_PGTABLE_H */ 1815