1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLY__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <asm/por.h> 38 #include <linux/mmdebug.h> 39 #include <linux/mm_types.h> 40 #include <linux/sched.h> 41 #include <linux/page_table_check.h> 42 43 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 44 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 45 46 /* Set stride and tlb_level in flush_*_tlb_range */ 47 #define flush_pmd_tlb_range(vma, addr, end) \ 48 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 49 #define flush_pud_tlb_range(vma, addr, end) \ 50 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 51 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 52 53 /* 54 * Outside of a few very special situations (e.g. hibernation), we always 55 * use broadcast TLB invalidation instructions, therefore a spurious page 56 * fault on one CPU which has been handled concurrently by another CPU 57 * does not need to perform additional invalidation. 58 */ 59 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 60 61 /* 62 * ZERO_PAGE is a global shared page that is always zero: used 63 * for zero-mapped memory areas etc.. 64 */ 65 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 66 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 67 68 #define pte_ERROR(e) \ 69 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 70 71 /* 72 * Macros to convert between a physical address and its placement in a 73 * page table entry, taking care of 52-bit addresses. 74 */ 75 #ifdef CONFIG_ARM64_PA_BITS_52 76 static inline phys_addr_t __pte_to_phys(pte_t pte) 77 { 78 pte_val(pte) &= ~PTE_MAYBE_SHARED; 79 return (pte_val(pte) & PTE_ADDR_LOW) | 80 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 81 } 82 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 83 { 84 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 85 } 86 #else 87 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_LOW) 88 #define __phys_to_pte_val(phys) (phys) 89 #endif 90 91 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 92 #define pfn_pte(pfn,prot) \ 93 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 94 95 #define pte_none(pte) (!pte_val(pte)) 96 #define __pte_clear(mm, addr, ptep) \ 97 __set_pte(ptep, __pte(0)) 98 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 99 100 /* 101 * The following only work if pte_present(). Undefined behaviour otherwise. 102 */ 103 #define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte)) 104 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 105 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 106 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 107 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 108 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 109 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 110 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 111 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 112 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 113 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 114 115 #define pte_cont_addr_end(addr, end) \ 116 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 117 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 118 }) 119 120 #define pmd_cont_addr_end(addr, end) \ 121 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 122 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 123 }) 124 125 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 126 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 127 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 128 129 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 130 #define pte_present_invalid(pte) \ 131 ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID) 132 /* 133 * Execute-only user mappings do not have the PTE_USER bit set. All valid 134 * kernel mappings have the PTE_UXN bit set. 135 */ 136 #define pte_valid_not_user(pte) \ 137 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 138 /* 139 * Returns true if the pte is valid and has the contiguous bit set. 140 */ 141 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 142 /* 143 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 144 * so that we don't erroneously return false for pages that have been 145 * remapped as PROT_NONE but are yet to be flushed from the TLB. 146 * Note that we can't make any assumptions based on the state of the access 147 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 148 * TLB. 149 */ 150 #define pte_accessible(mm, pte) \ 151 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 152 153 static inline bool por_el0_allows_pkey(u8 pkey, bool write, bool execute) 154 { 155 u64 por; 156 157 if (!system_supports_poe()) 158 return true; 159 160 por = read_sysreg_s(SYS_POR_EL0); 161 162 if (write) 163 return por_elx_allows_write(por, pkey); 164 165 if (execute) 166 return por_elx_allows_exec(por, pkey); 167 168 return por_elx_allows_read(por, pkey); 169 } 170 171 /* 172 * p??_access_permitted() is true for valid user mappings (PTE_USER 173 * bit set, subject to the write permission check). For execute-only 174 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 175 * not set) must return false. PROT_NONE mappings do not have the 176 * PTE_VALID bit set. 177 */ 178 #define pte_access_permitted_no_overlay(pte, write) \ 179 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 180 #define pte_access_permitted(pte, write) \ 181 (pte_access_permitted_no_overlay(pte, write) && \ 182 por_el0_allows_pkey(FIELD_GET(PTE_PO_IDX_MASK, pte_val(pte)), write, false)) 183 #define pmd_access_permitted(pmd, write) \ 184 (pte_access_permitted(pmd_pte(pmd), (write))) 185 #define pud_access_permitted(pud, write) \ 186 (pte_access_permitted(pud_pte(pud), (write))) 187 188 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 189 { 190 pte_val(pte) &= ~pgprot_val(prot); 191 return pte; 192 } 193 194 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 195 { 196 pte_val(pte) |= pgprot_val(prot); 197 return pte; 198 } 199 200 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 201 { 202 pmd_val(pmd) &= ~pgprot_val(prot); 203 return pmd; 204 } 205 206 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 207 { 208 pmd_val(pmd) |= pgprot_val(prot); 209 return pmd; 210 } 211 212 static inline pte_t pte_mkwrite_novma(pte_t pte) 213 { 214 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 215 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 216 return pte; 217 } 218 219 static inline pte_t pte_mkclean(pte_t pte) 220 { 221 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 222 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 223 224 return pte; 225 } 226 227 static inline pte_t pte_mkdirty(pte_t pte) 228 { 229 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 230 231 if (pte_write(pte)) 232 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 233 234 return pte; 235 } 236 237 static inline pte_t pte_wrprotect(pte_t pte) 238 { 239 /* 240 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 241 * clear), set the PTE_DIRTY bit. 242 */ 243 if (pte_hw_dirty(pte)) 244 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 245 246 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 247 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 248 return pte; 249 } 250 251 static inline pte_t pte_mkold(pte_t pte) 252 { 253 return clear_pte_bit(pte, __pgprot(PTE_AF)); 254 } 255 256 static inline pte_t pte_mkyoung(pte_t pte) 257 { 258 return set_pte_bit(pte, __pgprot(PTE_AF)); 259 } 260 261 static inline pte_t pte_mkspecial(pte_t pte) 262 { 263 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 264 } 265 266 static inline pte_t pte_mkcont(pte_t pte) 267 { 268 return set_pte_bit(pte, __pgprot(PTE_CONT)); 269 } 270 271 static inline pte_t pte_mknoncont(pte_t pte) 272 { 273 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 274 } 275 276 static inline pte_t pte_mkpresent(pte_t pte) 277 { 278 return set_pte_bit(pte, __pgprot(PTE_VALID)); 279 } 280 281 static inline pte_t pte_mkinvalid(pte_t pte) 282 { 283 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 284 pte = clear_pte_bit(pte, __pgprot(PTE_VALID)); 285 return pte; 286 } 287 288 static inline pmd_t pmd_mkcont(pmd_t pmd) 289 { 290 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 291 } 292 293 static inline pte_t pte_mkdevmap(pte_t pte) 294 { 295 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 296 } 297 298 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 299 static inline int pte_uffd_wp(pte_t pte) 300 { 301 return !!(pte_val(pte) & PTE_UFFD_WP); 302 } 303 304 static inline pte_t pte_mkuffd_wp(pte_t pte) 305 { 306 return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD_WP))); 307 } 308 309 static inline pte_t pte_clear_uffd_wp(pte_t pte) 310 { 311 return clear_pte_bit(pte, __pgprot(PTE_UFFD_WP)); 312 } 313 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 314 315 static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 316 { 317 WRITE_ONCE(*ptep, pte); 318 } 319 320 static inline void __set_pte(pte_t *ptep, pte_t pte) 321 { 322 __set_pte_nosync(ptep, pte); 323 324 /* 325 * Only if the new pte is valid and kernel, otherwise TLB maintenance 326 * or update_mmu_cache() have the necessary barriers. 327 */ 328 if (pte_valid_not_user(pte)) { 329 dsb(ishst); 330 isb(); 331 } 332 } 333 334 static inline pte_t __ptep_get(pte_t *ptep) 335 { 336 return READ_ONCE(*ptep); 337 } 338 339 extern void __sync_icache_dcache(pte_t pteval); 340 bool pgattr_change_is_safe(pteval_t old, pteval_t new); 341 342 /* 343 * PTE bits configuration in the presence of hardware Dirty Bit Management 344 * (PTE_WRITE == PTE_DBM): 345 * 346 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 347 * 0 0 | 1 0 0 348 * 0 1 | 1 1 0 349 * 1 0 | 1 0 1 350 * 1 1 | 0 1 x 351 * 352 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 353 * the page fault mechanism. Checking the dirty status of a pte becomes: 354 * 355 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 356 */ 357 358 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 359 pte_t pte) 360 { 361 pte_t old_pte; 362 363 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 364 return; 365 366 old_pte = __ptep_get(ptep); 367 368 if (!pte_valid(old_pte) || !pte_valid(pte)) 369 return; 370 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 371 return; 372 373 /* 374 * Check for potential race with hardware updates of the pte 375 * (__ptep_set_access_flags safely changes valid ptes without going 376 * through an invalid entry). 377 */ 378 VM_WARN_ONCE(!pte_young(pte), 379 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 380 __func__, pte_val(old_pte), pte_val(pte)); 381 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 382 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 383 __func__, pte_val(old_pte), pte_val(pte)); 384 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 385 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 386 __func__, pte_val(old_pte), pte_val(pte)); 387 } 388 389 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 390 { 391 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 392 __sync_icache_dcache(pte); 393 394 /* 395 * If the PTE would provide user space access to the tags associated 396 * with it then ensure that the MTE tags are synchronised. Although 397 * pte_access_permitted_no_overlay() returns false for exec only 398 * mappings, they don't expose tags (instruction fetches don't check 399 * tags). 400 */ 401 if (system_supports_mte() && pte_access_permitted_no_overlay(pte, false) && 402 !pte_special(pte) && pte_tagged(pte)) 403 mte_sync_tags(pte, nr_pages); 404 } 405 406 /* 407 * Select all bits except the pfn 408 */ 409 #define pte_pgprot pte_pgprot 410 static inline pgprot_t pte_pgprot(pte_t pte) 411 { 412 unsigned long pfn = pte_pfn(pte); 413 414 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 415 } 416 417 #define pte_advance_pfn pte_advance_pfn 418 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 419 { 420 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 421 } 422 423 static inline void __set_ptes(struct mm_struct *mm, 424 unsigned long __always_unused addr, 425 pte_t *ptep, pte_t pte, unsigned int nr) 426 { 427 page_table_check_ptes_set(mm, ptep, pte, nr); 428 __sync_cache_and_tags(pte, nr); 429 430 for (;;) { 431 __check_safe_pte_update(mm, ptep, pte); 432 __set_pte(ptep, pte); 433 if (--nr == 0) 434 break; 435 ptep++; 436 pte = pte_advance_pfn(pte, 1); 437 } 438 } 439 440 /* 441 * Hugetlb definitions. 442 */ 443 #define HUGE_MAX_HSTATE 4 444 #define HPAGE_SHIFT PMD_SHIFT 445 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 446 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 447 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 448 449 static inline pte_t pgd_pte(pgd_t pgd) 450 { 451 return __pte(pgd_val(pgd)); 452 } 453 454 static inline pte_t p4d_pte(p4d_t p4d) 455 { 456 return __pte(p4d_val(p4d)); 457 } 458 459 static inline pte_t pud_pte(pud_t pud) 460 { 461 return __pte(pud_val(pud)); 462 } 463 464 static inline pud_t pte_pud(pte_t pte) 465 { 466 return __pud(pte_val(pte)); 467 } 468 469 static inline pmd_t pud_pmd(pud_t pud) 470 { 471 return __pmd(pud_val(pud)); 472 } 473 474 static inline pte_t pmd_pte(pmd_t pmd) 475 { 476 return __pte(pmd_val(pmd)); 477 } 478 479 static inline pmd_t pte_pmd(pte_t pte) 480 { 481 return __pmd(pte_val(pte)); 482 } 483 484 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 485 { 486 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 487 } 488 489 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 490 { 491 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 492 } 493 494 static inline pte_t pte_swp_mkexclusive(pte_t pte) 495 { 496 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 497 } 498 499 static inline int pte_swp_exclusive(pte_t pte) 500 { 501 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 502 } 503 504 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 505 { 506 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 507 } 508 509 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 510 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 511 { 512 return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 513 } 514 515 static inline int pte_swp_uffd_wp(pte_t pte) 516 { 517 return !!(pte_val(pte) & PTE_SWP_UFFD_WP); 518 } 519 520 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 521 { 522 return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 523 } 524 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 525 526 #ifdef CONFIG_NUMA_BALANCING 527 /* 528 * See the comment in include/linux/pgtable.h 529 */ 530 static inline int pte_protnone(pte_t pte) 531 { 532 /* 533 * pte_present_invalid() tells us that the pte is invalid from HW 534 * perspective but present from SW perspective, so the fields are to be 535 * interpretted as per the HW layout. The second 2 checks are the unique 536 * encoding that we use for PROT_NONE. It is insufficient to only use 537 * the first check because we share the same encoding scheme with pmds 538 * which support pmd_mkinvalid(), so can be present-invalid without 539 * being PROT_NONE. 540 */ 541 return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte); 542 } 543 544 static inline int pmd_protnone(pmd_t pmd) 545 { 546 return pte_protnone(pmd_pte(pmd)); 547 } 548 #endif 549 550 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 551 552 /* 553 * THP definitions. 554 */ 555 556 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 557 static inline int pmd_trans_huge(pmd_t pmd) 558 { 559 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 560 } 561 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 562 563 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 564 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 565 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 566 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 567 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 568 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 569 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 570 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 571 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 572 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 573 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 574 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 575 #define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd))) 576 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 577 #define pmd_uffd_wp(pmd) pte_uffd_wp(pmd_pte(pmd)) 578 #define pmd_mkuffd_wp(pmd) pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))) 579 #define pmd_clear_uffd_wp(pmd) pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))) 580 #define pmd_swp_uffd_wp(pmd) pte_swp_uffd_wp(pmd_pte(pmd)) 581 #define pmd_swp_mkuffd_wp(pmd) pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))) 582 #define pmd_swp_clear_uffd_wp(pmd) \ 583 pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))) 584 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 585 586 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 587 588 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 589 590 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 591 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 592 #endif 593 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 594 { 595 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 596 } 597 598 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 599 #define pmd_special(pte) (!!((pmd_val(pte) & PTE_SPECIAL))) 600 static inline pmd_t pmd_mkspecial(pmd_t pmd) 601 { 602 return set_pmd_bit(pmd, __pgprot(PTE_SPECIAL)); 603 } 604 #endif 605 606 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 607 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 608 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 609 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 610 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 611 612 #define pud_young(pud) pte_young(pud_pte(pud)) 613 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 614 #define pud_write(pud) pte_write(pud_pte(pud)) 615 616 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 617 618 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 619 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 620 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 621 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 622 623 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP 624 #define pud_special(pte) pte_special(pud_pte(pud)) 625 #define pud_mkspecial(pte) pte_pud(pte_mkspecial(pud_pte(pud))) 626 #endif 627 628 #define pmd_pgprot pmd_pgprot 629 static inline pgprot_t pmd_pgprot(pmd_t pmd) 630 { 631 unsigned long pfn = pmd_pfn(pmd); 632 633 return __pgprot(pmd_val(pfn_pmd(pfn, __pgprot(0))) ^ pmd_val(pmd)); 634 } 635 636 #define pud_pgprot pud_pgprot 637 static inline pgprot_t pud_pgprot(pud_t pud) 638 { 639 unsigned long pfn = pud_pfn(pud); 640 641 return __pgprot(pud_val(pfn_pud(pfn, __pgprot(0))) ^ pud_val(pud)); 642 } 643 644 static inline void __set_pte_at(struct mm_struct *mm, 645 unsigned long __always_unused addr, 646 pte_t *ptep, pte_t pte, unsigned int nr) 647 { 648 __sync_cache_and_tags(pte, nr); 649 __check_safe_pte_update(mm, ptep, pte); 650 __set_pte(ptep, pte); 651 } 652 653 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 654 pmd_t *pmdp, pmd_t pmd) 655 { 656 page_table_check_pmd_set(mm, pmdp, pmd); 657 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 658 PMD_SIZE >> PAGE_SHIFT); 659 } 660 661 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 662 pud_t *pudp, pud_t pud) 663 { 664 page_table_check_pud_set(mm, pudp, pud); 665 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 666 PUD_SIZE >> PAGE_SHIFT); 667 } 668 669 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 670 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 671 672 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 673 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 674 675 #define __pgprot_modify(prot,mask,bits) \ 676 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 677 678 #define pgprot_nx(prot) \ 679 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 680 681 /* 682 * Mark the prot value as uncacheable and unbufferable. 683 */ 684 #define pgprot_noncached(prot) \ 685 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 686 #define pgprot_writecombine(prot) \ 687 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 688 #define pgprot_device(prot) \ 689 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 690 #define pgprot_tagged(prot) \ 691 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 692 #define pgprot_mhp pgprot_tagged 693 /* 694 * DMA allocations for non-coherent devices use what the Arm architecture calls 695 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 696 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 697 * is intended for MMIO and thus forbids speculation, preserves access size, 698 * requires strict alignment and can also force write responses to come from the 699 * endpoint. 700 */ 701 #define pgprot_dmacoherent(prot) \ 702 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 703 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 704 705 #define __HAVE_PHYS_MEM_ACCESS_PROT 706 struct file; 707 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 708 unsigned long size, pgprot_t vma_prot); 709 710 #define pmd_none(pmd) (!pmd_val(pmd)) 711 712 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 713 PMD_TYPE_TABLE) 714 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 715 PMD_TYPE_SECT) 716 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 717 #define pmd_bad(pmd) (!pmd_table(pmd)) 718 719 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 720 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 721 722 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 723 static inline bool pud_sect(pud_t pud) { return false; } 724 static inline bool pud_table(pud_t pud) { return true; } 725 #else 726 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 727 PUD_TYPE_SECT) 728 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 729 PUD_TYPE_TABLE) 730 #endif 731 732 extern pgd_t init_pg_dir[]; 733 extern pgd_t init_pg_end[]; 734 extern pgd_t swapper_pg_dir[]; 735 extern pgd_t idmap_pg_dir[]; 736 extern pgd_t tramp_pg_dir[]; 737 extern pgd_t reserved_pg_dir[]; 738 739 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 740 741 static inline bool in_swapper_pgdir(void *addr) 742 { 743 return ((unsigned long)addr & PAGE_MASK) == 744 ((unsigned long)swapper_pg_dir & PAGE_MASK); 745 } 746 747 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 748 { 749 #ifdef __PAGETABLE_PMD_FOLDED 750 if (in_swapper_pgdir(pmdp)) { 751 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 752 return; 753 } 754 #endif /* __PAGETABLE_PMD_FOLDED */ 755 756 WRITE_ONCE(*pmdp, pmd); 757 758 if (pmd_valid(pmd)) { 759 dsb(ishst); 760 isb(); 761 } 762 } 763 764 static inline void pmd_clear(pmd_t *pmdp) 765 { 766 set_pmd(pmdp, __pmd(0)); 767 } 768 769 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 770 { 771 return __pmd_to_phys(pmd); 772 } 773 774 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 775 { 776 return (unsigned long)__va(pmd_page_paddr(pmd)); 777 } 778 779 /* Find an entry in the third-level page table. */ 780 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 781 782 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 783 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 784 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 785 786 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 787 788 /* use ONLY for statically allocated translation tables */ 789 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 790 791 /* 792 * Conversion functions: convert a page and protection to a page entry, 793 * and a page entry and page directory to the page they refer to. 794 */ 795 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 796 797 #if CONFIG_PGTABLE_LEVELS > 2 798 799 #define pmd_ERROR(e) \ 800 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 801 802 #define pud_none(pud) (!pud_val(pud)) 803 #define pud_bad(pud) (!pud_table(pud)) 804 #define pud_present(pud) pte_present(pud_pte(pud)) 805 #ifndef __PAGETABLE_PMD_FOLDED 806 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 807 #else 808 #define pud_leaf(pud) false 809 #endif 810 #define pud_valid(pud) pte_valid(pud_pte(pud)) 811 #define pud_user(pud) pte_user(pud_pte(pud)) 812 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 813 814 static inline bool pgtable_l4_enabled(void); 815 816 static inline void set_pud(pud_t *pudp, pud_t pud) 817 { 818 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 819 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 820 return; 821 } 822 823 WRITE_ONCE(*pudp, pud); 824 825 if (pud_valid(pud)) { 826 dsb(ishst); 827 isb(); 828 } 829 } 830 831 static inline void pud_clear(pud_t *pudp) 832 { 833 set_pud(pudp, __pud(0)); 834 } 835 836 static inline phys_addr_t pud_page_paddr(pud_t pud) 837 { 838 return __pud_to_phys(pud); 839 } 840 841 static inline pmd_t *pud_pgtable(pud_t pud) 842 { 843 return (pmd_t *)__va(pud_page_paddr(pud)); 844 } 845 846 /* Find an entry in the second-level page table. */ 847 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 848 849 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 850 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 851 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 852 853 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 854 855 /* use ONLY for statically allocated translation tables */ 856 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 857 858 #else 859 860 #define pud_valid(pud) false 861 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 862 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 863 864 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 865 #define pmd_set_fixmap(addr) NULL 866 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 867 #define pmd_clear_fixmap() 868 869 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 870 871 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 872 873 #if CONFIG_PGTABLE_LEVELS > 3 874 875 static __always_inline bool pgtable_l4_enabled(void) 876 { 877 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 878 return true; 879 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 880 return vabits_actual == VA_BITS; 881 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 882 } 883 884 static inline bool mm_pud_folded(const struct mm_struct *mm) 885 { 886 return !pgtable_l4_enabled(); 887 } 888 #define mm_pud_folded mm_pud_folded 889 890 #define pud_ERROR(e) \ 891 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 892 893 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 894 #define p4d_bad(p4d) (pgtable_l4_enabled() && !(p4d_val(p4d) & 2)) 895 #define p4d_present(p4d) (!p4d_none(p4d)) 896 897 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 898 { 899 if (in_swapper_pgdir(p4dp)) { 900 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 901 return; 902 } 903 904 WRITE_ONCE(*p4dp, p4d); 905 dsb(ishst); 906 isb(); 907 } 908 909 static inline void p4d_clear(p4d_t *p4dp) 910 { 911 if (pgtable_l4_enabled()) 912 set_p4d(p4dp, __p4d(0)); 913 } 914 915 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 916 { 917 return __p4d_to_phys(p4d); 918 } 919 920 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 921 922 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 923 { 924 /* Ensure that 'p4dp' indexes a page table according to 'addr' */ 925 VM_BUG_ON(((addr >> P4D_SHIFT) ^ ((u64)p4dp >> 3)) % PTRS_PER_P4D); 926 927 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 928 } 929 930 static inline pud_t *p4d_pgtable(p4d_t p4d) 931 { 932 return (pud_t *)__va(p4d_page_paddr(p4d)); 933 } 934 935 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 936 { 937 BUG_ON(!pgtable_l4_enabled()); 938 939 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 940 } 941 942 static inline 943 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 944 { 945 if (!pgtable_l4_enabled()) 946 return p4d_to_folded_pud(p4dp, addr); 947 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 948 } 949 #define pud_offset_lockless pud_offset_lockless 950 951 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 952 { 953 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 954 } 955 #define pud_offset pud_offset 956 957 static inline pud_t *pud_set_fixmap(unsigned long addr) 958 { 959 if (!pgtable_l4_enabled()) 960 return NULL; 961 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 962 } 963 964 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 965 { 966 if (!pgtable_l4_enabled()) 967 return p4d_to_folded_pud(p4dp, addr); 968 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 969 } 970 971 static inline void pud_clear_fixmap(void) 972 { 973 if (pgtable_l4_enabled()) 974 clear_fixmap(FIX_PUD); 975 } 976 977 /* use ONLY for statically allocated translation tables */ 978 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 979 { 980 if (!pgtable_l4_enabled()) 981 return p4d_to_folded_pud(p4dp, addr); 982 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 983 } 984 985 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 986 987 #else 988 989 static inline bool pgtable_l4_enabled(void) { return false; } 990 991 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 992 993 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 994 #define pud_set_fixmap(addr) NULL 995 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 996 #define pud_clear_fixmap() 997 998 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 999 1000 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 1001 1002 #if CONFIG_PGTABLE_LEVELS > 4 1003 1004 static __always_inline bool pgtable_l5_enabled(void) 1005 { 1006 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 1007 return vabits_actual == VA_BITS; 1008 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 1009 } 1010 1011 static inline bool mm_p4d_folded(const struct mm_struct *mm) 1012 { 1013 return !pgtable_l5_enabled(); 1014 } 1015 #define mm_p4d_folded mm_p4d_folded 1016 1017 #define p4d_ERROR(e) \ 1018 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 1019 1020 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 1021 #define pgd_bad(pgd) (pgtable_l5_enabled() && !(pgd_val(pgd) & 2)) 1022 #define pgd_present(pgd) (!pgd_none(pgd)) 1023 1024 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 1025 { 1026 if (in_swapper_pgdir(pgdp)) { 1027 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 1028 return; 1029 } 1030 1031 WRITE_ONCE(*pgdp, pgd); 1032 dsb(ishst); 1033 isb(); 1034 } 1035 1036 static inline void pgd_clear(pgd_t *pgdp) 1037 { 1038 if (pgtable_l5_enabled()) 1039 set_pgd(pgdp, __pgd(0)); 1040 } 1041 1042 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 1043 { 1044 return __pgd_to_phys(pgd); 1045 } 1046 1047 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1048 1049 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 1050 { 1051 /* Ensure that 'pgdp' indexes a page table according to 'addr' */ 1052 VM_BUG_ON(((addr >> PGDIR_SHIFT) ^ ((u64)pgdp >> 3)) % PTRS_PER_PGD); 1053 1054 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 1055 } 1056 1057 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 1058 { 1059 BUG_ON(!pgtable_l5_enabled()); 1060 1061 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 1062 } 1063 1064 static inline 1065 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1066 { 1067 if (!pgtable_l5_enabled()) 1068 return pgd_to_folded_p4d(pgdp, addr); 1069 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 1070 } 1071 #define p4d_offset_lockless p4d_offset_lockless 1072 1073 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 1074 { 1075 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 1076 } 1077 1078 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 1079 { 1080 if (!pgtable_l5_enabled()) 1081 return NULL; 1082 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 1083 } 1084 1085 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 1086 { 1087 if (!pgtable_l5_enabled()) 1088 return pgd_to_folded_p4d(pgdp, addr); 1089 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 1090 } 1091 1092 static inline void p4d_clear_fixmap(void) 1093 { 1094 if (pgtable_l5_enabled()) 1095 clear_fixmap(FIX_P4D); 1096 } 1097 1098 /* use ONLY for statically allocated translation tables */ 1099 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 1100 { 1101 if (!pgtable_l5_enabled()) 1102 return pgd_to_folded_p4d(pgdp, addr); 1103 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 1104 } 1105 1106 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1107 1108 #else 1109 1110 static inline bool pgtable_l5_enabled(void) { return false; } 1111 1112 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1113 1114 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1115 #define p4d_set_fixmap(addr) NULL 1116 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1117 #define p4d_clear_fixmap() 1118 1119 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1120 1121 static inline 1122 p4d_t *p4d_offset_lockless_folded(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1123 { 1124 /* 1125 * With runtime folding of the pud, pud_offset_lockless() passes 1126 * the 'pgd_t *' we return here to p4d_to_folded_pud(), which 1127 * will offset the pointer assuming that it points into 1128 * a page-table page. However, the fast GUP path passes us a 1129 * pgd_t allocated on the stack and so we must use the original 1130 * pointer in 'pgdp' to construct the p4d pointer instead of 1131 * using the generic p4d_offset_lockless() implementation. 1132 * 1133 * Note: reusing the original pointer means that we may 1134 * dereference the same (live) page-table entry multiple times. 1135 * This is safe because it is still only loaded once in the 1136 * context of each level and the CPU guarantees same-address 1137 * read-after-read ordering. 1138 */ 1139 return p4d_offset(pgdp, addr); 1140 } 1141 #define p4d_offset_lockless p4d_offset_lockless_folded 1142 1143 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1144 1145 #define pgd_ERROR(e) \ 1146 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1147 1148 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1149 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1150 1151 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1152 { 1153 /* 1154 * Normal and Normal-Tagged are two different memory types and indices 1155 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1156 */ 1157 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1158 PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE | 1159 PTE_GP | PTE_ATTRINDX_MASK | PTE_PO_IDX_MASK; 1160 1161 /* preserve the hardware dirty information */ 1162 if (pte_hw_dirty(pte)) 1163 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1164 1165 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1166 /* 1167 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1168 * dirtiness again. 1169 */ 1170 if (pte_sw_dirty(pte)) 1171 pte = pte_mkdirty(pte); 1172 return pte; 1173 } 1174 1175 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1176 { 1177 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1178 } 1179 1180 extern int __ptep_set_access_flags(struct vm_area_struct *vma, 1181 unsigned long address, pte_t *ptep, 1182 pte_t entry, int dirty); 1183 1184 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1185 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1186 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1187 unsigned long address, pmd_t *pmdp, 1188 pmd_t entry, int dirty) 1189 { 1190 return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 1191 pmd_pte(entry), dirty); 1192 } 1193 1194 static inline int pud_devmap(pud_t pud) 1195 { 1196 return 0; 1197 } 1198 1199 static inline int pgd_devmap(pgd_t pgd) 1200 { 1201 return 0; 1202 } 1203 #endif 1204 1205 #ifdef CONFIG_PAGE_TABLE_CHECK 1206 static inline bool pte_user_accessible_page(pte_t pte) 1207 { 1208 return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte)); 1209 } 1210 1211 static inline bool pmd_user_accessible_page(pmd_t pmd) 1212 { 1213 return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1214 } 1215 1216 static inline bool pud_user_accessible_page(pud_t pud) 1217 { 1218 return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud)); 1219 } 1220 #endif 1221 1222 /* 1223 * Atomic pte/pmd modifications. 1224 */ 1225 static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 1226 unsigned long address, 1227 pte_t *ptep) 1228 { 1229 pte_t old_pte, pte; 1230 1231 pte = __ptep_get(ptep); 1232 do { 1233 old_pte = pte; 1234 pte = pte_mkold(pte); 1235 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1236 pte_val(old_pte), pte_val(pte)); 1237 } while (pte_val(pte) != pte_val(old_pte)); 1238 1239 return pte_young(pte); 1240 } 1241 1242 static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 1243 unsigned long address, pte_t *ptep) 1244 { 1245 int young = __ptep_test_and_clear_young(vma, address, ptep); 1246 1247 if (young) { 1248 /* 1249 * We can elide the trailing DSB here since the worst that can 1250 * happen is that a CPU continues to use the young entry in its 1251 * TLB and we mistakenly reclaim the associated page. The 1252 * window for such an event is bounded by the next 1253 * context-switch, which provides a DSB to complete the TLB 1254 * invalidation. 1255 */ 1256 flush_tlb_page_nosync(vma, address); 1257 } 1258 1259 return young; 1260 } 1261 1262 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1263 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1264 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1265 unsigned long address, 1266 pmd_t *pmdp) 1267 { 1268 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1269 } 1270 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1271 1272 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1273 unsigned long address, pte_t *ptep) 1274 { 1275 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1276 1277 page_table_check_pte_clear(mm, pte); 1278 1279 return pte; 1280 } 1281 1282 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1283 pte_t *ptep, unsigned int nr, int full) 1284 { 1285 for (;;) { 1286 __ptep_get_and_clear(mm, addr, ptep); 1287 if (--nr == 0) 1288 break; 1289 ptep++; 1290 addr += PAGE_SIZE; 1291 } 1292 } 1293 1294 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1295 unsigned long addr, pte_t *ptep, 1296 unsigned int nr, int full) 1297 { 1298 pte_t pte, tmp_pte; 1299 1300 pte = __ptep_get_and_clear(mm, addr, ptep); 1301 while (--nr) { 1302 ptep++; 1303 addr += PAGE_SIZE; 1304 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1305 if (pte_dirty(tmp_pte)) 1306 pte = pte_mkdirty(pte); 1307 if (pte_young(tmp_pte)) 1308 pte = pte_mkyoung(pte); 1309 } 1310 return pte; 1311 } 1312 1313 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1314 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1315 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1316 unsigned long address, pmd_t *pmdp) 1317 { 1318 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 1319 1320 page_table_check_pmd_clear(mm, pmd); 1321 1322 return pmd; 1323 } 1324 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1325 1326 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1327 unsigned long address, pte_t *ptep, 1328 pte_t pte) 1329 { 1330 pte_t old_pte; 1331 1332 do { 1333 old_pte = pte; 1334 pte = pte_wrprotect(pte); 1335 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1336 pte_val(old_pte), pte_val(pte)); 1337 } while (pte_val(pte) != pte_val(old_pte)); 1338 } 1339 1340 /* 1341 * __ptep_set_wrprotect - mark read-only while trasferring potential hardware 1342 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1343 */ 1344 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1345 unsigned long address, pte_t *ptep) 1346 { 1347 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1348 } 1349 1350 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1351 pte_t *ptep, unsigned int nr) 1352 { 1353 unsigned int i; 1354 1355 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1356 __ptep_set_wrprotect(mm, address, ptep); 1357 } 1358 1359 static inline void __clear_young_dirty_pte(struct vm_area_struct *vma, 1360 unsigned long addr, pte_t *ptep, 1361 pte_t pte, cydp_t flags) 1362 { 1363 pte_t old_pte; 1364 1365 do { 1366 old_pte = pte; 1367 1368 if (flags & CYDP_CLEAR_YOUNG) 1369 pte = pte_mkold(pte); 1370 if (flags & CYDP_CLEAR_DIRTY) 1371 pte = pte_mkclean(pte); 1372 1373 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1374 pte_val(old_pte), pte_val(pte)); 1375 } while (pte_val(pte) != pte_val(old_pte)); 1376 } 1377 1378 static inline void __clear_young_dirty_ptes(struct vm_area_struct *vma, 1379 unsigned long addr, pte_t *ptep, 1380 unsigned int nr, cydp_t flags) 1381 { 1382 pte_t pte; 1383 1384 for (;;) { 1385 pte = __ptep_get(ptep); 1386 1387 if (flags == (CYDP_CLEAR_YOUNG | CYDP_CLEAR_DIRTY)) 1388 __set_pte(ptep, pte_mkclean(pte_mkold(pte))); 1389 else 1390 __clear_young_dirty_pte(vma, addr, ptep, pte, flags); 1391 1392 if (--nr == 0) 1393 break; 1394 ptep++; 1395 addr += PAGE_SIZE; 1396 } 1397 } 1398 1399 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1400 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1401 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1402 unsigned long address, pmd_t *pmdp) 1403 { 1404 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1405 } 1406 1407 #define pmdp_establish pmdp_establish 1408 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1409 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1410 { 1411 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1412 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1413 } 1414 #endif 1415 1416 /* 1417 * Encode and decode a swap entry: 1418 * bits 0-1: present (must be zero) 1419 * bits 2: remember PG_anon_exclusive 1420 * bit 3: remember uffd-wp state 1421 * bits 6-10: swap type 1422 * bit 11: PTE_PRESENT_INVALID (must be zero) 1423 * bits 12-61: swap offset 1424 */ 1425 #define __SWP_TYPE_SHIFT 6 1426 #define __SWP_TYPE_BITS 5 1427 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1428 #define __SWP_OFFSET_SHIFT 12 1429 #define __SWP_OFFSET_BITS 50 1430 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1431 1432 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1433 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1434 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1435 1436 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1437 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1438 1439 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1440 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1441 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1442 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1443 1444 /* 1445 * Ensure that there are not more swap files than can be encoded in the kernel 1446 * PTEs. 1447 */ 1448 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1449 1450 #ifdef CONFIG_ARM64_MTE 1451 1452 #define __HAVE_ARCH_PREPARE_TO_SWAP 1453 extern int arch_prepare_to_swap(struct folio *folio); 1454 1455 #define __HAVE_ARCH_SWAP_INVALIDATE 1456 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1457 { 1458 if (system_supports_mte()) 1459 mte_invalidate_tags(type, offset); 1460 } 1461 1462 static inline void arch_swap_invalidate_area(int type) 1463 { 1464 if (system_supports_mte()) 1465 mte_invalidate_tags_area(type); 1466 } 1467 1468 #define __HAVE_ARCH_SWAP_RESTORE 1469 extern void arch_swap_restore(swp_entry_t entry, struct folio *folio); 1470 1471 #endif /* CONFIG_ARM64_MTE */ 1472 1473 /* 1474 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1475 */ 1476 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1477 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1478 unsigned int nr) 1479 { 1480 /* 1481 * We don't do anything here, so there's a very small chance of 1482 * us retaking a user fault which we just fixed up. The alternative 1483 * is doing a dsb(ishst), but that penalises the fastpath. 1484 */ 1485 } 1486 1487 #define update_mmu_cache(vma, addr, ptep) \ 1488 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1489 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1490 1491 #ifdef CONFIG_ARM64_PA_BITS_52 1492 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1493 #else 1494 #define phys_to_ttbr(addr) (addr) 1495 #endif 1496 1497 /* 1498 * On arm64 without hardware Access Flag, copying from user will fail because 1499 * the pte is old and cannot be marked young. So we always end up with zeroed 1500 * page after fork() + CoW for pfn mappings. We don't always have a 1501 * hardware-managed access flag on arm64. 1502 */ 1503 #define arch_has_hw_pte_young cpu_has_hw_af 1504 1505 /* 1506 * Experimentally, it's cheap to set the access flag in hardware and we 1507 * benefit from prefaulting mappings as 'old' to start with. 1508 */ 1509 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1510 1511 static inline bool pud_sect_supported(void) 1512 { 1513 return PAGE_SIZE == SZ_4K; 1514 } 1515 1516 1517 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1518 #define ptep_modify_prot_start ptep_modify_prot_start 1519 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1520 unsigned long addr, pte_t *ptep); 1521 1522 #define ptep_modify_prot_commit ptep_modify_prot_commit 1523 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1524 unsigned long addr, pte_t *ptep, 1525 pte_t old_pte, pte_t new_pte); 1526 1527 #ifdef CONFIG_ARM64_CONTPTE 1528 1529 /* 1530 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1531 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1532 * a private implementation detail of the public ptep API (see below). 1533 */ 1534 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1535 pte_t *ptep, pte_t pte); 1536 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1537 pte_t *ptep, pte_t pte); 1538 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1539 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1540 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1541 pte_t *ptep, pte_t pte, unsigned int nr); 1542 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1543 pte_t *ptep, unsigned int nr, int full); 1544 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1545 unsigned long addr, pte_t *ptep, 1546 unsigned int nr, int full); 1547 extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 1548 unsigned long addr, pte_t *ptep); 1549 extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 1550 unsigned long addr, pte_t *ptep); 1551 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1552 pte_t *ptep, unsigned int nr); 1553 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1554 unsigned long addr, pte_t *ptep, 1555 pte_t entry, int dirty); 1556 extern void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma, 1557 unsigned long addr, pte_t *ptep, 1558 unsigned int nr, cydp_t flags); 1559 1560 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1561 unsigned long addr, pte_t *ptep, pte_t pte) 1562 { 1563 /* 1564 * Only bother trying if both the virtual and physical addresses are 1565 * aligned and correspond to the last entry in a contig range. The core 1566 * code mostly modifies ranges from low to high, so this is the likely 1567 * the last modification in the contig range, so a good time to fold. 1568 * We can't fold special mappings, because there is no associated folio. 1569 */ 1570 1571 const unsigned long contmask = CONT_PTES - 1; 1572 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1573 1574 if (unlikely(valign)) { 1575 bool palign = (pte_pfn(pte) & contmask) == contmask; 1576 1577 if (unlikely(palign && 1578 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1579 __contpte_try_fold(mm, addr, ptep, pte); 1580 } 1581 } 1582 1583 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1584 unsigned long addr, pte_t *ptep, pte_t pte) 1585 { 1586 if (unlikely(pte_valid_cont(pte))) 1587 __contpte_try_unfold(mm, addr, ptep, pte); 1588 } 1589 1590 #define pte_batch_hint pte_batch_hint 1591 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1592 { 1593 if (!pte_valid_cont(pte)) 1594 return 1; 1595 1596 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1597 } 1598 1599 /* 1600 * The below functions constitute the public API that arm64 presents to the 1601 * core-mm to manipulate PTE entries within their page tables (or at least this 1602 * is the subset of the API that arm64 needs to implement). These public 1603 * versions will automatically and transparently apply the contiguous bit where 1604 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1605 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1606 * private versions, which are prefixed with double underscore. All of these 1607 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1608 * held. Although the contiguous bit is considered private to the 1609 * implementation, it is deliberately allowed to leak through the getters (e.g. 1610 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1611 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1612 * its possible a pte will be passed to a setter with the contiguous bit set, so 1613 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1614 * setting it in the pgtable. 1615 */ 1616 1617 #define ptep_get ptep_get 1618 static inline pte_t ptep_get(pte_t *ptep) 1619 { 1620 pte_t pte = __ptep_get(ptep); 1621 1622 if (likely(!pte_valid_cont(pte))) 1623 return pte; 1624 1625 return contpte_ptep_get(ptep, pte); 1626 } 1627 1628 #define ptep_get_lockless ptep_get_lockless 1629 static inline pte_t ptep_get_lockless(pte_t *ptep) 1630 { 1631 pte_t pte = __ptep_get(ptep); 1632 1633 if (likely(!pte_valid_cont(pte))) 1634 return pte; 1635 1636 return contpte_ptep_get_lockless(ptep); 1637 } 1638 1639 static inline void set_pte(pte_t *ptep, pte_t pte) 1640 { 1641 /* 1642 * We don't have the mm or vaddr so cannot unfold contig entries (since 1643 * it requires tlb maintenance). set_pte() is not used in core code, so 1644 * this should never even be called. Regardless do our best to service 1645 * any call and emit a warning if there is any attempt to set a pte on 1646 * top of an existing contig range. 1647 */ 1648 pte_t orig_pte = __ptep_get(ptep); 1649 1650 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1651 __set_pte(ptep, pte_mknoncont(pte)); 1652 } 1653 1654 #define set_ptes set_ptes 1655 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1656 pte_t *ptep, pte_t pte, unsigned int nr) 1657 { 1658 pte = pte_mknoncont(pte); 1659 1660 if (likely(nr == 1)) { 1661 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1662 __set_ptes(mm, addr, ptep, pte, 1); 1663 contpte_try_fold(mm, addr, ptep, pte); 1664 } else { 1665 contpte_set_ptes(mm, addr, ptep, pte, nr); 1666 } 1667 } 1668 1669 static inline void pte_clear(struct mm_struct *mm, 1670 unsigned long addr, pte_t *ptep) 1671 { 1672 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1673 __pte_clear(mm, addr, ptep); 1674 } 1675 1676 #define clear_full_ptes clear_full_ptes 1677 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1678 pte_t *ptep, unsigned int nr, int full) 1679 { 1680 if (likely(nr == 1)) { 1681 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1682 __clear_full_ptes(mm, addr, ptep, nr, full); 1683 } else { 1684 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1685 } 1686 } 1687 1688 #define get_and_clear_full_ptes get_and_clear_full_ptes 1689 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1690 unsigned long addr, pte_t *ptep, 1691 unsigned int nr, int full) 1692 { 1693 pte_t pte; 1694 1695 if (likely(nr == 1)) { 1696 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1697 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1698 } else { 1699 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1700 } 1701 1702 return pte; 1703 } 1704 1705 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1706 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1707 unsigned long addr, pte_t *ptep) 1708 { 1709 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1710 return __ptep_get_and_clear(mm, addr, ptep); 1711 } 1712 1713 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1714 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1715 unsigned long addr, pte_t *ptep) 1716 { 1717 pte_t orig_pte = __ptep_get(ptep); 1718 1719 if (likely(!pte_valid_cont(orig_pte))) 1720 return __ptep_test_and_clear_young(vma, addr, ptep); 1721 1722 return contpte_ptep_test_and_clear_young(vma, addr, ptep); 1723 } 1724 1725 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1726 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1727 unsigned long addr, pte_t *ptep) 1728 { 1729 pte_t orig_pte = __ptep_get(ptep); 1730 1731 if (likely(!pte_valid_cont(orig_pte))) 1732 return __ptep_clear_flush_young(vma, addr, ptep); 1733 1734 return contpte_ptep_clear_flush_young(vma, addr, ptep); 1735 } 1736 1737 #define wrprotect_ptes wrprotect_ptes 1738 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1739 unsigned long addr, pte_t *ptep, unsigned int nr) 1740 { 1741 if (likely(nr == 1)) { 1742 /* 1743 * Optimization: wrprotect_ptes() can only be called for present 1744 * ptes so we only need to check contig bit as condition for 1745 * unfold, and we can remove the contig bit from the pte we read 1746 * to avoid re-reading. This speeds up fork() which is sensitive 1747 * for order-0 folios. Equivalent to contpte_try_unfold(). 1748 */ 1749 pte_t orig_pte = __ptep_get(ptep); 1750 1751 if (unlikely(pte_cont(orig_pte))) { 1752 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1753 orig_pte = pte_mknoncont(orig_pte); 1754 } 1755 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1756 } else { 1757 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1758 } 1759 } 1760 1761 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1762 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1763 unsigned long addr, pte_t *ptep) 1764 { 1765 wrprotect_ptes(mm, addr, ptep, 1); 1766 } 1767 1768 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1769 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1770 unsigned long addr, pte_t *ptep, 1771 pte_t entry, int dirty) 1772 { 1773 pte_t orig_pte = __ptep_get(ptep); 1774 1775 entry = pte_mknoncont(entry); 1776 1777 if (likely(!pte_valid_cont(orig_pte))) 1778 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1779 1780 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1781 } 1782 1783 #define clear_young_dirty_ptes clear_young_dirty_ptes 1784 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 1785 unsigned long addr, pte_t *ptep, 1786 unsigned int nr, cydp_t flags) 1787 { 1788 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1789 __clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1790 else 1791 contpte_clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1792 } 1793 1794 #else /* CONFIG_ARM64_CONTPTE */ 1795 1796 #define ptep_get __ptep_get 1797 #define set_pte __set_pte 1798 #define set_ptes __set_ptes 1799 #define pte_clear __pte_clear 1800 #define clear_full_ptes __clear_full_ptes 1801 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1802 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1803 #define ptep_get_and_clear __ptep_get_and_clear 1804 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1805 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1806 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1807 #define ptep_clear_flush_young __ptep_clear_flush_young 1808 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1809 #define ptep_set_wrprotect __ptep_set_wrprotect 1810 #define wrprotect_ptes __wrprotect_ptes 1811 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1812 #define ptep_set_access_flags __ptep_set_access_flags 1813 #define clear_young_dirty_ptes __clear_young_dirty_ptes 1814 1815 #endif /* CONFIG_ARM64_CONTPTE */ 1816 1817 #endif /* !__ASSEMBLY__ */ 1818 1819 #endif /* __ASM_PGTABLE_H */ 1820