1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLY__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <linux/mmdebug.h> 38 #include <linux/mm_types.h> 39 #include <linux/sched.h> 40 #include <linux/page_table_check.h> 41 42 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 43 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 44 45 /* Set stride and tlb_level in flush_*_tlb_range */ 46 #define flush_pmd_tlb_range(vma, addr, end) \ 47 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 48 #define flush_pud_tlb_range(vma, addr, end) \ 49 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 50 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 51 52 /* 53 * Outside of a few very special situations (e.g. hibernation), we always 54 * use broadcast TLB invalidation instructions, therefore a spurious page 55 * fault on one CPU which has been handled concurrently by another CPU 56 * does not need to perform additional invalidation. 57 */ 58 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 59 60 /* 61 * ZERO_PAGE is a global shared page that is always zero: used 62 * for zero-mapped memory areas etc.. 63 */ 64 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 65 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 66 67 #define pte_ERROR(e) \ 68 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 69 70 /* 71 * Macros to convert between a physical address and its placement in a 72 * page table entry, taking care of 52-bit addresses. 73 */ 74 #ifdef CONFIG_ARM64_PA_BITS_52 75 static inline phys_addr_t __pte_to_phys(pte_t pte) 76 { 77 pte_val(pte) &= ~PTE_MAYBE_SHARED; 78 return (pte_val(pte) & PTE_ADDR_LOW) | 79 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 80 } 81 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 82 { 83 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 84 } 85 #else 86 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_LOW) 87 #define __phys_to_pte_val(phys) (phys) 88 #endif 89 90 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 91 #define pfn_pte(pfn,prot) \ 92 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 93 94 #define pte_none(pte) (!pte_val(pte)) 95 #define __pte_clear(mm, addr, ptep) \ 96 __set_pte(ptep, __pte(0)) 97 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 98 99 /* 100 * The following only work if pte_present(). Undefined behaviour otherwise. 101 */ 102 #define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte)) 103 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 104 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 105 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 106 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 107 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 108 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 109 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 110 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 111 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 112 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 113 114 #define pte_cont_addr_end(addr, end) \ 115 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 116 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 117 }) 118 119 #define pmd_cont_addr_end(addr, end) \ 120 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 121 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 122 }) 123 124 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 125 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 126 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 127 128 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 129 #define pte_present_invalid(pte) \ 130 ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID) 131 /* 132 * Execute-only user mappings do not have the PTE_USER bit set. All valid 133 * kernel mappings have the PTE_UXN bit set. 134 */ 135 #define pte_valid_not_user(pte) \ 136 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 137 /* 138 * Returns true if the pte is valid and has the contiguous bit set. 139 */ 140 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 141 /* 142 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 143 * so that we don't erroneously return false for pages that have been 144 * remapped as PROT_NONE but are yet to be flushed from the TLB. 145 * Note that we can't make any assumptions based on the state of the access 146 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 147 * TLB. 148 */ 149 #define pte_accessible(mm, pte) \ 150 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 151 152 /* 153 * p??_access_permitted() is true for valid user mappings (PTE_USER 154 * bit set, subject to the write permission check). For execute-only 155 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 156 * not set) must return false. PROT_NONE mappings do not have the 157 * PTE_VALID bit set. 158 */ 159 #define pte_access_permitted(pte, write) \ 160 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 161 #define pmd_access_permitted(pmd, write) \ 162 (pte_access_permitted(pmd_pte(pmd), (write))) 163 #define pud_access_permitted(pud, write) \ 164 (pte_access_permitted(pud_pte(pud), (write))) 165 166 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 167 { 168 pte_val(pte) &= ~pgprot_val(prot); 169 return pte; 170 } 171 172 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 173 { 174 pte_val(pte) |= pgprot_val(prot); 175 return pte; 176 } 177 178 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 179 { 180 pmd_val(pmd) &= ~pgprot_val(prot); 181 return pmd; 182 } 183 184 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 185 { 186 pmd_val(pmd) |= pgprot_val(prot); 187 return pmd; 188 } 189 190 static inline pte_t pte_mkwrite_novma(pte_t pte) 191 { 192 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 193 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 194 return pte; 195 } 196 197 static inline pte_t pte_mkclean(pte_t pte) 198 { 199 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 200 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 201 202 return pte; 203 } 204 205 static inline pte_t pte_mkdirty(pte_t pte) 206 { 207 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 208 209 if (pte_write(pte)) 210 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 211 212 return pte; 213 } 214 215 static inline pte_t pte_wrprotect(pte_t pte) 216 { 217 /* 218 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 219 * clear), set the PTE_DIRTY bit. 220 */ 221 if (pte_hw_dirty(pte)) 222 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 223 224 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 225 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 226 return pte; 227 } 228 229 static inline pte_t pte_mkold(pte_t pte) 230 { 231 return clear_pte_bit(pte, __pgprot(PTE_AF)); 232 } 233 234 static inline pte_t pte_mkyoung(pte_t pte) 235 { 236 return set_pte_bit(pte, __pgprot(PTE_AF)); 237 } 238 239 static inline pte_t pte_mkspecial(pte_t pte) 240 { 241 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 242 } 243 244 static inline pte_t pte_mkcont(pte_t pte) 245 { 246 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 247 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 248 } 249 250 static inline pte_t pte_mknoncont(pte_t pte) 251 { 252 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 253 } 254 255 static inline pte_t pte_mkpresent(pte_t pte) 256 { 257 return set_pte_bit(pte, __pgprot(PTE_VALID)); 258 } 259 260 static inline pte_t pte_mkinvalid(pte_t pte) 261 { 262 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 263 pte = clear_pte_bit(pte, __pgprot(PTE_VALID)); 264 return pte; 265 } 266 267 static inline pmd_t pmd_mkcont(pmd_t pmd) 268 { 269 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 270 } 271 272 static inline pte_t pte_mkdevmap(pte_t pte) 273 { 274 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 275 } 276 277 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 278 static inline int pte_uffd_wp(pte_t pte) 279 { 280 return !!(pte_val(pte) & PTE_UFFD_WP); 281 } 282 283 static inline pte_t pte_mkuffd_wp(pte_t pte) 284 { 285 return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD_WP))); 286 } 287 288 static inline pte_t pte_clear_uffd_wp(pte_t pte) 289 { 290 return clear_pte_bit(pte, __pgprot(PTE_UFFD_WP)); 291 } 292 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 293 294 static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 295 { 296 WRITE_ONCE(*ptep, pte); 297 } 298 299 static inline void __set_pte(pte_t *ptep, pte_t pte) 300 { 301 __set_pte_nosync(ptep, pte); 302 303 /* 304 * Only if the new pte is valid and kernel, otherwise TLB maintenance 305 * or update_mmu_cache() have the necessary barriers. 306 */ 307 if (pte_valid_not_user(pte)) { 308 dsb(ishst); 309 isb(); 310 } 311 } 312 313 static inline pte_t __ptep_get(pte_t *ptep) 314 { 315 return READ_ONCE(*ptep); 316 } 317 318 extern void __sync_icache_dcache(pte_t pteval); 319 bool pgattr_change_is_safe(u64 old, u64 new); 320 321 /* 322 * PTE bits configuration in the presence of hardware Dirty Bit Management 323 * (PTE_WRITE == PTE_DBM): 324 * 325 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 326 * 0 0 | 1 0 0 327 * 0 1 | 1 1 0 328 * 1 0 | 1 0 1 329 * 1 1 | 0 1 x 330 * 331 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 332 * the page fault mechanism. Checking the dirty status of a pte becomes: 333 * 334 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 335 */ 336 337 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 338 pte_t pte) 339 { 340 pte_t old_pte; 341 342 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 343 return; 344 345 old_pte = __ptep_get(ptep); 346 347 if (!pte_valid(old_pte) || !pte_valid(pte)) 348 return; 349 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 350 return; 351 352 /* 353 * Check for potential race with hardware updates of the pte 354 * (__ptep_set_access_flags safely changes valid ptes without going 355 * through an invalid entry). 356 */ 357 VM_WARN_ONCE(!pte_young(pte), 358 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 359 __func__, pte_val(old_pte), pte_val(pte)); 360 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 361 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 362 __func__, pte_val(old_pte), pte_val(pte)); 363 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 364 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 365 __func__, pte_val(old_pte), pte_val(pte)); 366 } 367 368 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 369 { 370 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 371 __sync_icache_dcache(pte); 372 373 /* 374 * If the PTE would provide user space access to the tags associated 375 * with it then ensure that the MTE tags are synchronised. Although 376 * pte_access_permitted() returns false for exec only mappings, they 377 * don't expose tags (instruction fetches don't check tags). 378 */ 379 if (system_supports_mte() && pte_access_permitted(pte, false) && 380 !pte_special(pte) && pte_tagged(pte)) 381 mte_sync_tags(pte, nr_pages); 382 } 383 384 /* 385 * Select all bits except the pfn 386 */ 387 #define pte_pgprot pte_pgprot 388 static inline pgprot_t pte_pgprot(pte_t pte) 389 { 390 unsigned long pfn = pte_pfn(pte); 391 392 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 393 } 394 395 #define pte_advance_pfn pte_advance_pfn 396 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 397 { 398 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 399 } 400 401 static inline void __set_ptes(struct mm_struct *mm, 402 unsigned long __always_unused addr, 403 pte_t *ptep, pte_t pte, unsigned int nr) 404 { 405 page_table_check_ptes_set(mm, ptep, pte, nr); 406 __sync_cache_and_tags(pte, nr); 407 408 for (;;) { 409 __check_safe_pte_update(mm, ptep, pte); 410 __set_pte(ptep, pte); 411 if (--nr == 0) 412 break; 413 ptep++; 414 pte = pte_advance_pfn(pte, 1); 415 } 416 } 417 418 /* 419 * Huge pte definitions. 420 */ 421 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 422 423 /* 424 * Hugetlb definitions. 425 */ 426 #define HUGE_MAX_HSTATE 4 427 #define HPAGE_SHIFT PMD_SHIFT 428 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 429 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 430 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 431 432 static inline pte_t pgd_pte(pgd_t pgd) 433 { 434 return __pte(pgd_val(pgd)); 435 } 436 437 static inline pte_t p4d_pte(p4d_t p4d) 438 { 439 return __pte(p4d_val(p4d)); 440 } 441 442 static inline pte_t pud_pte(pud_t pud) 443 { 444 return __pte(pud_val(pud)); 445 } 446 447 static inline pud_t pte_pud(pte_t pte) 448 { 449 return __pud(pte_val(pte)); 450 } 451 452 static inline pmd_t pud_pmd(pud_t pud) 453 { 454 return __pmd(pud_val(pud)); 455 } 456 457 static inline pte_t pmd_pte(pmd_t pmd) 458 { 459 return __pte(pmd_val(pmd)); 460 } 461 462 static inline pmd_t pte_pmd(pte_t pte) 463 { 464 return __pmd(pte_val(pte)); 465 } 466 467 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 468 { 469 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 470 } 471 472 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 473 { 474 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 475 } 476 477 static inline pte_t pte_swp_mkexclusive(pte_t pte) 478 { 479 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 480 } 481 482 static inline int pte_swp_exclusive(pte_t pte) 483 { 484 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 485 } 486 487 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 488 { 489 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 490 } 491 492 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 493 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 494 { 495 return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 496 } 497 498 static inline int pte_swp_uffd_wp(pte_t pte) 499 { 500 return !!(pte_val(pte) & PTE_SWP_UFFD_WP); 501 } 502 503 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 504 { 505 return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 506 } 507 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 508 509 #ifdef CONFIG_NUMA_BALANCING 510 /* 511 * See the comment in include/linux/pgtable.h 512 */ 513 static inline int pte_protnone(pte_t pte) 514 { 515 /* 516 * pte_present_invalid() tells us that the pte is invalid from HW 517 * perspective but present from SW perspective, so the fields are to be 518 * interpretted as per the HW layout. The second 2 checks are the unique 519 * encoding that we use for PROT_NONE. It is insufficient to only use 520 * the first check because we share the same encoding scheme with pmds 521 * which support pmd_mkinvalid(), so can be present-invalid without 522 * being PROT_NONE. 523 */ 524 return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte); 525 } 526 527 static inline int pmd_protnone(pmd_t pmd) 528 { 529 return pte_protnone(pmd_pte(pmd)); 530 } 531 #endif 532 533 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 534 535 /* 536 * THP definitions. 537 */ 538 539 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 540 static inline int pmd_trans_huge(pmd_t pmd) 541 { 542 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 543 } 544 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 545 546 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 547 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 548 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 549 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 550 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 551 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 552 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 553 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 554 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 555 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 556 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 557 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 558 #define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd))) 559 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 560 #define pmd_uffd_wp(pmd) pte_uffd_wp(pmd_pte(pmd)) 561 #define pmd_mkuffd_wp(pmd) pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))) 562 #define pmd_clear_uffd_wp(pmd) pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))) 563 #define pmd_swp_uffd_wp(pmd) pte_swp_uffd_wp(pmd_pte(pmd)) 564 #define pmd_swp_mkuffd_wp(pmd) pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))) 565 #define pmd_swp_clear_uffd_wp(pmd) \ 566 pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))) 567 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 568 569 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 570 571 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 572 573 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 574 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 575 #endif 576 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 577 { 578 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 579 } 580 581 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 582 #define pmd_special(pte) (!!((pmd_val(pte) & PTE_SPECIAL))) 583 static inline pmd_t pmd_mkspecial(pmd_t pmd) 584 { 585 return set_pmd_bit(pmd, __pgprot(PTE_SPECIAL)); 586 } 587 #endif 588 589 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 590 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 591 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 592 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 593 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 594 595 #define pud_young(pud) pte_young(pud_pte(pud)) 596 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 597 #define pud_write(pud) pte_write(pud_pte(pud)) 598 599 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 600 601 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 602 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 603 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 604 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 605 606 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP 607 #define pud_special(pte) pte_special(pud_pte(pud)) 608 #define pud_mkspecial(pte) pte_pud(pte_mkspecial(pud_pte(pud))) 609 #endif 610 611 #define pmd_pgprot pmd_pgprot 612 static inline pgprot_t pmd_pgprot(pmd_t pmd) 613 { 614 unsigned long pfn = pmd_pfn(pmd); 615 616 return __pgprot(pmd_val(pfn_pmd(pfn, __pgprot(0))) ^ pmd_val(pmd)); 617 } 618 619 #define pud_pgprot pud_pgprot 620 static inline pgprot_t pud_pgprot(pud_t pud) 621 { 622 unsigned long pfn = pud_pfn(pud); 623 624 return __pgprot(pud_val(pfn_pud(pfn, __pgprot(0))) ^ pud_val(pud)); 625 } 626 627 static inline void __set_pte_at(struct mm_struct *mm, 628 unsigned long __always_unused addr, 629 pte_t *ptep, pte_t pte, unsigned int nr) 630 { 631 __sync_cache_and_tags(pte, nr); 632 __check_safe_pte_update(mm, ptep, pte); 633 __set_pte(ptep, pte); 634 } 635 636 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 637 pmd_t *pmdp, pmd_t pmd) 638 { 639 page_table_check_pmd_set(mm, pmdp, pmd); 640 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 641 PMD_SIZE >> PAGE_SHIFT); 642 } 643 644 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 645 pud_t *pudp, pud_t pud) 646 { 647 page_table_check_pud_set(mm, pudp, pud); 648 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 649 PUD_SIZE >> PAGE_SHIFT); 650 } 651 652 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 653 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 654 655 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 656 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 657 658 #define __pgprot_modify(prot,mask,bits) \ 659 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 660 661 #define pgprot_nx(prot) \ 662 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 663 664 /* 665 * Mark the prot value as uncacheable and unbufferable. 666 */ 667 #define pgprot_noncached(prot) \ 668 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 669 #define pgprot_writecombine(prot) \ 670 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 671 #define pgprot_device(prot) \ 672 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 673 #define pgprot_tagged(prot) \ 674 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 675 #define pgprot_mhp pgprot_tagged 676 /* 677 * DMA allocations for non-coherent devices use what the Arm architecture calls 678 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 679 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 680 * is intended for MMIO and thus forbids speculation, preserves access size, 681 * requires strict alignment and can also force write responses to come from the 682 * endpoint. 683 */ 684 #define pgprot_dmacoherent(prot) \ 685 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 686 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 687 688 #define __HAVE_PHYS_MEM_ACCESS_PROT 689 struct file; 690 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 691 unsigned long size, pgprot_t vma_prot); 692 693 #define pmd_none(pmd) (!pmd_val(pmd)) 694 695 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 696 PMD_TYPE_TABLE) 697 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 698 PMD_TYPE_SECT) 699 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 700 #define pmd_bad(pmd) (!pmd_table(pmd)) 701 702 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 703 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 704 705 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 706 static inline bool pud_sect(pud_t pud) { return false; } 707 static inline bool pud_table(pud_t pud) { return true; } 708 #else 709 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 710 PUD_TYPE_SECT) 711 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 712 PUD_TYPE_TABLE) 713 #endif 714 715 extern pgd_t init_pg_dir[]; 716 extern pgd_t init_pg_end[]; 717 extern pgd_t swapper_pg_dir[]; 718 extern pgd_t idmap_pg_dir[]; 719 extern pgd_t tramp_pg_dir[]; 720 extern pgd_t reserved_pg_dir[]; 721 722 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 723 724 static inline bool in_swapper_pgdir(void *addr) 725 { 726 return ((unsigned long)addr & PAGE_MASK) == 727 ((unsigned long)swapper_pg_dir & PAGE_MASK); 728 } 729 730 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 731 { 732 #ifdef __PAGETABLE_PMD_FOLDED 733 if (in_swapper_pgdir(pmdp)) { 734 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 735 return; 736 } 737 #endif /* __PAGETABLE_PMD_FOLDED */ 738 739 WRITE_ONCE(*pmdp, pmd); 740 741 if (pmd_valid(pmd)) { 742 dsb(ishst); 743 isb(); 744 } 745 } 746 747 static inline void pmd_clear(pmd_t *pmdp) 748 { 749 set_pmd(pmdp, __pmd(0)); 750 } 751 752 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 753 { 754 return __pmd_to_phys(pmd); 755 } 756 757 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 758 { 759 return (unsigned long)__va(pmd_page_paddr(pmd)); 760 } 761 762 /* Find an entry in the third-level page table. */ 763 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 764 765 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 766 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 767 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 768 769 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 770 771 /* use ONLY for statically allocated translation tables */ 772 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 773 774 /* 775 * Conversion functions: convert a page and protection to a page entry, 776 * and a page entry and page directory to the page they refer to. 777 */ 778 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 779 780 #if CONFIG_PGTABLE_LEVELS > 2 781 782 #define pmd_ERROR(e) \ 783 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 784 785 #define pud_none(pud) (!pud_val(pud)) 786 #define pud_bad(pud) (!pud_table(pud)) 787 #define pud_present(pud) pte_present(pud_pte(pud)) 788 #ifndef __PAGETABLE_PMD_FOLDED 789 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 790 #else 791 #define pud_leaf(pud) false 792 #endif 793 #define pud_valid(pud) pte_valid(pud_pte(pud)) 794 #define pud_user(pud) pte_user(pud_pte(pud)) 795 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 796 797 static inline bool pgtable_l4_enabled(void); 798 799 static inline void set_pud(pud_t *pudp, pud_t pud) 800 { 801 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 802 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 803 return; 804 } 805 806 WRITE_ONCE(*pudp, pud); 807 808 if (pud_valid(pud)) { 809 dsb(ishst); 810 isb(); 811 } 812 } 813 814 static inline void pud_clear(pud_t *pudp) 815 { 816 set_pud(pudp, __pud(0)); 817 } 818 819 static inline phys_addr_t pud_page_paddr(pud_t pud) 820 { 821 return __pud_to_phys(pud); 822 } 823 824 static inline pmd_t *pud_pgtable(pud_t pud) 825 { 826 return (pmd_t *)__va(pud_page_paddr(pud)); 827 } 828 829 /* Find an entry in the second-level page table. */ 830 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 831 832 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 833 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 834 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 835 836 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 837 838 /* use ONLY for statically allocated translation tables */ 839 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 840 841 #else 842 843 #define pud_valid(pud) false 844 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 845 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 846 847 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 848 #define pmd_set_fixmap(addr) NULL 849 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 850 #define pmd_clear_fixmap() 851 852 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 853 854 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 855 856 #if CONFIG_PGTABLE_LEVELS > 3 857 858 static __always_inline bool pgtable_l4_enabled(void) 859 { 860 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 861 return true; 862 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 863 return vabits_actual == VA_BITS; 864 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 865 } 866 867 static inline bool mm_pud_folded(const struct mm_struct *mm) 868 { 869 return !pgtable_l4_enabled(); 870 } 871 #define mm_pud_folded mm_pud_folded 872 873 #define pud_ERROR(e) \ 874 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 875 876 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 877 #define p4d_bad(p4d) (pgtable_l4_enabled() && !(p4d_val(p4d) & 2)) 878 #define p4d_present(p4d) (!p4d_none(p4d)) 879 880 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 881 { 882 if (in_swapper_pgdir(p4dp)) { 883 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 884 return; 885 } 886 887 WRITE_ONCE(*p4dp, p4d); 888 dsb(ishst); 889 isb(); 890 } 891 892 static inline void p4d_clear(p4d_t *p4dp) 893 { 894 if (pgtable_l4_enabled()) 895 set_p4d(p4dp, __p4d(0)); 896 } 897 898 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 899 { 900 return __p4d_to_phys(p4d); 901 } 902 903 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 904 905 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 906 { 907 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 908 } 909 910 static inline pud_t *p4d_pgtable(p4d_t p4d) 911 { 912 return (pud_t *)__va(p4d_page_paddr(p4d)); 913 } 914 915 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 916 { 917 BUG_ON(!pgtable_l4_enabled()); 918 919 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 920 } 921 922 static inline 923 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 924 { 925 if (!pgtable_l4_enabled()) 926 return p4d_to_folded_pud(p4dp, addr); 927 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 928 } 929 #define pud_offset_lockless pud_offset_lockless 930 931 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 932 { 933 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 934 } 935 #define pud_offset pud_offset 936 937 static inline pud_t *pud_set_fixmap(unsigned long addr) 938 { 939 if (!pgtable_l4_enabled()) 940 return NULL; 941 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 942 } 943 944 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 945 { 946 if (!pgtable_l4_enabled()) 947 return p4d_to_folded_pud(p4dp, addr); 948 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 949 } 950 951 static inline void pud_clear_fixmap(void) 952 { 953 if (pgtable_l4_enabled()) 954 clear_fixmap(FIX_PUD); 955 } 956 957 /* use ONLY for statically allocated translation tables */ 958 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 959 { 960 if (!pgtable_l4_enabled()) 961 return p4d_to_folded_pud(p4dp, addr); 962 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 963 } 964 965 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 966 967 #else 968 969 static inline bool pgtable_l4_enabled(void) { return false; } 970 971 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 972 973 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 974 #define pud_set_fixmap(addr) NULL 975 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 976 #define pud_clear_fixmap() 977 978 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 979 980 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 981 982 #if CONFIG_PGTABLE_LEVELS > 4 983 984 static __always_inline bool pgtable_l5_enabled(void) 985 { 986 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 987 return vabits_actual == VA_BITS; 988 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 989 } 990 991 static inline bool mm_p4d_folded(const struct mm_struct *mm) 992 { 993 return !pgtable_l5_enabled(); 994 } 995 #define mm_p4d_folded mm_p4d_folded 996 997 #define p4d_ERROR(e) \ 998 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 999 1000 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 1001 #define pgd_bad(pgd) (pgtable_l5_enabled() && !(pgd_val(pgd) & 2)) 1002 #define pgd_present(pgd) (!pgd_none(pgd)) 1003 1004 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 1005 { 1006 if (in_swapper_pgdir(pgdp)) { 1007 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 1008 return; 1009 } 1010 1011 WRITE_ONCE(*pgdp, pgd); 1012 dsb(ishst); 1013 isb(); 1014 } 1015 1016 static inline void pgd_clear(pgd_t *pgdp) 1017 { 1018 if (pgtable_l5_enabled()) 1019 set_pgd(pgdp, __pgd(0)); 1020 } 1021 1022 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 1023 { 1024 return __pgd_to_phys(pgd); 1025 } 1026 1027 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1028 1029 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 1030 { 1031 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 1032 } 1033 1034 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 1035 { 1036 BUG_ON(!pgtable_l5_enabled()); 1037 1038 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 1039 } 1040 1041 static inline 1042 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1043 { 1044 if (!pgtable_l5_enabled()) 1045 return pgd_to_folded_p4d(pgdp, addr); 1046 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 1047 } 1048 #define p4d_offset_lockless p4d_offset_lockless 1049 1050 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 1051 { 1052 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 1053 } 1054 1055 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 1056 { 1057 if (!pgtable_l5_enabled()) 1058 return NULL; 1059 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 1060 } 1061 1062 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 1063 { 1064 if (!pgtable_l5_enabled()) 1065 return pgd_to_folded_p4d(pgdp, addr); 1066 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 1067 } 1068 1069 static inline void p4d_clear_fixmap(void) 1070 { 1071 if (pgtable_l5_enabled()) 1072 clear_fixmap(FIX_P4D); 1073 } 1074 1075 /* use ONLY for statically allocated translation tables */ 1076 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 1077 { 1078 if (!pgtable_l5_enabled()) 1079 return pgd_to_folded_p4d(pgdp, addr); 1080 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 1081 } 1082 1083 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1084 1085 #else 1086 1087 static inline bool pgtable_l5_enabled(void) { return false; } 1088 1089 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1090 1091 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1092 #define p4d_set_fixmap(addr) NULL 1093 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1094 #define p4d_clear_fixmap() 1095 1096 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1097 1098 static inline 1099 p4d_t *p4d_offset_lockless_folded(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1100 { 1101 /* 1102 * With runtime folding of the pud, pud_offset_lockless() passes 1103 * the 'pgd_t *' we return here to p4d_to_folded_pud(), which 1104 * will offset the pointer assuming that it points into 1105 * a page-table page. However, the fast GUP path passes us a 1106 * pgd_t allocated on the stack and so we must use the original 1107 * pointer in 'pgdp' to construct the p4d pointer instead of 1108 * using the generic p4d_offset_lockless() implementation. 1109 * 1110 * Note: reusing the original pointer means that we may 1111 * dereference the same (live) page-table entry multiple times. 1112 * This is safe because it is still only loaded once in the 1113 * context of each level and the CPU guarantees same-address 1114 * read-after-read ordering. 1115 */ 1116 return p4d_offset(pgdp, addr); 1117 } 1118 #define p4d_offset_lockless p4d_offset_lockless_folded 1119 1120 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1121 1122 #define pgd_ERROR(e) \ 1123 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1124 1125 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1126 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1127 1128 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1129 { 1130 /* 1131 * Normal and Normal-Tagged are two different memory types and indices 1132 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1133 */ 1134 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1135 PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE | 1136 PTE_GP | PTE_ATTRINDX_MASK; 1137 /* preserve the hardware dirty information */ 1138 if (pte_hw_dirty(pte)) 1139 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1140 1141 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1142 /* 1143 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1144 * dirtiness again. 1145 */ 1146 if (pte_sw_dirty(pte)) 1147 pte = pte_mkdirty(pte); 1148 return pte; 1149 } 1150 1151 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1152 { 1153 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1154 } 1155 1156 extern int __ptep_set_access_flags(struct vm_area_struct *vma, 1157 unsigned long address, pte_t *ptep, 1158 pte_t entry, int dirty); 1159 1160 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1161 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1162 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1163 unsigned long address, pmd_t *pmdp, 1164 pmd_t entry, int dirty) 1165 { 1166 return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 1167 pmd_pte(entry), dirty); 1168 } 1169 1170 static inline int pud_devmap(pud_t pud) 1171 { 1172 return 0; 1173 } 1174 1175 static inline int pgd_devmap(pgd_t pgd) 1176 { 1177 return 0; 1178 } 1179 #endif 1180 1181 #ifdef CONFIG_PAGE_TABLE_CHECK 1182 static inline bool pte_user_accessible_page(pte_t pte) 1183 { 1184 return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte)); 1185 } 1186 1187 static inline bool pmd_user_accessible_page(pmd_t pmd) 1188 { 1189 return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1190 } 1191 1192 static inline bool pud_user_accessible_page(pud_t pud) 1193 { 1194 return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud)); 1195 } 1196 #endif 1197 1198 /* 1199 * Atomic pte/pmd modifications. 1200 */ 1201 static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 1202 unsigned long address, 1203 pte_t *ptep) 1204 { 1205 pte_t old_pte, pte; 1206 1207 pte = __ptep_get(ptep); 1208 do { 1209 old_pte = pte; 1210 pte = pte_mkold(pte); 1211 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1212 pte_val(old_pte), pte_val(pte)); 1213 } while (pte_val(pte) != pte_val(old_pte)); 1214 1215 return pte_young(pte); 1216 } 1217 1218 static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 1219 unsigned long address, pte_t *ptep) 1220 { 1221 int young = __ptep_test_and_clear_young(vma, address, ptep); 1222 1223 if (young) { 1224 /* 1225 * We can elide the trailing DSB here since the worst that can 1226 * happen is that a CPU continues to use the young entry in its 1227 * TLB and we mistakenly reclaim the associated page. The 1228 * window for such an event is bounded by the next 1229 * context-switch, which provides a DSB to complete the TLB 1230 * invalidation. 1231 */ 1232 flush_tlb_page_nosync(vma, address); 1233 } 1234 1235 return young; 1236 } 1237 1238 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1239 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1240 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1241 unsigned long address, 1242 pmd_t *pmdp) 1243 { 1244 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1245 } 1246 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1247 1248 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1249 unsigned long address, pte_t *ptep) 1250 { 1251 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1252 1253 page_table_check_pte_clear(mm, pte); 1254 1255 return pte; 1256 } 1257 1258 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1259 pte_t *ptep, unsigned int nr, int full) 1260 { 1261 for (;;) { 1262 __ptep_get_and_clear(mm, addr, ptep); 1263 if (--nr == 0) 1264 break; 1265 ptep++; 1266 addr += PAGE_SIZE; 1267 } 1268 } 1269 1270 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1271 unsigned long addr, pte_t *ptep, 1272 unsigned int nr, int full) 1273 { 1274 pte_t pte, tmp_pte; 1275 1276 pte = __ptep_get_and_clear(mm, addr, ptep); 1277 while (--nr) { 1278 ptep++; 1279 addr += PAGE_SIZE; 1280 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1281 if (pte_dirty(tmp_pte)) 1282 pte = pte_mkdirty(pte); 1283 if (pte_young(tmp_pte)) 1284 pte = pte_mkyoung(pte); 1285 } 1286 return pte; 1287 } 1288 1289 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1290 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1291 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1292 unsigned long address, pmd_t *pmdp) 1293 { 1294 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 1295 1296 page_table_check_pmd_clear(mm, pmd); 1297 1298 return pmd; 1299 } 1300 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1301 1302 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1303 unsigned long address, pte_t *ptep, 1304 pte_t pte) 1305 { 1306 pte_t old_pte; 1307 1308 do { 1309 old_pte = pte; 1310 pte = pte_wrprotect(pte); 1311 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1312 pte_val(old_pte), pte_val(pte)); 1313 } while (pte_val(pte) != pte_val(old_pte)); 1314 } 1315 1316 /* 1317 * __ptep_set_wrprotect - mark read-only while trasferring potential hardware 1318 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1319 */ 1320 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1321 unsigned long address, pte_t *ptep) 1322 { 1323 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1324 } 1325 1326 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1327 pte_t *ptep, unsigned int nr) 1328 { 1329 unsigned int i; 1330 1331 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1332 __ptep_set_wrprotect(mm, address, ptep); 1333 } 1334 1335 static inline void __clear_young_dirty_pte(struct vm_area_struct *vma, 1336 unsigned long addr, pte_t *ptep, 1337 pte_t pte, cydp_t flags) 1338 { 1339 pte_t old_pte; 1340 1341 do { 1342 old_pte = pte; 1343 1344 if (flags & CYDP_CLEAR_YOUNG) 1345 pte = pte_mkold(pte); 1346 if (flags & CYDP_CLEAR_DIRTY) 1347 pte = pte_mkclean(pte); 1348 1349 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1350 pte_val(old_pte), pte_val(pte)); 1351 } while (pte_val(pte) != pte_val(old_pte)); 1352 } 1353 1354 static inline void __clear_young_dirty_ptes(struct vm_area_struct *vma, 1355 unsigned long addr, pte_t *ptep, 1356 unsigned int nr, cydp_t flags) 1357 { 1358 pte_t pte; 1359 1360 for (;;) { 1361 pte = __ptep_get(ptep); 1362 1363 if (flags == (CYDP_CLEAR_YOUNG | CYDP_CLEAR_DIRTY)) 1364 __set_pte(ptep, pte_mkclean(pte_mkold(pte))); 1365 else 1366 __clear_young_dirty_pte(vma, addr, ptep, pte, flags); 1367 1368 if (--nr == 0) 1369 break; 1370 ptep++; 1371 addr += PAGE_SIZE; 1372 } 1373 } 1374 1375 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1376 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1377 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1378 unsigned long address, pmd_t *pmdp) 1379 { 1380 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1381 } 1382 1383 #define pmdp_establish pmdp_establish 1384 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1385 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1386 { 1387 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1388 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1389 } 1390 #endif 1391 1392 /* 1393 * Encode and decode a swap entry: 1394 * bits 0-1: present (must be zero) 1395 * bits 2: remember PG_anon_exclusive 1396 * bit 3: remember uffd-wp state 1397 * bits 6-10: swap type 1398 * bit 11: PTE_PRESENT_INVALID (must be zero) 1399 * bits 12-61: swap offset 1400 */ 1401 #define __SWP_TYPE_SHIFT 6 1402 #define __SWP_TYPE_BITS 5 1403 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1404 #define __SWP_OFFSET_SHIFT 12 1405 #define __SWP_OFFSET_BITS 50 1406 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1407 1408 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1409 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1410 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1411 1412 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1413 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1414 1415 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1416 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1417 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1418 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1419 1420 /* 1421 * Ensure that there are not more swap files than can be encoded in the kernel 1422 * PTEs. 1423 */ 1424 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1425 1426 #ifdef CONFIG_ARM64_MTE 1427 1428 #define __HAVE_ARCH_PREPARE_TO_SWAP 1429 extern int arch_prepare_to_swap(struct folio *folio); 1430 1431 #define __HAVE_ARCH_SWAP_INVALIDATE 1432 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1433 { 1434 if (system_supports_mte()) 1435 mte_invalidate_tags(type, offset); 1436 } 1437 1438 static inline void arch_swap_invalidate_area(int type) 1439 { 1440 if (system_supports_mte()) 1441 mte_invalidate_tags_area(type); 1442 } 1443 1444 #define __HAVE_ARCH_SWAP_RESTORE 1445 extern void arch_swap_restore(swp_entry_t entry, struct folio *folio); 1446 1447 #endif /* CONFIG_ARM64_MTE */ 1448 1449 /* 1450 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1451 */ 1452 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1453 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1454 unsigned int nr) 1455 { 1456 /* 1457 * We don't do anything here, so there's a very small chance of 1458 * us retaking a user fault which we just fixed up. The alternative 1459 * is doing a dsb(ishst), but that penalises the fastpath. 1460 */ 1461 } 1462 1463 #define update_mmu_cache(vma, addr, ptep) \ 1464 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1465 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1466 1467 #ifdef CONFIG_ARM64_PA_BITS_52 1468 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1469 #else 1470 #define phys_to_ttbr(addr) (addr) 1471 #endif 1472 1473 /* 1474 * On arm64 without hardware Access Flag, copying from user will fail because 1475 * the pte is old and cannot be marked young. So we always end up with zeroed 1476 * page after fork() + CoW for pfn mappings. We don't always have a 1477 * hardware-managed access flag on arm64. 1478 */ 1479 #define arch_has_hw_pte_young cpu_has_hw_af 1480 1481 /* 1482 * Experimentally, it's cheap to set the access flag in hardware and we 1483 * benefit from prefaulting mappings as 'old' to start with. 1484 */ 1485 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1486 1487 static inline bool pud_sect_supported(void) 1488 { 1489 return PAGE_SIZE == SZ_4K; 1490 } 1491 1492 1493 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1494 #define ptep_modify_prot_start ptep_modify_prot_start 1495 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1496 unsigned long addr, pte_t *ptep); 1497 1498 #define ptep_modify_prot_commit ptep_modify_prot_commit 1499 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1500 unsigned long addr, pte_t *ptep, 1501 pte_t old_pte, pte_t new_pte); 1502 1503 #ifdef CONFIG_ARM64_CONTPTE 1504 1505 /* 1506 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1507 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1508 * a private implementation detail of the public ptep API (see below). 1509 */ 1510 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1511 pte_t *ptep, pte_t pte); 1512 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1513 pte_t *ptep, pte_t pte); 1514 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1515 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1516 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1517 pte_t *ptep, pte_t pte, unsigned int nr); 1518 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1519 pte_t *ptep, unsigned int nr, int full); 1520 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1521 unsigned long addr, pte_t *ptep, 1522 unsigned int nr, int full); 1523 extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 1524 unsigned long addr, pte_t *ptep); 1525 extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 1526 unsigned long addr, pte_t *ptep); 1527 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1528 pte_t *ptep, unsigned int nr); 1529 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1530 unsigned long addr, pte_t *ptep, 1531 pte_t entry, int dirty); 1532 extern void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma, 1533 unsigned long addr, pte_t *ptep, 1534 unsigned int nr, cydp_t flags); 1535 1536 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1537 unsigned long addr, pte_t *ptep, pte_t pte) 1538 { 1539 /* 1540 * Only bother trying if both the virtual and physical addresses are 1541 * aligned and correspond to the last entry in a contig range. The core 1542 * code mostly modifies ranges from low to high, so this is the likely 1543 * the last modification in the contig range, so a good time to fold. 1544 * We can't fold special mappings, because there is no associated folio. 1545 */ 1546 1547 const unsigned long contmask = CONT_PTES - 1; 1548 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1549 1550 if (unlikely(valign)) { 1551 bool palign = (pte_pfn(pte) & contmask) == contmask; 1552 1553 if (unlikely(palign && 1554 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1555 __contpte_try_fold(mm, addr, ptep, pte); 1556 } 1557 } 1558 1559 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1560 unsigned long addr, pte_t *ptep, pte_t pte) 1561 { 1562 if (unlikely(pte_valid_cont(pte))) 1563 __contpte_try_unfold(mm, addr, ptep, pte); 1564 } 1565 1566 #define pte_batch_hint pte_batch_hint 1567 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1568 { 1569 if (!pte_valid_cont(pte)) 1570 return 1; 1571 1572 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1573 } 1574 1575 /* 1576 * The below functions constitute the public API that arm64 presents to the 1577 * core-mm to manipulate PTE entries within their page tables (or at least this 1578 * is the subset of the API that arm64 needs to implement). These public 1579 * versions will automatically and transparently apply the contiguous bit where 1580 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1581 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1582 * private versions, which are prefixed with double underscore. All of these 1583 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1584 * held. Although the contiguous bit is considered private to the 1585 * implementation, it is deliberately allowed to leak through the getters (e.g. 1586 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1587 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1588 * its possible a pte will be passed to a setter with the contiguous bit set, so 1589 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1590 * setting it in the pgtable. 1591 */ 1592 1593 #define ptep_get ptep_get 1594 static inline pte_t ptep_get(pte_t *ptep) 1595 { 1596 pte_t pte = __ptep_get(ptep); 1597 1598 if (likely(!pte_valid_cont(pte))) 1599 return pte; 1600 1601 return contpte_ptep_get(ptep, pte); 1602 } 1603 1604 #define ptep_get_lockless ptep_get_lockless 1605 static inline pte_t ptep_get_lockless(pte_t *ptep) 1606 { 1607 pte_t pte = __ptep_get(ptep); 1608 1609 if (likely(!pte_valid_cont(pte))) 1610 return pte; 1611 1612 return contpte_ptep_get_lockless(ptep); 1613 } 1614 1615 static inline void set_pte(pte_t *ptep, pte_t pte) 1616 { 1617 /* 1618 * We don't have the mm or vaddr so cannot unfold contig entries (since 1619 * it requires tlb maintenance). set_pte() is not used in core code, so 1620 * this should never even be called. Regardless do our best to service 1621 * any call and emit a warning if there is any attempt to set a pte on 1622 * top of an existing contig range. 1623 */ 1624 pte_t orig_pte = __ptep_get(ptep); 1625 1626 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1627 __set_pte(ptep, pte_mknoncont(pte)); 1628 } 1629 1630 #define set_ptes set_ptes 1631 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1632 pte_t *ptep, pte_t pte, unsigned int nr) 1633 { 1634 pte = pte_mknoncont(pte); 1635 1636 if (likely(nr == 1)) { 1637 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1638 __set_ptes(mm, addr, ptep, pte, 1); 1639 contpte_try_fold(mm, addr, ptep, pte); 1640 } else { 1641 contpte_set_ptes(mm, addr, ptep, pte, nr); 1642 } 1643 } 1644 1645 static inline void pte_clear(struct mm_struct *mm, 1646 unsigned long addr, pte_t *ptep) 1647 { 1648 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1649 __pte_clear(mm, addr, ptep); 1650 } 1651 1652 #define clear_full_ptes clear_full_ptes 1653 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1654 pte_t *ptep, unsigned int nr, int full) 1655 { 1656 if (likely(nr == 1)) { 1657 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1658 __clear_full_ptes(mm, addr, ptep, nr, full); 1659 } else { 1660 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1661 } 1662 } 1663 1664 #define get_and_clear_full_ptes get_and_clear_full_ptes 1665 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1666 unsigned long addr, pte_t *ptep, 1667 unsigned int nr, int full) 1668 { 1669 pte_t pte; 1670 1671 if (likely(nr == 1)) { 1672 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1673 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1674 } else { 1675 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1676 } 1677 1678 return pte; 1679 } 1680 1681 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1682 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1683 unsigned long addr, pte_t *ptep) 1684 { 1685 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1686 return __ptep_get_and_clear(mm, addr, ptep); 1687 } 1688 1689 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1690 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1691 unsigned long addr, pte_t *ptep) 1692 { 1693 pte_t orig_pte = __ptep_get(ptep); 1694 1695 if (likely(!pte_valid_cont(orig_pte))) 1696 return __ptep_test_and_clear_young(vma, addr, ptep); 1697 1698 return contpte_ptep_test_and_clear_young(vma, addr, ptep); 1699 } 1700 1701 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1702 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1703 unsigned long addr, pte_t *ptep) 1704 { 1705 pte_t orig_pte = __ptep_get(ptep); 1706 1707 if (likely(!pte_valid_cont(orig_pte))) 1708 return __ptep_clear_flush_young(vma, addr, ptep); 1709 1710 return contpte_ptep_clear_flush_young(vma, addr, ptep); 1711 } 1712 1713 #define wrprotect_ptes wrprotect_ptes 1714 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1715 unsigned long addr, pte_t *ptep, unsigned int nr) 1716 { 1717 if (likely(nr == 1)) { 1718 /* 1719 * Optimization: wrprotect_ptes() can only be called for present 1720 * ptes so we only need to check contig bit as condition for 1721 * unfold, and we can remove the contig bit from the pte we read 1722 * to avoid re-reading. This speeds up fork() which is sensitive 1723 * for order-0 folios. Equivalent to contpte_try_unfold(). 1724 */ 1725 pte_t orig_pte = __ptep_get(ptep); 1726 1727 if (unlikely(pte_cont(orig_pte))) { 1728 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1729 orig_pte = pte_mknoncont(orig_pte); 1730 } 1731 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1732 } else { 1733 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1734 } 1735 } 1736 1737 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1738 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1739 unsigned long addr, pte_t *ptep) 1740 { 1741 wrprotect_ptes(mm, addr, ptep, 1); 1742 } 1743 1744 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1745 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1746 unsigned long addr, pte_t *ptep, 1747 pte_t entry, int dirty) 1748 { 1749 pte_t orig_pte = __ptep_get(ptep); 1750 1751 entry = pte_mknoncont(entry); 1752 1753 if (likely(!pte_valid_cont(orig_pte))) 1754 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1755 1756 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1757 } 1758 1759 #define clear_young_dirty_ptes clear_young_dirty_ptes 1760 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 1761 unsigned long addr, pte_t *ptep, 1762 unsigned int nr, cydp_t flags) 1763 { 1764 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1765 __clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1766 else 1767 contpte_clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1768 } 1769 1770 #else /* CONFIG_ARM64_CONTPTE */ 1771 1772 #define ptep_get __ptep_get 1773 #define set_pte __set_pte 1774 #define set_ptes __set_ptes 1775 #define pte_clear __pte_clear 1776 #define clear_full_ptes __clear_full_ptes 1777 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1778 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1779 #define ptep_get_and_clear __ptep_get_and_clear 1780 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1781 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1782 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1783 #define ptep_clear_flush_young __ptep_clear_flush_young 1784 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1785 #define ptep_set_wrprotect __ptep_set_wrprotect 1786 #define wrprotect_ptes __wrprotect_ptes 1787 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1788 #define ptep_set_access_flags __ptep_set_access_flags 1789 #define clear_young_dirty_ptes __clear_young_dirty_ptes 1790 1791 #endif /* CONFIG_ARM64_CONTPTE */ 1792 1793 #endif /* !__ASSEMBLY__ */ 1794 1795 #endif /* __ASM_PGTABLE_H */ 1796