1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLY__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <linux/mmdebug.h> 38 #include <linux/mm_types.h> 39 #include <linux/sched.h> 40 #include <linux/page_table_check.h> 41 42 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 43 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 44 45 /* Set stride and tlb_level in flush_*_tlb_range */ 46 #define flush_pmd_tlb_range(vma, addr, end) \ 47 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 48 #define flush_pud_tlb_range(vma, addr, end) \ 49 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 50 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 51 52 /* 53 * Outside of a few very special situations (e.g. hibernation), we always 54 * use broadcast TLB invalidation instructions, therefore a spurious page 55 * fault on one CPU which has been handled concurrently by another CPU 56 * does not need to perform additional invalidation. 57 */ 58 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 59 60 /* 61 * ZERO_PAGE is a global shared page that is always zero: used 62 * for zero-mapped memory areas etc.. 63 */ 64 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 65 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 66 67 #define pte_ERROR(e) \ 68 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 69 70 /* 71 * Macros to convert between a physical address and its placement in a 72 * page table entry, taking care of 52-bit addresses. 73 */ 74 #ifdef CONFIG_ARM64_PA_BITS_52 75 static inline phys_addr_t __pte_to_phys(pte_t pte) 76 { 77 pte_val(pte) &= ~PTE_MAYBE_SHARED; 78 return (pte_val(pte) & PTE_ADDR_LOW) | 79 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 80 } 81 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 82 { 83 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 84 } 85 #else 86 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_LOW) 87 #define __phys_to_pte_val(phys) (phys) 88 #endif 89 90 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 91 #define pfn_pte(pfn,prot) \ 92 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 93 94 #define pte_none(pte) (!pte_val(pte)) 95 #define __pte_clear(mm, addr, ptep) \ 96 __set_pte(ptep, __pte(0)) 97 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 98 99 /* 100 * The following only work if pte_present(). Undefined behaviour otherwise. 101 */ 102 #define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte)) 103 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 104 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 105 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 106 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 107 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 108 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 109 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 110 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 111 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 112 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 113 114 #define pte_cont_addr_end(addr, end) \ 115 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 116 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 117 }) 118 119 #define pmd_cont_addr_end(addr, end) \ 120 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 121 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 122 }) 123 124 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 125 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 126 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 127 128 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 129 #define pte_present_invalid(pte) \ 130 ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID) 131 /* 132 * Execute-only user mappings do not have the PTE_USER bit set. All valid 133 * kernel mappings have the PTE_UXN bit set. 134 */ 135 #define pte_valid_not_user(pte) \ 136 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 137 /* 138 * Returns true if the pte is valid and has the contiguous bit set. 139 */ 140 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 141 /* 142 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 143 * so that we don't erroneously return false for pages that have been 144 * remapped as PROT_NONE but are yet to be flushed from the TLB. 145 * Note that we can't make any assumptions based on the state of the access 146 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 147 * TLB. 148 */ 149 #define pte_accessible(mm, pte) \ 150 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 151 152 /* 153 * p??_access_permitted() is true for valid user mappings (PTE_USER 154 * bit set, subject to the write permission check). For execute-only 155 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 156 * not set) must return false. PROT_NONE mappings do not have the 157 * PTE_VALID bit set. 158 */ 159 #define pte_access_permitted(pte, write) \ 160 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 161 #define pmd_access_permitted(pmd, write) \ 162 (pte_access_permitted(pmd_pte(pmd), (write))) 163 #define pud_access_permitted(pud, write) \ 164 (pte_access_permitted(pud_pte(pud), (write))) 165 166 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 167 { 168 pte_val(pte) &= ~pgprot_val(prot); 169 return pte; 170 } 171 172 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 173 { 174 pte_val(pte) |= pgprot_val(prot); 175 return pte; 176 } 177 178 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 179 { 180 pmd_val(pmd) &= ~pgprot_val(prot); 181 return pmd; 182 } 183 184 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 185 { 186 pmd_val(pmd) |= pgprot_val(prot); 187 return pmd; 188 } 189 190 static inline pte_t pte_mkwrite_novma(pte_t pte) 191 { 192 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 193 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 194 return pte; 195 } 196 197 static inline pte_t pte_mkclean(pte_t pte) 198 { 199 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 200 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 201 202 return pte; 203 } 204 205 static inline pte_t pte_mkdirty(pte_t pte) 206 { 207 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 208 209 if (pte_write(pte)) 210 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 211 212 return pte; 213 } 214 215 static inline pte_t pte_wrprotect(pte_t pte) 216 { 217 /* 218 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 219 * clear), set the PTE_DIRTY bit. 220 */ 221 if (pte_hw_dirty(pte)) 222 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 223 224 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 225 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 226 return pte; 227 } 228 229 static inline pte_t pte_mkold(pte_t pte) 230 { 231 return clear_pte_bit(pte, __pgprot(PTE_AF)); 232 } 233 234 static inline pte_t pte_mkyoung(pte_t pte) 235 { 236 return set_pte_bit(pte, __pgprot(PTE_AF)); 237 } 238 239 static inline pte_t pte_mkspecial(pte_t pte) 240 { 241 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 242 } 243 244 static inline pte_t pte_mkcont(pte_t pte) 245 { 246 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 247 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 248 } 249 250 static inline pte_t pte_mknoncont(pte_t pte) 251 { 252 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 253 } 254 255 static inline pte_t pte_mkpresent(pte_t pte) 256 { 257 return set_pte_bit(pte, __pgprot(PTE_VALID)); 258 } 259 260 static inline pte_t pte_mkinvalid(pte_t pte) 261 { 262 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 263 pte = clear_pte_bit(pte, __pgprot(PTE_VALID)); 264 return pte; 265 } 266 267 static inline pmd_t pmd_mkcont(pmd_t pmd) 268 { 269 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 270 } 271 272 static inline pte_t pte_mkdevmap(pte_t pte) 273 { 274 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 275 } 276 277 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 278 static inline int pte_uffd_wp(pte_t pte) 279 { 280 return !!(pte_val(pte) & PTE_UFFD_WP); 281 } 282 283 static inline pte_t pte_mkuffd_wp(pte_t pte) 284 { 285 return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD_WP))); 286 } 287 288 static inline pte_t pte_clear_uffd_wp(pte_t pte) 289 { 290 return clear_pte_bit(pte, __pgprot(PTE_UFFD_WP)); 291 } 292 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 293 294 static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 295 { 296 WRITE_ONCE(*ptep, pte); 297 } 298 299 static inline void __set_pte(pte_t *ptep, pte_t pte) 300 { 301 __set_pte_nosync(ptep, pte); 302 303 /* 304 * Only if the new pte is valid and kernel, otherwise TLB maintenance 305 * or update_mmu_cache() have the necessary barriers. 306 */ 307 if (pte_valid_not_user(pte)) { 308 dsb(ishst); 309 isb(); 310 } 311 } 312 313 static inline pte_t __ptep_get(pte_t *ptep) 314 { 315 return READ_ONCE(*ptep); 316 } 317 318 extern void __sync_icache_dcache(pte_t pteval); 319 bool pgattr_change_is_safe(u64 old, u64 new); 320 321 /* 322 * PTE bits configuration in the presence of hardware Dirty Bit Management 323 * (PTE_WRITE == PTE_DBM): 324 * 325 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 326 * 0 0 | 1 0 0 327 * 0 1 | 1 1 0 328 * 1 0 | 1 0 1 329 * 1 1 | 0 1 x 330 * 331 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 332 * the page fault mechanism. Checking the dirty status of a pte becomes: 333 * 334 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 335 */ 336 337 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 338 pte_t pte) 339 { 340 pte_t old_pte; 341 342 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 343 return; 344 345 old_pte = __ptep_get(ptep); 346 347 if (!pte_valid(old_pte) || !pte_valid(pte)) 348 return; 349 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 350 return; 351 352 /* 353 * Check for potential race with hardware updates of the pte 354 * (__ptep_set_access_flags safely changes valid ptes without going 355 * through an invalid entry). 356 */ 357 VM_WARN_ONCE(!pte_young(pte), 358 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 359 __func__, pte_val(old_pte), pte_val(pte)); 360 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 361 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 362 __func__, pte_val(old_pte), pte_val(pte)); 363 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 364 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 365 __func__, pte_val(old_pte), pte_val(pte)); 366 } 367 368 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 369 { 370 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 371 __sync_icache_dcache(pte); 372 373 /* 374 * If the PTE would provide user space access to the tags associated 375 * with it then ensure that the MTE tags are synchronised. Although 376 * pte_access_permitted() returns false for exec only mappings, they 377 * don't expose tags (instruction fetches don't check tags). 378 */ 379 if (system_supports_mte() && pte_access_permitted(pte, false) && 380 !pte_special(pte) && pte_tagged(pte)) 381 mte_sync_tags(pte, nr_pages); 382 } 383 384 /* 385 * Select all bits except the pfn 386 */ 387 #define pte_pgprot pte_pgprot 388 static inline pgprot_t pte_pgprot(pte_t pte) 389 { 390 unsigned long pfn = pte_pfn(pte); 391 392 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 393 } 394 395 #define pte_advance_pfn pte_advance_pfn 396 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 397 { 398 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 399 } 400 401 static inline void __set_ptes(struct mm_struct *mm, 402 unsigned long __always_unused addr, 403 pte_t *ptep, pte_t pte, unsigned int nr) 404 { 405 page_table_check_ptes_set(mm, ptep, pte, nr); 406 __sync_cache_and_tags(pte, nr); 407 408 for (;;) { 409 __check_safe_pte_update(mm, ptep, pte); 410 __set_pte(ptep, pte); 411 if (--nr == 0) 412 break; 413 ptep++; 414 pte = pte_advance_pfn(pte, 1); 415 } 416 } 417 418 /* 419 * Huge pte definitions. 420 */ 421 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 422 423 /* 424 * Hugetlb definitions. 425 */ 426 #define HUGE_MAX_HSTATE 4 427 #define HPAGE_SHIFT PMD_SHIFT 428 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 429 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 430 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 431 432 static inline pte_t pgd_pte(pgd_t pgd) 433 { 434 return __pte(pgd_val(pgd)); 435 } 436 437 static inline pte_t p4d_pte(p4d_t p4d) 438 { 439 return __pte(p4d_val(p4d)); 440 } 441 442 static inline pte_t pud_pte(pud_t pud) 443 { 444 return __pte(pud_val(pud)); 445 } 446 447 static inline pud_t pte_pud(pte_t pte) 448 { 449 return __pud(pte_val(pte)); 450 } 451 452 static inline pmd_t pud_pmd(pud_t pud) 453 { 454 return __pmd(pud_val(pud)); 455 } 456 457 static inline pte_t pmd_pte(pmd_t pmd) 458 { 459 return __pte(pmd_val(pmd)); 460 } 461 462 static inline pmd_t pte_pmd(pte_t pte) 463 { 464 return __pmd(pte_val(pte)); 465 } 466 467 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 468 { 469 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 470 } 471 472 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 473 { 474 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 475 } 476 477 static inline pte_t pte_swp_mkexclusive(pte_t pte) 478 { 479 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 480 } 481 482 static inline int pte_swp_exclusive(pte_t pte) 483 { 484 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 485 } 486 487 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 488 { 489 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 490 } 491 492 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 493 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 494 { 495 return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 496 } 497 498 static inline int pte_swp_uffd_wp(pte_t pte) 499 { 500 return !!(pte_val(pte) & PTE_SWP_UFFD_WP); 501 } 502 503 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 504 { 505 return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 506 } 507 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 508 509 #ifdef CONFIG_NUMA_BALANCING 510 /* 511 * See the comment in include/linux/pgtable.h 512 */ 513 static inline int pte_protnone(pte_t pte) 514 { 515 /* 516 * pte_present_invalid() tells us that the pte is invalid from HW 517 * perspective but present from SW perspective, so the fields are to be 518 * interpretted as per the HW layout. The second 2 checks are the unique 519 * encoding that we use for PROT_NONE. It is insufficient to only use 520 * the first check because we share the same encoding scheme with pmds 521 * which support pmd_mkinvalid(), so can be present-invalid without 522 * being PROT_NONE. 523 */ 524 return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte); 525 } 526 527 static inline int pmd_protnone(pmd_t pmd) 528 { 529 return pte_protnone(pmd_pte(pmd)); 530 } 531 #endif 532 533 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 534 535 /* 536 * THP definitions. 537 */ 538 539 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 540 static inline int pmd_trans_huge(pmd_t pmd) 541 { 542 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 543 } 544 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 545 546 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 547 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 548 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 549 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 550 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 551 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 552 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 553 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 554 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 555 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 556 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 557 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 558 #define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd))) 559 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 560 #define pmd_uffd_wp(pmd) pte_uffd_wp(pmd_pte(pmd)) 561 #define pmd_mkuffd_wp(pmd) pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))) 562 #define pmd_clear_uffd_wp(pmd) pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))) 563 #define pmd_swp_uffd_wp(pmd) pte_swp_uffd_wp(pmd_pte(pmd)) 564 #define pmd_swp_mkuffd_wp(pmd) pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))) 565 #define pmd_swp_clear_uffd_wp(pmd) \ 566 pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))) 567 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 568 569 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 570 571 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 572 573 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 574 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 575 #endif 576 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 577 { 578 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 579 } 580 581 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 582 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 583 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 584 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 585 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 586 587 #define pud_young(pud) pte_young(pud_pte(pud)) 588 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 589 #define pud_write(pud) pte_write(pud_pte(pud)) 590 591 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 592 593 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 594 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 595 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 596 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 597 598 static inline void __set_pte_at(struct mm_struct *mm, 599 unsigned long __always_unused addr, 600 pte_t *ptep, pte_t pte, unsigned int nr) 601 { 602 __sync_cache_and_tags(pte, nr); 603 __check_safe_pte_update(mm, ptep, pte); 604 __set_pte(ptep, pte); 605 } 606 607 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 608 pmd_t *pmdp, pmd_t pmd) 609 { 610 page_table_check_pmd_set(mm, pmdp, pmd); 611 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 612 PMD_SIZE >> PAGE_SHIFT); 613 } 614 615 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 616 pud_t *pudp, pud_t pud) 617 { 618 page_table_check_pud_set(mm, pudp, pud); 619 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 620 PUD_SIZE >> PAGE_SHIFT); 621 } 622 623 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 624 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 625 626 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 627 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 628 629 #define __pgprot_modify(prot,mask,bits) \ 630 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 631 632 #define pgprot_nx(prot) \ 633 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 634 635 /* 636 * Mark the prot value as uncacheable and unbufferable. 637 */ 638 #define pgprot_noncached(prot) \ 639 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 640 #define pgprot_writecombine(prot) \ 641 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 642 #define pgprot_device(prot) \ 643 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 644 #define pgprot_tagged(prot) \ 645 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 646 #define pgprot_mhp pgprot_tagged 647 /* 648 * DMA allocations for non-coherent devices use what the Arm architecture calls 649 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 650 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 651 * is intended for MMIO and thus forbids speculation, preserves access size, 652 * requires strict alignment and can also force write responses to come from the 653 * endpoint. 654 */ 655 #define pgprot_dmacoherent(prot) \ 656 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 657 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 658 659 #define __HAVE_PHYS_MEM_ACCESS_PROT 660 struct file; 661 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 662 unsigned long size, pgprot_t vma_prot); 663 664 #define pmd_none(pmd) (!pmd_val(pmd)) 665 666 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 667 PMD_TYPE_TABLE) 668 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 669 PMD_TYPE_SECT) 670 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 671 #define pmd_bad(pmd) (!pmd_table(pmd)) 672 673 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 674 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 675 676 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 677 static inline bool pud_sect(pud_t pud) { return false; } 678 static inline bool pud_table(pud_t pud) { return true; } 679 #else 680 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 681 PUD_TYPE_SECT) 682 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 683 PUD_TYPE_TABLE) 684 #endif 685 686 extern pgd_t init_pg_dir[]; 687 extern pgd_t init_pg_end[]; 688 extern pgd_t swapper_pg_dir[]; 689 extern pgd_t idmap_pg_dir[]; 690 extern pgd_t tramp_pg_dir[]; 691 extern pgd_t reserved_pg_dir[]; 692 693 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 694 695 static inline bool in_swapper_pgdir(void *addr) 696 { 697 return ((unsigned long)addr & PAGE_MASK) == 698 ((unsigned long)swapper_pg_dir & PAGE_MASK); 699 } 700 701 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 702 { 703 #ifdef __PAGETABLE_PMD_FOLDED 704 if (in_swapper_pgdir(pmdp)) { 705 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 706 return; 707 } 708 #endif /* __PAGETABLE_PMD_FOLDED */ 709 710 WRITE_ONCE(*pmdp, pmd); 711 712 if (pmd_valid(pmd)) { 713 dsb(ishst); 714 isb(); 715 } 716 } 717 718 static inline void pmd_clear(pmd_t *pmdp) 719 { 720 set_pmd(pmdp, __pmd(0)); 721 } 722 723 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 724 { 725 return __pmd_to_phys(pmd); 726 } 727 728 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 729 { 730 return (unsigned long)__va(pmd_page_paddr(pmd)); 731 } 732 733 /* Find an entry in the third-level page table. */ 734 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 735 736 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 737 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 738 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 739 740 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 741 742 /* use ONLY for statically allocated translation tables */ 743 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 744 745 /* 746 * Conversion functions: convert a page and protection to a page entry, 747 * and a page entry and page directory to the page they refer to. 748 */ 749 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 750 751 #if CONFIG_PGTABLE_LEVELS > 2 752 753 #define pmd_ERROR(e) \ 754 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 755 756 #define pud_none(pud) (!pud_val(pud)) 757 #define pud_bad(pud) (!pud_table(pud)) 758 #define pud_present(pud) pte_present(pud_pte(pud)) 759 #ifndef __PAGETABLE_PMD_FOLDED 760 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 761 #else 762 #define pud_leaf(pud) false 763 #endif 764 #define pud_valid(pud) pte_valid(pud_pte(pud)) 765 #define pud_user(pud) pte_user(pud_pte(pud)) 766 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 767 768 static inline bool pgtable_l4_enabled(void); 769 770 static inline void set_pud(pud_t *pudp, pud_t pud) 771 { 772 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 773 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 774 return; 775 } 776 777 WRITE_ONCE(*pudp, pud); 778 779 if (pud_valid(pud)) { 780 dsb(ishst); 781 isb(); 782 } 783 } 784 785 static inline void pud_clear(pud_t *pudp) 786 { 787 set_pud(pudp, __pud(0)); 788 } 789 790 static inline phys_addr_t pud_page_paddr(pud_t pud) 791 { 792 return __pud_to_phys(pud); 793 } 794 795 static inline pmd_t *pud_pgtable(pud_t pud) 796 { 797 return (pmd_t *)__va(pud_page_paddr(pud)); 798 } 799 800 /* Find an entry in the second-level page table. */ 801 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 802 803 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 804 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 805 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 806 807 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 808 809 /* use ONLY for statically allocated translation tables */ 810 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 811 812 #else 813 814 #define pud_valid(pud) false 815 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 816 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 817 818 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 819 #define pmd_set_fixmap(addr) NULL 820 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 821 #define pmd_clear_fixmap() 822 823 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 824 825 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 826 827 #if CONFIG_PGTABLE_LEVELS > 3 828 829 static __always_inline bool pgtable_l4_enabled(void) 830 { 831 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 832 return true; 833 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 834 return vabits_actual == VA_BITS; 835 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 836 } 837 838 static inline bool mm_pud_folded(const struct mm_struct *mm) 839 { 840 return !pgtable_l4_enabled(); 841 } 842 #define mm_pud_folded mm_pud_folded 843 844 #define pud_ERROR(e) \ 845 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 846 847 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 848 #define p4d_bad(p4d) (pgtable_l4_enabled() && !(p4d_val(p4d) & 2)) 849 #define p4d_present(p4d) (!p4d_none(p4d)) 850 851 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 852 { 853 if (in_swapper_pgdir(p4dp)) { 854 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 855 return; 856 } 857 858 WRITE_ONCE(*p4dp, p4d); 859 dsb(ishst); 860 isb(); 861 } 862 863 static inline void p4d_clear(p4d_t *p4dp) 864 { 865 if (pgtable_l4_enabled()) 866 set_p4d(p4dp, __p4d(0)); 867 } 868 869 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 870 { 871 return __p4d_to_phys(p4d); 872 } 873 874 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 875 876 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 877 { 878 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 879 } 880 881 static inline pud_t *p4d_pgtable(p4d_t p4d) 882 { 883 return (pud_t *)__va(p4d_page_paddr(p4d)); 884 } 885 886 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 887 { 888 BUG_ON(!pgtable_l4_enabled()); 889 890 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 891 } 892 893 static inline 894 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 895 { 896 if (!pgtable_l4_enabled()) 897 return p4d_to_folded_pud(p4dp, addr); 898 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 899 } 900 #define pud_offset_lockless pud_offset_lockless 901 902 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 903 { 904 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 905 } 906 #define pud_offset pud_offset 907 908 static inline pud_t *pud_set_fixmap(unsigned long addr) 909 { 910 if (!pgtable_l4_enabled()) 911 return NULL; 912 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 913 } 914 915 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 916 { 917 if (!pgtable_l4_enabled()) 918 return p4d_to_folded_pud(p4dp, addr); 919 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 920 } 921 922 static inline void pud_clear_fixmap(void) 923 { 924 if (pgtable_l4_enabled()) 925 clear_fixmap(FIX_PUD); 926 } 927 928 /* use ONLY for statically allocated translation tables */ 929 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 930 { 931 if (!pgtable_l4_enabled()) 932 return p4d_to_folded_pud(p4dp, addr); 933 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 934 } 935 936 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 937 938 #else 939 940 static inline bool pgtable_l4_enabled(void) { return false; } 941 942 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 943 944 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 945 #define pud_set_fixmap(addr) NULL 946 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 947 #define pud_clear_fixmap() 948 949 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 950 951 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 952 953 #if CONFIG_PGTABLE_LEVELS > 4 954 955 static __always_inline bool pgtable_l5_enabled(void) 956 { 957 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 958 return vabits_actual == VA_BITS; 959 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 960 } 961 962 static inline bool mm_p4d_folded(const struct mm_struct *mm) 963 { 964 return !pgtable_l5_enabled(); 965 } 966 #define mm_p4d_folded mm_p4d_folded 967 968 #define p4d_ERROR(e) \ 969 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 970 971 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 972 #define pgd_bad(pgd) (pgtable_l5_enabled() && !(pgd_val(pgd) & 2)) 973 #define pgd_present(pgd) (!pgd_none(pgd)) 974 975 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 976 { 977 if (in_swapper_pgdir(pgdp)) { 978 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 979 return; 980 } 981 982 WRITE_ONCE(*pgdp, pgd); 983 dsb(ishst); 984 isb(); 985 } 986 987 static inline void pgd_clear(pgd_t *pgdp) 988 { 989 if (pgtable_l5_enabled()) 990 set_pgd(pgdp, __pgd(0)); 991 } 992 993 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 994 { 995 return __pgd_to_phys(pgd); 996 } 997 998 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 999 1000 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 1001 { 1002 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 1003 } 1004 1005 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 1006 { 1007 BUG_ON(!pgtable_l5_enabled()); 1008 1009 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 1010 } 1011 1012 static inline 1013 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1014 { 1015 if (!pgtable_l5_enabled()) 1016 return pgd_to_folded_p4d(pgdp, addr); 1017 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 1018 } 1019 #define p4d_offset_lockless p4d_offset_lockless 1020 1021 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 1022 { 1023 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 1024 } 1025 1026 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 1027 { 1028 if (!pgtable_l5_enabled()) 1029 return NULL; 1030 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 1031 } 1032 1033 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 1034 { 1035 if (!pgtable_l5_enabled()) 1036 return pgd_to_folded_p4d(pgdp, addr); 1037 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 1038 } 1039 1040 static inline void p4d_clear_fixmap(void) 1041 { 1042 if (pgtable_l5_enabled()) 1043 clear_fixmap(FIX_P4D); 1044 } 1045 1046 /* use ONLY for statically allocated translation tables */ 1047 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 1048 { 1049 if (!pgtable_l5_enabled()) 1050 return pgd_to_folded_p4d(pgdp, addr); 1051 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 1052 } 1053 1054 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1055 1056 #else 1057 1058 static inline bool pgtable_l5_enabled(void) { return false; } 1059 1060 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1061 1062 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1063 #define p4d_set_fixmap(addr) NULL 1064 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1065 #define p4d_clear_fixmap() 1066 1067 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1068 1069 static inline 1070 p4d_t *p4d_offset_lockless_folded(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1071 { 1072 /* 1073 * With runtime folding of the pud, pud_offset_lockless() passes 1074 * the 'pgd_t *' we return here to p4d_to_folded_pud(), which 1075 * will offset the pointer assuming that it points into 1076 * a page-table page. However, the fast GUP path passes us a 1077 * pgd_t allocated on the stack and so we must use the original 1078 * pointer in 'pgdp' to construct the p4d pointer instead of 1079 * using the generic p4d_offset_lockless() implementation. 1080 * 1081 * Note: reusing the original pointer means that we may 1082 * dereference the same (live) page-table entry multiple times. 1083 * This is safe because it is still only loaded once in the 1084 * context of each level and the CPU guarantees same-address 1085 * read-after-read ordering. 1086 */ 1087 return p4d_offset(pgdp, addr); 1088 } 1089 #define p4d_offset_lockless p4d_offset_lockless_folded 1090 1091 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1092 1093 #define pgd_ERROR(e) \ 1094 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1095 1096 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1097 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1098 1099 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1100 { 1101 /* 1102 * Normal and Normal-Tagged are two different memory types and indices 1103 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1104 */ 1105 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1106 PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE | 1107 PTE_GP | PTE_ATTRINDX_MASK; 1108 /* preserve the hardware dirty information */ 1109 if (pte_hw_dirty(pte)) 1110 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1111 1112 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1113 /* 1114 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1115 * dirtiness again. 1116 */ 1117 if (pte_sw_dirty(pte)) 1118 pte = pte_mkdirty(pte); 1119 return pte; 1120 } 1121 1122 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1123 { 1124 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1125 } 1126 1127 extern int __ptep_set_access_flags(struct vm_area_struct *vma, 1128 unsigned long address, pte_t *ptep, 1129 pte_t entry, int dirty); 1130 1131 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1132 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1133 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1134 unsigned long address, pmd_t *pmdp, 1135 pmd_t entry, int dirty) 1136 { 1137 return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 1138 pmd_pte(entry), dirty); 1139 } 1140 1141 static inline int pud_devmap(pud_t pud) 1142 { 1143 return 0; 1144 } 1145 1146 static inline int pgd_devmap(pgd_t pgd) 1147 { 1148 return 0; 1149 } 1150 #endif 1151 1152 #ifdef CONFIG_PAGE_TABLE_CHECK 1153 static inline bool pte_user_accessible_page(pte_t pte) 1154 { 1155 return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte)); 1156 } 1157 1158 static inline bool pmd_user_accessible_page(pmd_t pmd) 1159 { 1160 return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1161 } 1162 1163 static inline bool pud_user_accessible_page(pud_t pud) 1164 { 1165 return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud)); 1166 } 1167 #endif 1168 1169 /* 1170 * Atomic pte/pmd modifications. 1171 */ 1172 static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 1173 unsigned long address, 1174 pte_t *ptep) 1175 { 1176 pte_t old_pte, pte; 1177 1178 pte = __ptep_get(ptep); 1179 do { 1180 old_pte = pte; 1181 pte = pte_mkold(pte); 1182 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1183 pte_val(old_pte), pte_val(pte)); 1184 } while (pte_val(pte) != pte_val(old_pte)); 1185 1186 return pte_young(pte); 1187 } 1188 1189 static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 1190 unsigned long address, pte_t *ptep) 1191 { 1192 int young = __ptep_test_and_clear_young(vma, address, ptep); 1193 1194 if (young) { 1195 /* 1196 * We can elide the trailing DSB here since the worst that can 1197 * happen is that a CPU continues to use the young entry in its 1198 * TLB and we mistakenly reclaim the associated page. The 1199 * window for such an event is bounded by the next 1200 * context-switch, which provides a DSB to complete the TLB 1201 * invalidation. 1202 */ 1203 flush_tlb_page_nosync(vma, address); 1204 } 1205 1206 return young; 1207 } 1208 1209 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1210 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1211 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1212 unsigned long address, 1213 pmd_t *pmdp) 1214 { 1215 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1216 } 1217 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1218 1219 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1220 unsigned long address, pte_t *ptep) 1221 { 1222 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1223 1224 page_table_check_pte_clear(mm, pte); 1225 1226 return pte; 1227 } 1228 1229 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1230 pte_t *ptep, unsigned int nr, int full) 1231 { 1232 for (;;) { 1233 __ptep_get_and_clear(mm, addr, ptep); 1234 if (--nr == 0) 1235 break; 1236 ptep++; 1237 addr += PAGE_SIZE; 1238 } 1239 } 1240 1241 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1242 unsigned long addr, pte_t *ptep, 1243 unsigned int nr, int full) 1244 { 1245 pte_t pte, tmp_pte; 1246 1247 pte = __ptep_get_and_clear(mm, addr, ptep); 1248 while (--nr) { 1249 ptep++; 1250 addr += PAGE_SIZE; 1251 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1252 if (pte_dirty(tmp_pte)) 1253 pte = pte_mkdirty(pte); 1254 if (pte_young(tmp_pte)) 1255 pte = pte_mkyoung(pte); 1256 } 1257 return pte; 1258 } 1259 1260 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1261 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1262 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1263 unsigned long address, pmd_t *pmdp) 1264 { 1265 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 1266 1267 page_table_check_pmd_clear(mm, pmd); 1268 1269 return pmd; 1270 } 1271 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1272 1273 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1274 unsigned long address, pte_t *ptep, 1275 pte_t pte) 1276 { 1277 pte_t old_pte; 1278 1279 do { 1280 old_pte = pte; 1281 pte = pte_wrprotect(pte); 1282 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1283 pte_val(old_pte), pte_val(pte)); 1284 } while (pte_val(pte) != pte_val(old_pte)); 1285 } 1286 1287 /* 1288 * __ptep_set_wrprotect - mark read-only while trasferring potential hardware 1289 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1290 */ 1291 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1292 unsigned long address, pte_t *ptep) 1293 { 1294 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1295 } 1296 1297 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1298 pte_t *ptep, unsigned int nr) 1299 { 1300 unsigned int i; 1301 1302 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1303 __ptep_set_wrprotect(mm, address, ptep); 1304 } 1305 1306 static inline void __clear_young_dirty_pte(struct vm_area_struct *vma, 1307 unsigned long addr, pte_t *ptep, 1308 pte_t pte, cydp_t flags) 1309 { 1310 pte_t old_pte; 1311 1312 do { 1313 old_pte = pte; 1314 1315 if (flags & CYDP_CLEAR_YOUNG) 1316 pte = pte_mkold(pte); 1317 if (flags & CYDP_CLEAR_DIRTY) 1318 pte = pte_mkclean(pte); 1319 1320 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1321 pte_val(old_pte), pte_val(pte)); 1322 } while (pte_val(pte) != pte_val(old_pte)); 1323 } 1324 1325 static inline void __clear_young_dirty_ptes(struct vm_area_struct *vma, 1326 unsigned long addr, pte_t *ptep, 1327 unsigned int nr, cydp_t flags) 1328 { 1329 pte_t pte; 1330 1331 for (;;) { 1332 pte = __ptep_get(ptep); 1333 1334 if (flags == (CYDP_CLEAR_YOUNG | CYDP_CLEAR_DIRTY)) 1335 __set_pte(ptep, pte_mkclean(pte_mkold(pte))); 1336 else 1337 __clear_young_dirty_pte(vma, addr, ptep, pte, flags); 1338 1339 if (--nr == 0) 1340 break; 1341 ptep++; 1342 addr += PAGE_SIZE; 1343 } 1344 } 1345 1346 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1347 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1348 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1349 unsigned long address, pmd_t *pmdp) 1350 { 1351 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1352 } 1353 1354 #define pmdp_establish pmdp_establish 1355 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1356 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1357 { 1358 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1359 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1360 } 1361 #endif 1362 1363 /* 1364 * Encode and decode a swap entry: 1365 * bits 0-1: present (must be zero) 1366 * bits 2: remember PG_anon_exclusive 1367 * bit 3: remember uffd-wp state 1368 * bits 6-10: swap type 1369 * bit 11: PTE_PRESENT_INVALID (must be zero) 1370 * bits 12-61: swap offset 1371 */ 1372 #define __SWP_TYPE_SHIFT 6 1373 #define __SWP_TYPE_BITS 5 1374 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1375 #define __SWP_OFFSET_SHIFT 12 1376 #define __SWP_OFFSET_BITS 50 1377 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1378 1379 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1380 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1381 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1382 1383 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1384 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1385 1386 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1387 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1388 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1389 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1390 1391 /* 1392 * Ensure that there are not more swap files than can be encoded in the kernel 1393 * PTEs. 1394 */ 1395 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1396 1397 #ifdef CONFIG_ARM64_MTE 1398 1399 #define __HAVE_ARCH_PREPARE_TO_SWAP 1400 extern int arch_prepare_to_swap(struct folio *folio); 1401 1402 #define __HAVE_ARCH_SWAP_INVALIDATE 1403 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1404 { 1405 if (system_supports_mte()) 1406 mte_invalidate_tags(type, offset); 1407 } 1408 1409 static inline void arch_swap_invalidate_area(int type) 1410 { 1411 if (system_supports_mte()) 1412 mte_invalidate_tags_area(type); 1413 } 1414 1415 #define __HAVE_ARCH_SWAP_RESTORE 1416 extern void arch_swap_restore(swp_entry_t entry, struct folio *folio); 1417 1418 #endif /* CONFIG_ARM64_MTE */ 1419 1420 /* 1421 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1422 */ 1423 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1424 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1425 unsigned int nr) 1426 { 1427 /* 1428 * We don't do anything here, so there's a very small chance of 1429 * us retaking a user fault which we just fixed up. The alternative 1430 * is doing a dsb(ishst), but that penalises the fastpath. 1431 */ 1432 } 1433 1434 #define update_mmu_cache(vma, addr, ptep) \ 1435 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1436 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1437 1438 #ifdef CONFIG_ARM64_PA_BITS_52 1439 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1440 #else 1441 #define phys_to_ttbr(addr) (addr) 1442 #endif 1443 1444 /* 1445 * On arm64 without hardware Access Flag, copying from user will fail because 1446 * the pte is old and cannot be marked young. So we always end up with zeroed 1447 * page after fork() + CoW for pfn mappings. We don't always have a 1448 * hardware-managed access flag on arm64. 1449 */ 1450 #define arch_has_hw_pte_young cpu_has_hw_af 1451 1452 /* 1453 * Experimentally, it's cheap to set the access flag in hardware and we 1454 * benefit from prefaulting mappings as 'old' to start with. 1455 */ 1456 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1457 1458 static inline bool pud_sect_supported(void) 1459 { 1460 return PAGE_SIZE == SZ_4K; 1461 } 1462 1463 1464 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1465 #define ptep_modify_prot_start ptep_modify_prot_start 1466 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1467 unsigned long addr, pte_t *ptep); 1468 1469 #define ptep_modify_prot_commit ptep_modify_prot_commit 1470 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1471 unsigned long addr, pte_t *ptep, 1472 pte_t old_pte, pte_t new_pte); 1473 1474 #ifdef CONFIG_ARM64_CONTPTE 1475 1476 /* 1477 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1478 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1479 * a private implementation detail of the public ptep API (see below). 1480 */ 1481 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1482 pte_t *ptep, pte_t pte); 1483 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1484 pte_t *ptep, pte_t pte); 1485 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1486 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1487 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1488 pte_t *ptep, pte_t pte, unsigned int nr); 1489 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1490 pte_t *ptep, unsigned int nr, int full); 1491 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1492 unsigned long addr, pte_t *ptep, 1493 unsigned int nr, int full); 1494 extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 1495 unsigned long addr, pte_t *ptep); 1496 extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 1497 unsigned long addr, pte_t *ptep); 1498 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1499 pte_t *ptep, unsigned int nr); 1500 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1501 unsigned long addr, pte_t *ptep, 1502 pte_t entry, int dirty); 1503 extern void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma, 1504 unsigned long addr, pte_t *ptep, 1505 unsigned int nr, cydp_t flags); 1506 1507 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1508 unsigned long addr, pte_t *ptep, pte_t pte) 1509 { 1510 /* 1511 * Only bother trying if both the virtual and physical addresses are 1512 * aligned and correspond to the last entry in a contig range. The core 1513 * code mostly modifies ranges from low to high, so this is the likely 1514 * the last modification in the contig range, so a good time to fold. 1515 * We can't fold special mappings, because there is no associated folio. 1516 */ 1517 1518 const unsigned long contmask = CONT_PTES - 1; 1519 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1520 1521 if (unlikely(valign)) { 1522 bool palign = (pte_pfn(pte) & contmask) == contmask; 1523 1524 if (unlikely(palign && 1525 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1526 __contpte_try_fold(mm, addr, ptep, pte); 1527 } 1528 } 1529 1530 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1531 unsigned long addr, pte_t *ptep, pte_t pte) 1532 { 1533 if (unlikely(pte_valid_cont(pte))) 1534 __contpte_try_unfold(mm, addr, ptep, pte); 1535 } 1536 1537 #define pte_batch_hint pte_batch_hint 1538 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1539 { 1540 if (!pte_valid_cont(pte)) 1541 return 1; 1542 1543 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1544 } 1545 1546 /* 1547 * The below functions constitute the public API that arm64 presents to the 1548 * core-mm to manipulate PTE entries within their page tables (or at least this 1549 * is the subset of the API that arm64 needs to implement). These public 1550 * versions will automatically and transparently apply the contiguous bit where 1551 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1552 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1553 * private versions, which are prefixed with double underscore. All of these 1554 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1555 * held. Although the contiguous bit is considered private to the 1556 * implementation, it is deliberately allowed to leak through the getters (e.g. 1557 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1558 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1559 * its possible a pte will be passed to a setter with the contiguous bit set, so 1560 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1561 * setting it in the pgtable. 1562 */ 1563 1564 #define ptep_get ptep_get 1565 static inline pte_t ptep_get(pte_t *ptep) 1566 { 1567 pte_t pte = __ptep_get(ptep); 1568 1569 if (likely(!pte_valid_cont(pte))) 1570 return pte; 1571 1572 return contpte_ptep_get(ptep, pte); 1573 } 1574 1575 #define ptep_get_lockless ptep_get_lockless 1576 static inline pte_t ptep_get_lockless(pte_t *ptep) 1577 { 1578 pte_t pte = __ptep_get(ptep); 1579 1580 if (likely(!pte_valid_cont(pte))) 1581 return pte; 1582 1583 return contpte_ptep_get_lockless(ptep); 1584 } 1585 1586 static inline void set_pte(pte_t *ptep, pte_t pte) 1587 { 1588 /* 1589 * We don't have the mm or vaddr so cannot unfold contig entries (since 1590 * it requires tlb maintenance). set_pte() is not used in core code, so 1591 * this should never even be called. Regardless do our best to service 1592 * any call and emit a warning if there is any attempt to set a pte on 1593 * top of an existing contig range. 1594 */ 1595 pte_t orig_pte = __ptep_get(ptep); 1596 1597 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1598 __set_pte(ptep, pte_mknoncont(pte)); 1599 } 1600 1601 #define set_ptes set_ptes 1602 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1603 pte_t *ptep, pte_t pte, unsigned int nr) 1604 { 1605 pte = pte_mknoncont(pte); 1606 1607 if (likely(nr == 1)) { 1608 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1609 __set_ptes(mm, addr, ptep, pte, 1); 1610 contpte_try_fold(mm, addr, ptep, pte); 1611 } else { 1612 contpte_set_ptes(mm, addr, ptep, pte, nr); 1613 } 1614 } 1615 1616 static inline void pte_clear(struct mm_struct *mm, 1617 unsigned long addr, pte_t *ptep) 1618 { 1619 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1620 __pte_clear(mm, addr, ptep); 1621 } 1622 1623 #define clear_full_ptes clear_full_ptes 1624 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1625 pte_t *ptep, unsigned int nr, int full) 1626 { 1627 if (likely(nr == 1)) { 1628 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1629 __clear_full_ptes(mm, addr, ptep, nr, full); 1630 } else { 1631 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1632 } 1633 } 1634 1635 #define get_and_clear_full_ptes get_and_clear_full_ptes 1636 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1637 unsigned long addr, pte_t *ptep, 1638 unsigned int nr, int full) 1639 { 1640 pte_t pte; 1641 1642 if (likely(nr == 1)) { 1643 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1644 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1645 } else { 1646 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1647 } 1648 1649 return pte; 1650 } 1651 1652 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1653 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1654 unsigned long addr, pte_t *ptep) 1655 { 1656 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1657 return __ptep_get_and_clear(mm, addr, ptep); 1658 } 1659 1660 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1661 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1662 unsigned long addr, pte_t *ptep) 1663 { 1664 pte_t orig_pte = __ptep_get(ptep); 1665 1666 if (likely(!pte_valid_cont(orig_pte))) 1667 return __ptep_test_and_clear_young(vma, addr, ptep); 1668 1669 return contpte_ptep_test_and_clear_young(vma, addr, ptep); 1670 } 1671 1672 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1673 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1674 unsigned long addr, pte_t *ptep) 1675 { 1676 pte_t orig_pte = __ptep_get(ptep); 1677 1678 if (likely(!pte_valid_cont(orig_pte))) 1679 return __ptep_clear_flush_young(vma, addr, ptep); 1680 1681 return contpte_ptep_clear_flush_young(vma, addr, ptep); 1682 } 1683 1684 #define wrprotect_ptes wrprotect_ptes 1685 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1686 unsigned long addr, pte_t *ptep, unsigned int nr) 1687 { 1688 if (likely(nr == 1)) { 1689 /* 1690 * Optimization: wrprotect_ptes() can only be called for present 1691 * ptes so we only need to check contig bit as condition for 1692 * unfold, and we can remove the contig bit from the pte we read 1693 * to avoid re-reading. This speeds up fork() which is sensitive 1694 * for order-0 folios. Equivalent to contpte_try_unfold(). 1695 */ 1696 pte_t orig_pte = __ptep_get(ptep); 1697 1698 if (unlikely(pte_cont(orig_pte))) { 1699 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1700 orig_pte = pte_mknoncont(orig_pte); 1701 } 1702 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1703 } else { 1704 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1705 } 1706 } 1707 1708 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1709 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1710 unsigned long addr, pte_t *ptep) 1711 { 1712 wrprotect_ptes(mm, addr, ptep, 1); 1713 } 1714 1715 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1716 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1717 unsigned long addr, pte_t *ptep, 1718 pte_t entry, int dirty) 1719 { 1720 pte_t orig_pte = __ptep_get(ptep); 1721 1722 entry = pte_mknoncont(entry); 1723 1724 if (likely(!pte_valid_cont(orig_pte))) 1725 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1726 1727 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1728 } 1729 1730 #define clear_young_dirty_ptes clear_young_dirty_ptes 1731 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 1732 unsigned long addr, pte_t *ptep, 1733 unsigned int nr, cydp_t flags) 1734 { 1735 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1736 __clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1737 else 1738 contpte_clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1739 } 1740 1741 #else /* CONFIG_ARM64_CONTPTE */ 1742 1743 #define ptep_get __ptep_get 1744 #define set_pte __set_pte 1745 #define set_ptes __set_ptes 1746 #define pte_clear __pte_clear 1747 #define clear_full_ptes __clear_full_ptes 1748 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1749 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1750 #define ptep_get_and_clear __ptep_get_and_clear 1751 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1752 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1753 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1754 #define ptep_clear_flush_young __ptep_clear_flush_young 1755 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1756 #define ptep_set_wrprotect __ptep_set_wrprotect 1757 #define wrprotect_ptes __wrprotect_ptes 1758 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1759 #define ptep_set_access_flags __ptep_set_access_flags 1760 #define clear_young_dirty_ptes __clear_young_dirty_ptes 1761 1762 #endif /* CONFIG_ARM64_CONTPTE */ 1763 1764 #endif /* !__ASSEMBLY__ */ 1765 1766 #endif /* __ASM_PGTABLE_H */ 1767