1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/seq_file.h> 10 #include <linux/fs.h> 11 #include <linux/delay.h> 12 #include <linux/root_dev.h> 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clocksource.h> 16 #include <linux/console.h> 17 #include <linux/module.h> 18 #include <linux/cpu.h> 19 #include <linux/of_fdt.h> 20 #include <linux/of.h> 21 #include <linux/cache.h> 22 #include <uapi/linux/mount.h> 23 #include <asm/sections.h> 24 #include <asm/arcregs.h> 25 #include <asm/tlb.h> 26 #include <asm/setup.h> 27 #include <asm/page.h> 28 #include <asm/irq.h> 29 #include <asm/unwind.h> 30 #include <asm/mach_desc.h> 31 #include <asm/smp.h> 32 33 #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) 34 35 unsigned int intr_to_DE_cnt; 36 37 /* Part of U-boot ABI: see head.S */ 38 int __initdata uboot_tag; 39 int __initdata uboot_magic; 40 char __initdata *uboot_arg; 41 42 const struct machine_desc *machine_desc; 43 44 struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ 45 46 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; 47 48 static const struct id_to_str arc_legacy_rel[] = { 49 /* ID.ARCVER, Release */ 50 #ifdef CONFIG_ISA_ARCOMPACT 51 { 0x34, "R4.10"}, 52 { 0x35, "R4.11"}, 53 #else 54 { 0x51, "R2.0" }, 55 { 0x52, "R2.1" }, 56 { 0x53, "R3.0" }, 57 #endif 58 { 0x00, NULL } 59 }; 60 61 static const struct id_to_str arc_cpu_rel[] = { 62 /* UARCH.MAJOR, Release */ 63 { 0, "R3.10a"}, 64 { 1, "R3.50a"}, 65 { 0xFF, NULL } 66 }; 67 68 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) 69 { 70 if (is_isa_arcompact()) { 71 struct bcr_iccm_arcompact iccm; 72 struct bcr_dccm_arcompact dccm; 73 74 READ_BCR(ARC_REG_ICCM_BUILD, iccm); 75 if (iccm.ver) { 76 cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ 77 cpu->iccm.base_addr = iccm.base << 16; 78 } 79 80 READ_BCR(ARC_REG_DCCM_BUILD, dccm); 81 if (dccm.ver) { 82 unsigned long base; 83 cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */ 84 85 base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); 86 cpu->dccm.base_addr = base & ~0xF; 87 } 88 } else { 89 struct bcr_iccm_arcv2 iccm; 90 struct bcr_dccm_arcv2 dccm; 91 unsigned long region; 92 93 READ_BCR(ARC_REG_ICCM_BUILD, iccm); 94 if (iccm.ver) { 95 cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */ 96 if (iccm.sz00 == 0xF && iccm.sz01 > 0) 97 cpu->iccm.sz <<= iccm.sz01; 98 99 region = read_aux_reg(ARC_REG_AUX_ICCM); 100 cpu->iccm.base_addr = region & 0xF0000000; 101 } 102 103 READ_BCR(ARC_REG_DCCM_BUILD, dccm); 104 if (dccm.ver) { 105 cpu->dccm.sz = 256 << dccm.sz0; 106 if (dccm.sz0 == 0xF && dccm.sz1 > 0) 107 cpu->dccm.sz <<= dccm.sz1; 108 109 region = read_aux_reg(ARC_REG_AUX_DCCM); 110 cpu->dccm.base_addr = region & 0xF0000000; 111 } 112 } 113 } 114 115 static void decode_arc_core(struct cpuinfo_arc *cpu) 116 { 117 struct bcr_uarch_build_arcv2 uarch; 118 const struct id_to_str *tbl; 119 120 /* 121 * Up until (including) the first core4 release (0x54) things were 122 * simple: AUX IDENTITY.ARCVER was sufficient to identify arc family 123 * and release: 0x50 to 0x53 was HS38, 0x54 was HS48 (dual issue) 124 */ 125 126 if (cpu->core.family < 0x54) { /* includes arc700 */ 127 128 for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) { 129 if (cpu->core.family == tbl->id) { 130 cpu->release = tbl->str; 131 break; 132 } 133 } 134 135 if (is_isa_arcompact()) 136 cpu->name = "ARC700"; 137 else if (tbl->str) 138 cpu->name = "HS38"; 139 else 140 cpu->name = cpu->release = "Unknown"; 141 142 return; 143 } 144 145 /* 146 * However the subsequent HS release (same 0x54) allow HS38 or HS48 147 * configurations and encode this info in a different BCR. 148 * The BCR was introduced in 0x54 so can't be read unconditionally. 149 */ 150 151 READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch); 152 153 if (uarch.prod == 4) { 154 cpu->name = "HS48"; 155 cpu->extn.dual = 1; 156 157 } else { 158 cpu->name = "HS38"; 159 } 160 161 for (tbl = &arc_cpu_rel[0]; tbl->id != 0xFF; tbl++) { 162 if (uarch.maj == tbl->id) { 163 cpu->release = tbl->str; 164 break; 165 } 166 } 167 } 168 169 static void read_arc_build_cfg_regs(void) 170 { 171 struct bcr_timer timer; 172 struct bcr_generic bcr; 173 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 174 struct bcr_isa_arcv2 isa; 175 struct bcr_actionpoint ap; 176 177 FIX_PTR(cpu); 178 179 READ_BCR(AUX_IDENTITY, cpu->core); 180 decode_arc_core(cpu); 181 182 READ_BCR(ARC_REG_TIMERS_BCR, timer); 183 cpu->extn.timer0 = timer.t0; 184 cpu->extn.timer1 = timer.t1; 185 cpu->extn.rtc = timer.rtc; 186 187 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); 188 189 READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy); 190 191 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */ 192 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */ 193 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */ 194 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0; 195 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */ 196 cpu->extn.swape = (cpu->core.family >= 0x34) ? 1 : 197 IS_ENABLED(CONFIG_ARC_HAS_SWAPE); 198 199 READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem); 200 201 /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ 202 read_decode_ccm_bcr(cpu); 203 204 read_decode_mmu_bcr(); 205 read_decode_cache_bcr(); 206 207 if (is_isa_arcompact()) { 208 struct bcr_fp_arcompact sp, dp; 209 struct bcr_bpu_arcompact bpu; 210 211 READ_BCR(ARC_REG_FP_BCR, sp); 212 READ_BCR(ARC_REG_DPFP_BCR, dp); 213 cpu->extn.fpu_sp = sp.ver ? 1 : 0; 214 cpu->extn.fpu_dp = dp.ver ? 1 : 0; 215 216 READ_BCR(ARC_REG_BPU_BCR, bpu); 217 cpu->bpu.ver = bpu.ver; 218 cpu->bpu.full = bpu.fam ? 1 : 0; 219 if (bpu.ent) { 220 cpu->bpu.num_cache = 256 << (bpu.ent - 1); 221 cpu->bpu.num_pred = 256 << (bpu.ent - 1); 222 } 223 } else { 224 struct bcr_fp_arcv2 spdp; 225 struct bcr_bpu_arcv2 bpu; 226 227 READ_BCR(ARC_REG_FP_V2_BCR, spdp); 228 cpu->extn.fpu_sp = spdp.sp ? 1 : 0; 229 cpu->extn.fpu_dp = spdp.dp ? 1 : 0; 230 231 READ_BCR(ARC_REG_BPU_BCR, bpu); 232 cpu->bpu.ver = bpu.ver; 233 cpu->bpu.full = bpu.ft; 234 cpu->bpu.num_cache = 256 << bpu.bce; 235 cpu->bpu.num_pred = 2048 << bpu.pte; 236 cpu->bpu.ret_stk = 4 << bpu.rse; 237 238 /* if dual issue hardware, is it enabled ? */ 239 if (cpu->extn.dual) { 240 unsigned int exec_ctrl; 241 242 READ_BCR(AUX_EXEC_CTRL, exec_ctrl); 243 cpu->extn.dual_enb = !(exec_ctrl & 1); 244 } 245 } 246 247 READ_BCR(ARC_REG_AP_BCR, ap); 248 if (ap.ver) { 249 cpu->extn.ap_num = 2 << ap.num; 250 cpu->extn.ap_full = !ap.min; 251 } 252 253 READ_BCR(ARC_REG_SMART_BCR, bcr); 254 cpu->extn.smart = bcr.ver ? 1 : 0; 255 256 READ_BCR(ARC_REG_RTT_BCR, bcr); 257 cpu->extn.rtt = bcr.ver ? 1 : 0; 258 259 READ_BCR(ARC_REG_ISA_CFG_BCR, isa); 260 261 /* some hacks for lack of feature BCR info in old ARC700 cores */ 262 if (is_isa_arcompact()) { 263 if (!isa.ver) /* ISA BCR absent, use Kconfig info */ 264 cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); 265 else { 266 /* ARC700_BUILD only has 2 bits of isa info */ 267 struct bcr_generic bcr = *(struct bcr_generic *)&isa; 268 cpu->isa.atomic = bcr.info & 1; 269 } 270 271 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); 272 273 /* there's no direct way to distinguish 750 vs. 770 */ 274 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3)) 275 cpu->name = "ARC750"; 276 } else { 277 cpu->isa = isa; 278 } 279 } 280 281 static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) 282 { 283 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 284 struct bcr_identity *core = &cpu->core; 285 int n = 0; 286 287 FIX_PTR(cpu); 288 289 n += scnprintf(buf + n, len - n, 290 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", 291 core->family, core->cpu_id, core->chip_id); 292 293 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n", 294 cpu_id, cpu->name, cpu->release, 295 is_isa_arcompact() ? "ARCompact" : "ARCv2", 296 IS_AVAIL1(cpu->isa.be, "[Big-Endian]"), 297 IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue ")); 298 299 n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ", 300 IS_AVAIL1(cpu->extn.timer0, "Timer0 "), 301 IS_AVAIL1(cpu->extn.timer1, "Timer1 "), 302 IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT), 303 IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT)); 304 305 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s", 306 IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC), 307 IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), 308 IS_AVAIL2(cpu->isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS)); 309 310 #if defined(__ARC_UNALIGNED__) && !defined(CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS) 311 /* 312 * gcc 7.3.1 (GNU 2018.03) onwards generate unaligned access by default 313 * but -mno-unaligned-access to disable that didn't work until gcc 8.2.1 314 * (GNU 2019.03). So landing here implies the interim period, when 315 * despite Kconfig being off, gcc is generating unaligned accesses which 316 * could bomb later on. So better to disallow such broken builds 317 */ 318 BUILD_BUG_ON_MSG(1, "gcc doesn't support -mno-unaligned-access"); 319 #endif 320 321 n += scnprintf(buf + n, len - n, "\n\t\t: "); 322 323 if (cpu->extn_mpy.ver) { 324 if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */ 325 n += scnprintf(buf + n, len - n, "mpy "); 326 } else { 327 int opt = 2; /* stock MPY/MPYH */ 328 329 if (cpu->extn_mpy.dsp) /* OPT 7-9 */ 330 opt = cpu->extn_mpy.dsp + 6; 331 332 n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt); 333 } 334 } 335 336 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n", 337 IS_AVAIL1(cpu->isa.div_rem, "div_rem "), 338 IS_AVAIL1(cpu->extn.norm, "norm "), 339 IS_AVAIL1(cpu->extn.barrel, "barrel-shift "), 340 IS_AVAIL1(cpu->extn.swap, "swap "), 341 IS_AVAIL1(cpu->extn.minmax, "minmax "), 342 IS_AVAIL1(cpu->extn.crc, "crc "), 343 IS_AVAIL2(cpu->extn.swape, "swape", CONFIG_ARC_HAS_SWAPE)); 344 345 if (cpu->bpu.ver) 346 n += scnprintf(buf + n, len - n, 347 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d", 348 IS_AVAIL1(cpu->bpu.full, "full"), 349 IS_AVAIL1(!cpu->bpu.full, "partial"), 350 cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk); 351 352 if (is_isa_arcv2()) { 353 struct bcr_lpb lpb; 354 355 READ_BCR(ARC_REG_LPB_BUILD, lpb); 356 if (lpb.ver) { 357 unsigned int ctl; 358 ctl = read_aux_reg(ARC_REG_LPB_CTRL); 359 360 n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s", 361 lpb.entries, 362 IS_DISABLED_RUN(!ctl)); 363 } 364 } 365 366 n += scnprintf(buf + n, len - n, "\n"); 367 return buf; 368 } 369 370 static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) 371 { 372 int n = 0; 373 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 374 375 FIX_PTR(cpu); 376 377 n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base); 378 379 if (cpu->extn.fpu_sp || cpu->extn.fpu_dp) 380 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", 381 IS_AVAIL1(cpu->extn.fpu_sp, "SP "), 382 IS_AVAIL1(cpu->extn.fpu_dp, "DP ")); 383 384 if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) { 385 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s", 386 IS_AVAIL1(cpu->extn.smart, "smaRT "), 387 IS_AVAIL1(cpu->extn.rtt, "RTT ")); 388 if (cpu->extn.ap_num) { 389 n += scnprintf(buf + n, len - n, "ActionPoint %d/%s", 390 cpu->extn.ap_num, 391 cpu->extn.ap_full ? "full":"min"); 392 } 393 n += scnprintf(buf + n, len - n, "\n"); 394 } 395 396 if (cpu->dccm.sz || cpu->iccm.sz) 397 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n", 398 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), 399 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); 400 401 if (is_isa_arcv2()) { 402 403 /* Error Protection: ECC/Parity */ 404 struct bcr_erp erp; 405 READ_BCR(ARC_REG_ERP_BUILD, erp); 406 407 if (erp.ver) { 408 struct ctl_erp ctl; 409 READ_BCR(ARC_REG_ERP_CTRL, ctl); 410 411 /* inverted bits: 0 means enabled */ 412 n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n", 413 IS_AVAIL3(erp.ic, !ctl.dpi, "IC "), 414 IS_AVAIL3(erp.dc, !ctl.dpd, "DC "), 415 IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU ")); 416 } 417 } 418 419 n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n", 420 EF_ARC_OSABI_CURRENT >> 8, 421 EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ? 422 "no-legacy-syscalls" : "64-bit data any register aligned"); 423 424 return buf; 425 } 426 427 static void arc_chk_core_config(void) 428 { 429 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 430 int saved = 0, present = 0; 431 char *opt_nm = NULL; 432 433 if (!cpu->extn.timer0) 434 panic("Timer0 is not present!\n"); 435 436 if (!cpu->extn.timer1) 437 panic("Timer1 is not present!\n"); 438 439 #ifdef CONFIG_ARC_HAS_DCCM 440 /* 441 * DCCM can be arbit placed in hardware. 442 * Make sure it's placement/sz matches what Linux is built with 443 */ 444 if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr) 445 panic("Linux built with incorrect DCCM Base address\n"); 446 447 if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz) 448 panic("Linux built with incorrect DCCM Size\n"); 449 #endif 450 451 #ifdef CONFIG_ARC_HAS_ICCM 452 if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz) 453 panic("Linux built with incorrect ICCM Size\n"); 454 #endif 455 456 /* 457 * FP hardware/software config sanity 458 * -If hardware present, kernel needs to save/restore FPU state 459 * -If not, it will crash trying to save/restore the non-existant regs 460 */ 461 462 if (is_isa_arcompact()) { 463 opt_nm = "CONFIG_ARC_FPU_SAVE_RESTORE"; 464 saved = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE); 465 466 /* only DPDP checked since SP has no arch visible regs */ 467 present = cpu->extn.fpu_dp; 468 } else { 469 opt_nm = "CONFIG_ARC_HAS_ACCL_REGS"; 470 saved = IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS); 471 472 /* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */ 473 present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp; 474 } 475 476 if (present && !saved) 477 pr_warn("Enable %s for working apps\n", opt_nm); 478 else if (!present && saved) 479 panic("Disable %s, hardware NOT present\n", opt_nm); 480 } 481 482 /* 483 * Initialize and setup the processor core 484 * This is called by all the CPUs thus should not do special case stuff 485 * such as only for boot CPU etc 486 */ 487 488 void setup_processor(void) 489 { 490 char str[512]; 491 int cpu_id = smp_processor_id(); 492 493 read_arc_build_cfg_regs(); 494 arc_init_IRQ(); 495 496 pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); 497 498 arc_mmu_init(); 499 arc_cache_init(); 500 501 pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); 502 pr_info("%s", arc_platform_smp_cpuinfo()); 503 504 arc_chk_core_config(); 505 } 506 507 static inline bool uboot_arg_invalid(unsigned long addr) 508 { 509 /* 510 * Check that it is a untranslated address (although MMU is not enabled 511 * yet, it being a high address ensures this is not by fluke) 512 */ 513 if (addr < PAGE_OFFSET) 514 return true; 515 516 /* Check that address doesn't clobber resident kernel image */ 517 return addr >= (unsigned long)_stext && addr <= (unsigned long)_end; 518 } 519 520 #define IGNORE_ARGS "Ignore U-boot args: " 521 522 /* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */ 523 #define UBOOT_TAG_NONE 0 524 #define UBOOT_TAG_CMDLINE 1 525 #define UBOOT_TAG_DTB 2 526 /* We always pass 0 as magic from U-boot */ 527 #define UBOOT_MAGIC_VALUE 0 528 529 void __init handle_uboot_args(void) 530 { 531 bool use_embedded_dtb = true; 532 bool append_cmdline = false; 533 534 /* check that we know this tag */ 535 if (uboot_tag != UBOOT_TAG_NONE && 536 uboot_tag != UBOOT_TAG_CMDLINE && 537 uboot_tag != UBOOT_TAG_DTB) { 538 pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag); 539 goto ignore_uboot_args; 540 } 541 542 if (uboot_magic != UBOOT_MAGIC_VALUE) { 543 pr_warn(IGNORE_ARGS "non zero uboot magic\n"); 544 goto ignore_uboot_args; 545 } 546 547 if (uboot_tag != UBOOT_TAG_NONE && 548 uboot_arg_invalid((unsigned long)uboot_arg)) { 549 pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg); 550 goto ignore_uboot_args; 551 } 552 553 /* see if U-boot passed an external Device Tree blob */ 554 if (uboot_tag == UBOOT_TAG_DTB) { 555 machine_desc = setup_machine_fdt((void *)uboot_arg); 556 557 /* external Device Tree blob is invalid - use embedded one */ 558 use_embedded_dtb = !machine_desc; 559 } 560 561 if (uboot_tag == UBOOT_TAG_CMDLINE) 562 append_cmdline = true; 563 564 ignore_uboot_args: 565 566 if (use_embedded_dtb) { 567 machine_desc = setup_machine_fdt(__dtb_start); 568 if (!machine_desc) 569 panic("Embedded DT invalid\n"); 570 } 571 572 /* 573 * NOTE: @boot_command_line is populated by setup_machine_fdt() so this 574 * append processing can only happen after. 575 */ 576 if (append_cmdline) { 577 /* Ensure a whitespace between the 2 cmdlines */ 578 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); 579 strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE); 580 } 581 } 582 583 void __init setup_arch(char **cmdline_p) 584 { 585 handle_uboot_args(); 586 587 /* Save unparsed command line copy for /proc/cmdline */ 588 *cmdline_p = boot_command_line; 589 590 /* To force early parsing of things like mem=xxx */ 591 parse_early_param(); 592 593 /* Platform/board specific: e.g. early console registration */ 594 if (machine_desc->init_early) 595 machine_desc->init_early(); 596 597 smp_init_cpus(); 598 599 setup_processor(); 600 setup_arch_memory(); 601 602 /* copy flat DT out of .init and then unflatten it */ 603 unflatten_and_copy_device_tree(); 604 605 /* Can be issue if someone passes cmd line arg "ro" 606 * But that is unlikely so keeping it as it is 607 */ 608 root_mountflags &= ~MS_RDONLY; 609 610 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE) 611 conswitchp = &dummy_con; 612 #endif 613 614 arc_unwind_init(); 615 } 616 617 /* 618 * Called from start_kernel() - boot CPU only 619 */ 620 void __init time_init(void) 621 { 622 of_clk_init(NULL); 623 timer_probe(); 624 } 625 626 static int __init customize_machine(void) 627 { 628 if (machine_desc->init_machine) 629 machine_desc->init_machine(); 630 631 return 0; 632 } 633 arch_initcall(customize_machine); 634 635 static int __init init_late_machine(void) 636 { 637 if (machine_desc->init_late) 638 machine_desc->init_late(); 639 640 return 0; 641 } 642 late_initcall(init_late_machine); 643 /* 644 * Get CPU information for use by the procfs. 645 */ 646 647 #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c))) 648 #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p)) 649 650 static int show_cpuinfo(struct seq_file *m, void *v) 651 { 652 char *str; 653 int cpu_id = ptr_to_cpu(v); 654 struct device *cpu_dev = get_cpu_device(cpu_id); 655 struct clk *cpu_clk; 656 unsigned long freq = 0; 657 658 if (!cpu_online(cpu_id)) { 659 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); 660 goto done; 661 } 662 663 str = (char *)__get_free_page(GFP_KERNEL); 664 if (!str) 665 goto done; 666 667 seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 668 669 cpu_clk = clk_get(cpu_dev, NULL); 670 if (IS_ERR(cpu_clk)) { 671 seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n", 672 cpu_id); 673 } else { 674 freq = clk_get_rate(cpu_clk); 675 } 676 if (freq) 677 seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n", 678 freq / 1000000, (freq / 10000) % 100); 679 680 seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", 681 loops_per_jiffy / (500000 / HZ), 682 (loops_per_jiffy / (5000 / HZ)) % 100); 683 684 seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 685 seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); 686 seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); 687 seq_printf(m, arc_platform_smp_cpuinfo()); 688 689 free_page((unsigned long)str); 690 done: 691 seq_printf(m, "\n"); 692 693 return 0; 694 } 695 696 static void *c_start(struct seq_file *m, loff_t *pos) 697 { 698 /* 699 * Callback returns cpu-id to iterator for show routine, NULL to stop. 700 * However since NULL is also a valid cpu-id (0), we use a round-about 701 * way to pass it w/o having to kmalloc/free a 2 byte string. 702 * Encode cpu-id as 0xFFcccc, which is decoded by show routine. 703 */ 704 return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL; 705 } 706 707 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 708 { 709 ++*pos; 710 return c_start(m, pos); 711 } 712 713 static void c_stop(struct seq_file *m, void *v) 714 { 715 } 716 717 const struct seq_operations cpuinfo_op = { 718 .start = c_start, 719 .next = c_next, 720 .stop = c_stop, 721 .show = show_cpuinfo 722 }; 723 724 static DEFINE_PER_CPU(struct cpu, cpu_topology); 725 726 static int __init topology_init(void) 727 { 728 int cpu; 729 730 for_each_present_cpu(cpu) 731 register_cpu(&per_cpu(cpu_topology, cpu), cpu); 732 733 return 0; 734 } 735 736 subsys_initcall(topology_init); 737