1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 295d6976dSVineet Gupta /* 395d6976dSVineet Gupta * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 495d6976dSVineet Gupta * 595d6976dSVineet Gupta * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs 695d6976dSVineet Gupta * -flush_cache_dup_mm (fork) 795d6976dSVineet Gupta * -likewise for flush_cache_mm (exit/execve) 895d6976dSVineet Gupta * -likewise for flush_cache_{range,page} (munmap, exit, COW-break) 995d6976dSVineet Gupta * 1095d6976dSVineet Gupta * vineetg: April 2008 1195d6976dSVineet Gupta * -Added a critical CacheLine flush to copy_to_user_page( ) which 1295d6976dSVineet Gupta * was causing gdbserver to not setup breakpoints consistently 1395d6976dSVineet Gupta */ 1495d6976dSVineet Gupta 1595d6976dSVineet Gupta #ifndef _ASM_CACHEFLUSH_H 1695d6976dSVineet Gupta #define _ASM_CACHEFLUSH_H 1795d6976dSVineet Gupta 1895d6976dSVineet Gupta #include <linux/mm.h> 195bba49f5SVineet Gupta #include <asm/shmparam.h> 2095d6976dSVineet Gupta 2195d6976dSVineet Gupta void flush_cache_all(void); 2295d6976dSVineet Gupta 2328b4af72SVineet Gupta void flush_icache_range(unsigned long kstart, unsigned long kend); 2428b4af72SVineet Gupta void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len); 25ac4cfaccSMatthew Wilcox (Oracle) void __inv_icache_pages(phys_addr_t paddr, unsigned long vaddr, unsigned nr); 26ac4cfaccSMatthew Wilcox (Oracle) void __flush_dcache_pages(phys_addr_t paddr, unsigned long vaddr, unsigned nr); 2795d6976dSVineet Gupta 2895d6976dSVineet Gupta #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 2995d6976dSVineet Gupta 3095d6976dSVineet Gupta void flush_dcache_page(struct page *page); 31ac4cfaccSMatthew Wilcox (Oracle) void flush_dcache_folio(struct folio *folio); 32ac4cfaccSMatthew Wilcox (Oracle) #define flush_dcache_folio flush_dcache_folio 3395d6976dSVineet Gupta 34f5db19e9SVineet Gupta void dma_cache_wback_inv(phys_addr_t start, unsigned long sz); 35f5db19e9SVineet Gupta void dma_cache_inv(phys_addr_t start, unsigned long sz); 36f5db19e9SVineet Gupta void dma_cache_wback(phys_addr_t start, unsigned long sz); 3795d6976dSVineet Gupta 3895d6976dSVineet Gupta #define flush_dcache_mmap_lock(mapping) do { } while (0) 3995d6976dSVineet Gupta #define flush_dcache_mmap_unlock(mapping) do { } while (0) 4095d6976dSVineet Gupta 4195d6976dSVineet Gupta /* TBD: optimize this */ 4295d6976dSVineet Gupta #define flush_cache_vmap(start, end) flush_cache_all() 43*7a92fc8bSAlexandre Ghiti #define flush_cache_vmap_early(start, end) do { } while (0) 4495d6976dSVineet Gupta #define flush_cache_vunmap(start, end) flush_cache_all() 4595d6976dSVineet Gupta 464102b533SVineet Gupta #define flush_cache_dup_mm(mm) /* called on fork (VIVT only) */ 474102b533SVineet Gupta 484102b533SVineet Gupta #define flush_cache_mm(mm) /* called on munmap/exit */ 494102b533SVineet Gupta #define flush_cache_range(mm, u_vstart, u_vend) 5095d6976dSVineet Gupta #define flush_cache_page(vma, u_vaddr, pfn) /* PF handling/COW-break */ 5195d6976dSVineet Gupta 5295d6976dSVineet Gupta /* 5395d6976dSVineet Gupta * A new pagecache page has PG_arch_1 clear - thus dcache dirty by default 544102b533SVineet Gupta * This works around some PIO based drivers which don't call flush_dcache_page 554102b533SVineet Gupta * to record that they dirtied the dcache 564102b533SVineet Gupta */ 574102b533SVineet Gupta #define PG_dc_clean PG_arch_1 584102b533SVineet Gupta 594102b533SVineet Gupta #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 604102b533SVineet Gupta do { \ 614102b533SVineet Gupta memcpy(dst, src, len); \ 624102b533SVineet Gupta if (vma->vm_flags & VM_EXEC) \ 634102b533SVineet Gupta __sync_icache_dcache((unsigned long)(dst), vaddr, len); \ 644102b533SVineet Gupta } while (0) 654102b533SVineet Gupta 664102b533SVineet Gupta #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 674102b533SVineet Gupta memcpy(dst, src, len); \ 684102b533SVineet Gupta 694102b533SVineet Gupta #endif 704102b533SVineet Gupta