116a14673SYassine Oudjana# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
216a14673SYassine Oudjana%YAML 1.2
316a14673SYassine Oudjana---
432671977SRob Herring$id: http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#
532671977SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml#
616a14673SYassine Oudjana
716a14673SYassine Oudjanatitle: MediaTek AP Mixedsys Controller
816a14673SYassine Oudjana
916a14673SYassine Oudjanamaintainers:
1016a14673SYassine Oudjana  - Michael Turquette <[email protected]>
1116a14673SYassine Oudjana  - Stephen Boyd <[email protected]>
1216a14673SYassine Oudjana
1316a14673SYassine Oudjanadescription:
1416a14673SYassine Oudjana  The Mediatek apmixedsys controller provides PLLs to the system.
15*ea1cca02SYassine Oudjana  The clock values can be found in <dt-bindings/clock/mt*-clk.h>
16*ea1cca02SYassine Oudjana  and <dt-bindings/clock/mediatek,mt*-apmixedsys.h>.
1716a14673SYassine Oudjana
1816a14673SYassine Oudjanaproperties:
1916a14673SYassine Oudjana  compatible:
2016a14673SYassine Oudjana    oneOf:
2116a14673SYassine Oudjana      - enum:
2216a14673SYassine Oudjana          - mediatek,mt6797-apmixedsys
2316a14673SYassine Oudjana          - mediatek,mt7622-apmixedsys
24cc4d9e0cSDaniel Golle          - mediatek,mt7981-apmixedsys
2516a14673SYassine Oudjana          - mediatek,mt7986-apmixedsys
26afd36e9dSDaniel Golle          - mediatek,mt7988-apmixedsys
2716a14673SYassine Oudjana          - mediatek,mt8135-apmixedsys
2816a14673SYassine Oudjana          - mediatek,mt8173-apmixedsys
2916a14673SYassine Oudjana          - mediatek,mt8516-apmixedsys
3016a14673SYassine Oudjana      - items:
3116a14673SYassine Oudjana          - const: mediatek,mt7623-apmixedsys
3216a14673SYassine Oudjana          - const: mediatek,mt2701-apmixedsys
3316a14673SYassine Oudjana          - const: syscon
3416a14673SYassine Oudjana      - items:
3516a14673SYassine Oudjana          - enum:
3616a14673SYassine Oudjana              - mediatek,mt2701-apmixedsys
3716a14673SYassine Oudjana              - mediatek,mt2712-apmixedsys
38*ea1cca02SYassine Oudjana              - mediatek,mt6735-apmixedsys
3916a14673SYassine Oudjana              - mediatek,mt6765-apmixedsys
405e938ef6SRob Herring (Arm)              - mediatek,mt6779-apmixed
41d5099c95SAngeloGioacchino Del Regno              - mediatek,mt6795-apmixedsys
4216a14673SYassine Oudjana              - mediatek,mt7629-apmixedsys
4316a14673SYassine Oudjana              - mediatek,mt8167-apmixedsys
4416a14673SYassine Oudjana              - mediatek,mt8183-apmixedsys
4516a14673SYassine Oudjana          - const: syscon
4616a14673SYassine Oudjana
4716a14673SYassine Oudjana  reg:
4816a14673SYassine Oudjana    maxItems: 1
4916a14673SYassine Oudjana
5016a14673SYassine Oudjana  '#clock-cells':
5116a14673SYassine Oudjana    const: 1
5216a14673SYassine Oudjana
5316a14673SYassine Oudjanarequired:
5416a14673SYassine Oudjana  - compatible
5516a14673SYassine Oudjana  - reg
5616a14673SYassine Oudjana  - '#clock-cells'
5716a14673SYassine Oudjana
5816a14673SYassine OudjanaadditionalProperties: false
5916a14673SYassine Oudjana
6016a14673SYassine Oudjanaexamples:
6116a14673SYassine Oudjana  - |
6216a14673SYassine Oudjana    apmixedsys: clock-controller@10209000 {
6316a14673SYassine Oudjana        compatible = "mediatek,mt8173-apmixedsys";
6416a14673SYassine Oudjana        reg = <0x10209000 0x1000>;
6516a14673SYassine Oudjana        #clock-cells = <1>;
6616a14673SYassine Oudjana    };
67