1What:           /sys/kernel/debug/hisi_zip/<bdf>/comp_core[01]/regs
2Date:           Nov 2018
3Contact:        [email protected]
4Description:    Dump of compression cores related debug registers.
5		Only available for PF.
6
7What:           /sys/kernel/debug/hisi_zip/<bdf>/decomp_core[0-5]/regs
8Date:           Nov 2018
9Contact:        [email protected]
10Description:    Dump of decompression cores related debug registers.
11		Only available for PF.
12
13What:           /sys/kernel/debug/hisi_zip/<bdf>/clear_enable
14Date:           Nov 2018
15Contact:        [email protected]
16Description:    Compression/decompression core debug registers read clear
17		control. 1 means enable register read clear, otherwise 0.
18		Writing to this file has no functional effect, only enable or
19		disable counters clear after reading of these registers.
20		Only available for PF.
21
22What:           /sys/kernel/debug/hisi_zip/<bdf>/current_qm
23Date:           Nov 2018
24Contact:        [email protected]
25Description:    One ZIP controller has one PF and multiple VFs, each function
26		has a QM. Select the QM which below qm refers to.
27		Only available for PF.
28
29What:           /sys/kernel/debug/hisi_zip/<bdf>/qm/qm_regs
30Date:           Nov 2018
31Contact:        [email protected]
32Description:    Dump of QM related debug registers.
33		Available for PF and VF in host. VF in guest currently only
34		has one debug register.
35
36What:           /sys/kernel/debug/hisi_zip/<bdf>/qm/current_q
37Date:           Nov 2018
38Contact:        [email protected]
39Description:    One QM may contain multiple queues. Select specific queue to
40		show its debug registers in above qm_regs.
41		Only available for PF.
42
43What:           /sys/kernel/debug/hisi_zip/<bdf>/qm/clear_enable
44Date:           Nov 2018
45Contact:        [email protected]
46Description:    QM debug registers(qm_regs) read clear control. 1 means enable
47		register read clear, otherwise 0.
48		Writing to this file has no functional effect, only enable or
49		disable counters clear after reading of these registers.
50		Only available for PF.
51