1 /* 2 * (C) Copyright IBM Corporation 2006 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 */ 24 25 /** 26 * \file common_interface.c 27 * Platform independent interface glue. 28 * 29 * \author Ian Romanick <[email protected]> 30 */ 31 32 #include <stdlib.h> 33 #include <string.h> 34 #include <errno.h> 35 36 #include "pciaccess.h" 37 #include "pciaccess_private.h" 38 39 #if defined(__linux__) || defined(__GLIBC__) 40 #include <byteswap.h> 41 42 #if __BYTE_ORDER == __BIG_ENDIAN 43 # define LETOH_16(x) bswap_16(x) 44 # define HTOLE_16(x) bswap_16(x) 45 # define LETOH_32(x) bswap_32(x) 46 # define HTOLE_32(x) bswap_32(x) 47 #else 48 # define LETOH_16(x) (x) 49 # define HTOLE_16(x) (x) 50 # define LETOH_32(x) (x) 51 # define HTOLE_32(x) (x) 52 #endif /* linux */ 53 54 #elif defined(__sun) 55 56 #include <sys/byteorder.h> 57 58 #ifdef _BIG_ENDIAN 59 # define LETOH_16(x) BSWAP_16(x) 60 # define HTOLE_16(x) BSWAP_16(x) 61 # define LETOH_32(x) BSWAP_32(x) 62 # define HTOLE_32(x) BSWAP_32(x) 63 #else 64 # define LETOH_16(x) (x) 65 # define HTOLE_16(x) (x) 66 # define LETOH_32(x) (x) 67 # define HTOLE_32(x) (x) 68 #endif /* Solaris */ 69 70 #else 71 72 #include <sys/endian.h> 73 74 #define HTOLE_16(x) htole16(x) 75 #define HTOLE_32(x) htole32(x) 76 77 #if defined(__FreeBSD__) || defined(__DragonFly__) || defined(__NetBSD__) 78 #define LETOH_16(x) le16toh(x) 79 #define LETOH_32(x) le32toh(x) 80 #else 81 #define LETOH_16(x) letoh16(x) 82 #define LETOH_32(x) letoh32(x) 83 #endif 84 85 #endif /* others */ 86 87 /** 88 * Read a device's expansion ROM. 89 * 90 * Reads the device's expansion ROM and stores the data in the memory pointed 91 * to by \c buffer. The buffer must be at least \c pci_device::rom_size 92 * bytes. 93 * 94 * \param dev Device whose expansion ROM is to be read. 95 * \param buffer Memory in which to store the ROM. 96 * 97 * \return 98 * Zero on success or an \c errno value on failure. 99 */ 100 int 101 pci_device_read_rom( struct pci_device * dev, void * buffer ) 102 { 103 if ( (dev == NULL) || (buffer == NULL) ) { 104 return EFAULT; 105 } 106 107 108 return (pci_sys->methods->read_rom)( dev, buffer ); 109 } 110 111 112 /** 113 * Probe a PCI device to learn information about the device. 114 * 115 * Probes a PCI device to learn various information about the device. Before 116 * calling this function, the only public fields in the \c pci_device 117 * structure that have valid values are \c pci_device::domain, 118 * \c pci_device::bus, \c pci_device::dev, and \c pci_device::func. 119 * 120 * \param dev Device to be probed. 121 * 122 * \return 123 * Zero on success or an \c errno value on failure. 124 */ 125 int 126 pci_device_probe( struct pci_device * dev ) 127 { 128 if ( dev == NULL ) { 129 return EFAULT; 130 } 131 132 133 return (pci_sys->methods->probe)( dev ); 134 } 135 136 137 /** 138 * Map the specified BAR so that it can be accessed by the CPU. 139 * 140 * Maps the specified BAR for access by the processor. The pointer to the 141 * mapped region is stored in the \c pci_mem_region::memory pointer for the 142 * BAR. 143 * 144 * \param dev Device whose memory region is to be mapped. 145 * \param region Region, on the range [0, 5], that is to be mapped. 146 * \param write_enable Map for writing (non-zero). 147 * 148 * \return 149 * Zero on success or an \c errno value on failure. 150 * 151 * \sa pci_device_map_range, pci_device_unmap_range 152 * \deprecated 153 */ 154 int 155 pci_device_map_region(struct pci_device * dev, unsigned region, 156 int write_enable) 157 { 158 const unsigned map_flags = 159 (write_enable) ? PCI_DEV_MAP_FLAG_WRITABLE : 0; 160 161 if ((region > 5) || (dev->regions[region].size == 0)) { 162 return ENOENT; 163 } 164 165 if (dev->regions[region].memory != NULL) { 166 return 0; 167 } 168 169 return pci_device_map_range(dev, dev->regions[region].base_addr, 170 dev->regions[region].size, map_flags, 171 &dev->regions[region].memory); 172 } 173 174 175 /** 176 * Map the specified memory range so that it can be accessed by the CPU. 177 * 178 * Maps the specified memory range for access by the processor. The pointer 179 * to the mapped region is stored in \c addr. In addition, the 180 * \c pci_mem_region::memory pointer for the BAR will be updated. 181 * 182 * \param dev Device whose memory region is to be mapped. 183 * \param base Base address of the range to be mapped. 184 * \param size Size of the range to be mapped. 185 * \param write_enable Map for writing (non-zero). 186 * \param addr Location to store the mapped address. 187 * 188 * \return 189 * Zero on success or an \c errno value on failure. 190 * 191 * \sa pci_device_map_range 192 */ 193 int pci_device_map_memory_range(struct pci_device *dev, 194 pciaddr_t base, pciaddr_t size, 195 int write_enable, void **addr) 196 { 197 return pci_device_map_range(dev, base, size, 198 (write_enable) ? PCI_DEV_MAP_FLAG_WRITABLE : 0, 199 addr); 200 } 201 202 203 /** 204 * Map the specified memory range so that it can be accessed by the CPU. 205 * 206 * Maps the specified memory range for access by the processor. The pointer 207 * to the mapped region is stored in \c addr. In addition, the 208 * \c pci_mem_region::memory pointer for the BAR will be updated. 209 * 210 * \param dev Device whose memory region is to be mapped. 211 * \param base Base address of the range to be mapped. 212 * \param size Size of the range to be mapped. 213 * \param map_flags Flag bits controlling how the mapping is accessed. 214 * \param addr Location to store the mapped address. 215 * 216 * \return 217 * Zero on success or an \c errno value on failure. 218 * 219 * \sa pci_device_unmap_range 220 */ 221 int 222 pci_device_map_range(struct pci_device *dev, pciaddr_t base, 223 pciaddr_t size, unsigned map_flags, 224 void **addr) 225 { 226 struct pci_device_private *const devp = 227 (struct pci_device_private *) dev; 228 struct pci_device_mapping *mappings; 229 unsigned region; 230 unsigned i; 231 int err = 0; 232 233 234 *addr = NULL; 235 236 if (dev == NULL) { 237 return EFAULT; 238 } 239 240 241 for (region = 0; region < 6; region++) { 242 const struct pci_mem_region const* r = &dev->regions[region]; 243 244 if (r->size != 0) { 245 if ((r->base_addr <= base) && ((r->base_addr + r->size) > base)) { 246 if ((base + size) > (r->base_addr + r->size)) { 247 return E2BIG; 248 } 249 250 break; 251 } 252 } 253 } 254 255 if (region > 5) { 256 return ENOENT; 257 } 258 259 /* Make sure that there isn't already a mapping with the same base and 260 * size. 261 */ 262 for (i = 0; i < devp->num_mappings; i++) { 263 if ((devp->mappings[i].base == base) 264 && (devp->mappings[i].size == size)) { 265 return EINVAL; 266 } 267 } 268 269 270 mappings = realloc(devp->mappings, 271 (sizeof(devp->mappings[0]) * (devp->num_mappings + 1))); 272 if (mappings == NULL) { 273 return ENOMEM; 274 } 275 276 mappings[devp->num_mappings].base = base; 277 mappings[devp->num_mappings].size = size; 278 mappings[devp->num_mappings].region = region; 279 mappings[devp->num_mappings].flags = map_flags; 280 mappings[devp->num_mappings].memory = NULL; 281 282 if (dev->regions[region].memory == NULL) { 283 err = (*pci_sys->methods->map_range)(dev, 284 &mappings[devp->num_mappings]); 285 } 286 287 if (err == 0) { 288 *addr = mappings[devp->num_mappings].memory; 289 devp->num_mappings++; 290 } else { 291 mappings = realloc(devp->mappings, 292 (sizeof(devp->mappings[0]) * devp->num_mappings)); 293 } 294 295 devp->mappings = mappings; 296 297 return err; 298 } 299 300 301 /** 302 * Unmap the specified BAR so that it can no longer be accessed by the CPU. 303 * 304 * Unmaps the specified BAR that was previously mapped via 305 * \c pci_device_map_region. 306 * 307 * \param dev Device whose memory region is to be mapped. 308 * \param region Region, on the range [0, 5], that is to be mapped. 309 * 310 * \return 311 * Zero on success or an \c errno value on failure. 312 * 313 * \sa pci_device_map_range, pci_device_unmap_range 314 * \deprecated 315 */ 316 int 317 pci_device_unmap_region( struct pci_device * dev, unsigned region ) 318 { 319 int err; 320 321 if (dev == NULL) { 322 return EFAULT; 323 } 324 325 if ((region > 5) || (dev->regions[region].size == 0)) { 326 return ENOENT; 327 } 328 329 err = pci_device_unmap_range(dev, dev->regions[region].memory, 330 dev->regions[region].size); 331 if (!err) { 332 dev->regions[region].memory = NULL; 333 } 334 335 return err; 336 } 337 338 339 /** 340 * Unmap the specified memory range so that it can no longer be accessed by the CPU. 341 * 342 * Unmaps the specified memory range that was previously mapped via 343 * \c pci_device_map_memory_range. 344 * 345 * \param dev Device whose memory is to be unmapped. 346 * \param memory Pointer to the base of the mapped range. 347 * \param size Size, in bytes, of the range to be unmapped. 348 * 349 * \return 350 * Zero on success or an \c errno value on failure. 351 * 352 * \sa pci_device_map_range, pci_device_unmap_range 353 * \deprecated 354 */ 355 int 356 pci_device_unmap_memory_range(struct pci_device *dev, void *memory, 357 pciaddr_t size) 358 { 359 return pci_device_unmap_range(dev, memory, size); 360 } 361 362 363 /** 364 * Unmap the specified memory range so that it can no longer be accessed by the CPU. 365 * 366 * Unmaps the specified memory range that was previously mapped via 367 * \c pci_device_map_memory_range. 368 * 369 * \param dev Device whose memory is to be unmapped. 370 * \param memory Pointer to the base of the mapped range. 371 * \param size Size, in bytes, of the range to be unmapped. 372 * 373 * \return 374 * Zero on success or an \c errno value on failure. 375 * 376 * \sa pci_device_map_range 377 */ 378 int 379 pci_device_unmap_range(struct pci_device *dev, void *memory, 380 pciaddr_t size) 381 { 382 struct pci_device_private *const devp = 383 (struct pci_device_private *) dev; 384 unsigned i; 385 int err; 386 387 388 if (dev == NULL) { 389 return EFAULT; 390 } 391 392 for (i = 0; i < devp->num_mappings; i++) { 393 if ((devp->mappings[i].memory == memory) 394 && (devp->mappings[i].size == size)) { 395 break; 396 } 397 } 398 399 if (i == devp->num_mappings) { 400 return ENOENT; 401 } 402 403 404 err = (*pci_sys->methods->unmap_range)(dev, &devp->mappings[i]); 405 if (!err) { 406 const unsigned entries_to_move = (devp->num_mappings - i) - 1; 407 408 if (entries_to_move > 0) { 409 (void) memmove(&devp->mappings[i], 410 &devp->mappings[i + 1], 411 entries_to_move * sizeof(devp->mappings[0])); 412 } 413 414 devp->num_mappings--; 415 devp->mappings = realloc(devp->mappings, 416 (sizeof(devp->mappings[0]) * devp->num_mappings)); 417 } 418 419 return err; 420 } 421 422 423 /** 424 * Read arbitrary bytes from device's PCI config space 425 * 426 * Reads data from the device's PCI configuration space. As with the system 427 * read command, less data may be returned, without an error, than was 428 * requested. This is particularly the case if a non-root user tries to read 429 * beyond the first 64-bytes of configuration space. 430 * 431 * \param dev Device whose PCI configuration data is to be read. 432 * \param data Location to store the data 433 * \param offset Initial byte offset to read 434 * \param size Total number of bytes to read 435 * \param bytes_read Location to store the actual number of bytes read. This 436 * pointer may be \c NULL. 437 * 438 * \returns 439 * Zero on success or an errno value on failure. 440 * 441 * \note 442 * Data read from PCI configuration space using this routine is \b not 443 * byte-swapped to the host's byte order. PCI configuration data is always 444 * stored in little-endian order, and that is what this routine returns. 445 */ 446 int 447 pci_device_cfg_read( struct pci_device * dev, void * data, 448 pciaddr_t offset, pciaddr_t size, 449 pciaddr_t * bytes_read ) 450 { 451 pciaddr_t scratch; 452 453 if ( (dev == NULL) || (data == NULL) ) { 454 return EFAULT; 455 } 456 457 return pci_sys->methods->read( dev, data, offset, size, 458 (bytes_read == NULL) 459 ? & scratch : bytes_read ); 460 } 461 462 463 int 464 pci_device_cfg_read_u8( struct pci_device * dev, uint8_t * data, 465 pciaddr_t offset ) 466 { 467 pciaddr_t bytes; 468 int err = pci_device_cfg_read( dev, data, offset, 1, & bytes ); 469 470 if ( (err == 0) && (bytes != 1) ) { 471 err = ENXIO; 472 } 473 474 return err; 475 } 476 477 478 int 479 pci_device_cfg_read_u16( struct pci_device * dev, uint16_t * data, 480 pciaddr_t offset ) 481 { 482 pciaddr_t bytes; 483 int err = pci_device_cfg_read( dev, data, offset, 2, & bytes ); 484 485 if ( (err == 0) && (bytes != 2) ) { 486 err = ENXIO; 487 } 488 489 *data = LETOH_16( *data ); 490 return err; 491 } 492 493 494 int 495 pci_device_cfg_read_u32( struct pci_device * dev, uint32_t * data, 496 pciaddr_t offset ) 497 { 498 pciaddr_t bytes; 499 int err = pci_device_cfg_read( dev, data, offset, 4, & bytes ); 500 501 if ( (err == 0) && (bytes != 4) ) { 502 err = ENXIO; 503 } 504 505 *data = LETOH_32( *data ); 506 return err; 507 } 508 509 510 /** 511 * Write arbitrary bytes to device's PCI config space 512 * 513 * Writes data to the device's PCI configuration space. As with the system 514 * write command, less data may be written, without an error, than was 515 * requested. 516 * 517 * \param dev Device whose PCI configuration data is to be written. 518 * \param data Location of the source data 519 * \param offset Initial byte offset to write 520 * \param size Total number of bytes to write 521 * \param bytes_read Location to store the actual number of bytes written. 522 * This pointer may be \c NULL. 523 * 524 * \returns 525 * Zero on success or an errno value on failure. 526 * 527 * \note 528 * Data written to PCI configuration space using this routine is \b not 529 * byte-swapped from the host's byte order. PCI configuration data is always 530 * stored in little-endian order, so data written with this routine should be 531 * put in that order in advance. 532 */ 533 int 534 pci_device_cfg_write( struct pci_device * dev, const void * data, 535 pciaddr_t offset, pciaddr_t size, 536 pciaddr_t * bytes_written ) 537 { 538 pciaddr_t scratch; 539 540 if ( (dev == NULL) || (data == NULL) ) { 541 return EFAULT; 542 } 543 544 return pci_sys->methods->write( dev, data, offset, size, 545 (bytes_written == NULL) 546 ? & scratch : bytes_written ); 547 } 548 549 550 int 551 pci_device_cfg_write_u8(struct pci_device *dev, uint8_t data, 552 pciaddr_t offset) 553 { 554 pciaddr_t bytes; 555 int err = pci_device_cfg_write(dev, & data, offset, 1, & bytes); 556 557 if ( (err == 0) && (bytes != 1) ) { 558 err = ENOSPC; 559 } 560 561 562 return err; 563 } 564 565 566 int 567 pci_device_cfg_write_u16(struct pci_device *dev, uint16_t data, 568 pciaddr_t offset) 569 { 570 pciaddr_t bytes; 571 const uint16_t temp = HTOLE_16(data); 572 int err = pci_device_cfg_write( dev, & temp, offset, 2, & bytes ); 573 574 if ( (err == 0) && (bytes != 2) ) { 575 err = ENOSPC; 576 } 577 578 579 return err; 580 } 581 582 583 int 584 pci_device_cfg_write_u32(struct pci_device *dev, uint32_t data, 585 pciaddr_t offset) 586 { 587 pciaddr_t bytes; 588 const uint32_t temp = HTOLE_32(data); 589 int err = pci_device_cfg_write( dev, & temp, offset, 4, & bytes ); 590 591 if ( (err == 0) && (bytes != 4) ) { 592 err = ENOSPC; 593 } 594 595 596 return err; 597 } 598 599 600 int 601 pci_device_cfg_write_bits( struct pci_device * dev, uint32_t mask, 602 uint32_t data, pciaddr_t offset ) 603 { 604 uint32_t temp; 605 int err; 606 607 err = pci_device_cfg_read_u32( dev, & temp, offset ); 608 if ( ! err ) { 609 temp &= ~mask; 610 temp |= data; 611 612 err = pci_device_cfg_write_u32(dev, temp, offset); 613 } 614 615 return err; 616 } 617 618 void 619 pci_device_enable(struct pci_device *dev) 620 { 621 if (dev == NULL) { 622 return; 623 } 624 625 if (pci_sys->methods->enable) 626 pci_sys->methods->enable(dev); 627 } 628