1 /* 2 * (C) Copyright IBM Corporation 2006 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 */ 24 25 /** 26 * \file common_interface.c 27 * Platform independent interface glue. 28 * 29 * \author Ian Romanick <[email protected]> 30 */ 31 32 #include <stdlib.h> 33 #include <string.h> 34 #include <errno.h> 35 36 #include "pciaccess.h" 37 #include "pciaccess_private.h" 38 39 #if defined(__linux__) || defined(__GLIBC__) 40 #include <byteswap.h> 41 42 #if __BYTE_ORDER == __BIG_ENDIAN 43 # define LETOH_16(x) bswap_16(x) 44 # define HTOLE_16(x) bswap_16(x) 45 # define LETOH_32(x) bswap_32(x) 46 # define HTOLE_32(x) bswap_32(x) 47 #else 48 # define LETOH_16(x) (x) 49 # define HTOLE_16(x) (x) 50 # define LETOH_32(x) (x) 51 # define HTOLE_32(x) (x) 52 #endif /* linux */ 53 54 #elif defined(__sun) 55 56 #include <sys/byteorder.h> 57 58 #ifdef _BIG_ENDIAN 59 # define LETOH_16(x) BSWAP_16(x) 60 # define HTOLE_16(x) BSWAP_16(x) 61 # define LETOH_32(x) BSWAP_32(x) 62 # define HTOLE_32(x) BSWAP_32(x) 63 #else 64 # define LETOH_16(x) (x) 65 # define HTOLE_16(x) (x) 66 # define LETOH_32(x) (x) 67 # define HTOLE_32(x) (x) 68 #endif /* Solaris */ 69 70 #else 71 72 #include <sys/endian.h> 73 74 #define HTOLE_16(x) htole16(x) 75 #define HTOLE_32(x) htole32(x) 76 77 #if defined(__FreeBSD__) || defined(__DragonFly__) || defined(__NetBSD__) 78 #define LETOH_16(x) le16toh(x) 79 #define LETOH_32(x) le32toh(x) 80 #else 81 #define LETOH_16(x) letoh16(x) 82 #define LETOH_32(x) letoh32(x) 83 #endif 84 85 #endif /* others */ 86 87 /** 88 * Read a device's expansion ROM. 89 * 90 * Reads the device's expansion ROM and stores the data in the memory pointed 91 * to by \c buffer. The buffer must be at least \c pci_device::rom_size 92 * bytes. 93 * 94 * \param dev Device whose expansion ROM is to be read. 95 * \param buffer Memory in which to store the ROM. 96 * 97 * \return 98 * Zero on success or an \c errno value on failure. 99 */ 100 int 101 pci_device_read_rom( struct pci_device * dev, void * buffer ) 102 { 103 if ( (dev == NULL) || (buffer == NULL) ) { 104 return EFAULT; 105 } 106 107 108 return (pci_sys->methods->read_rom)( dev, buffer ); 109 } 110 111 /** 112 * Probe a PCI (VGA) device to determine if its the boot VGA device 113 * 114 * \param dev Device whose VGA status to query 115 * \return 116 * Zero if not the boot VGA, 1 if the boot VGA. 117 */ 118 int 119 pci_device_is_boot_vga( struct pci_device * dev ) 120 { 121 if (!pci_sys->methods->boot_vga) 122 return 0; 123 return pci_sys->methods->boot_vga( dev ); 124 } 125 126 /** 127 * Probe a PCI device to learn information about the device. 128 * 129 * Probes a PCI device to learn various information about the device. Before 130 * calling this function, the only public fields in the \c pci_device 131 * structure that have valid values are \c pci_device::domain, 132 * \c pci_device::bus, \c pci_device::dev, and \c pci_device::func. 133 * 134 * \param dev Device to be probed. 135 * 136 * \return 137 * Zero on success or an \c errno value on failure. 138 */ 139 int 140 pci_device_probe( struct pci_device * dev ) 141 { 142 if ( dev == NULL ) { 143 return EFAULT; 144 } 145 146 147 return (pci_sys->methods->probe)( dev ); 148 } 149 150 151 /** 152 * Map the specified BAR so that it can be accessed by the CPU. 153 * 154 * Maps the specified BAR for access by the processor. The pointer to the 155 * mapped region is stored in the \c pci_mem_region::memory pointer for the 156 * BAR. 157 * 158 * \param dev Device whose memory region is to be mapped. 159 * \param region Region, on the range [0, 5], that is to be mapped. 160 * \param write_enable Map for writing (non-zero). 161 * 162 * \return 163 * Zero on success or an \c errno value on failure. 164 * 165 * \sa pci_device_map_range, pci_device_unmap_range 166 * \deprecated 167 */ 168 int 169 pci_device_map_region(struct pci_device * dev, unsigned region, 170 int write_enable) 171 { 172 const unsigned map_flags = 173 (write_enable) ? PCI_DEV_MAP_FLAG_WRITABLE : 0; 174 175 if ((region > 5) || (dev->regions[region].size == 0)) { 176 return ENOENT; 177 } 178 179 if (dev->regions[region].memory != NULL) { 180 return 0; 181 } 182 183 return pci_device_map_range(dev, dev->regions[region].base_addr, 184 dev->regions[region].size, map_flags, 185 &dev->regions[region].memory); 186 } 187 188 189 /** 190 * Map the specified memory range so that it can be accessed by the CPU. 191 * 192 * Maps the specified memory range for access by the processor. The pointer 193 * to the mapped region is stored in \c addr. In addition, the 194 * \c pci_mem_region::memory pointer for the BAR will be updated. 195 * 196 * \param dev Device whose memory region is to be mapped. 197 * \param base Base address of the range to be mapped. 198 * \param size Size of the range to be mapped. 199 * \param write_enable Map for writing (non-zero). 200 * \param addr Location to store the mapped address. 201 * 202 * \return 203 * Zero on success or an \c errno value on failure. 204 * 205 * \sa pci_device_map_range 206 */ 207 int pci_device_map_memory_range(struct pci_device *dev, 208 pciaddr_t base, pciaddr_t size, 209 int write_enable, void **addr) 210 { 211 return pci_device_map_range(dev, base, size, 212 (write_enable) ? PCI_DEV_MAP_FLAG_WRITABLE : 0, 213 addr); 214 } 215 216 217 /** 218 * Map the specified memory range so that it can be accessed by the CPU. 219 * 220 * Maps the specified memory range for access by the processor. The pointer 221 * to the mapped region is stored in \c addr. In addition, the 222 * \c pci_mem_region::memory pointer for the BAR will be updated. 223 * 224 * \param dev Device whose memory region is to be mapped. 225 * \param base Base address of the range to be mapped. 226 * \param size Size of the range to be mapped. 227 * \param map_flags Flag bits controlling how the mapping is accessed. 228 * \param addr Location to store the mapped address. 229 * 230 * \return 231 * Zero on success or an \c errno value on failure. 232 * 233 * \sa pci_device_unmap_range 234 */ 235 int 236 pci_device_map_range(struct pci_device *dev, pciaddr_t base, 237 pciaddr_t size, unsigned map_flags, 238 void **addr) 239 { 240 struct pci_device_private *const devp = 241 (struct pci_device_private *) dev; 242 struct pci_device_mapping *mappings; 243 unsigned region; 244 unsigned i; 245 int err = 0; 246 247 248 *addr = NULL; 249 250 if (dev == NULL) { 251 return EFAULT; 252 } 253 254 255 for (region = 0; region < 6; region++) { 256 const struct pci_mem_region const* r = &dev->regions[region]; 257 258 if (r->size != 0) { 259 if ((r->base_addr <= base) && ((r->base_addr + r->size) > base)) { 260 if ((base + size) > (r->base_addr + r->size)) { 261 return E2BIG; 262 } 263 264 break; 265 } 266 } 267 } 268 269 if (region > 5) { 270 return ENOENT; 271 } 272 273 /* Make sure that there isn't already a mapping with the same base and 274 * size. 275 */ 276 for (i = 0; i < devp->num_mappings; i++) { 277 if ((devp->mappings[i].base == base) 278 && (devp->mappings[i].size == size)) { 279 return EINVAL; 280 } 281 } 282 283 284 mappings = realloc(devp->mappings, 285 (sizeof(devp->mappings[0]) * (devp->num_mappings + 1))); 286 if (mappings == NULL) { 287 return ENOMEM; 288 } 289 290 mappings[devp->num_mappings].base = base; 291 mappings[devp->num_mappings].size = size; 292 mappings[devp->num_mappings].region = region; 293 mappings[devp->num_mappings].flags = map_flags; 294 mappings[devp->num_mappings].memory = NULL; 295 296 if (dev->regions[region].memory == NULL) { 297 err = (*pci_sys->methods->map_range)(dev, 298 &mappings[devp->num_mappings]); 299 } 300 301 if (err == 0) { 302 *addr = mappings[devp->num_mappings].memory; 303 devp->num_mappings++; 304 } else { 305 mappings = realloc(devp->mappings, 306 (sizeof(devp->mappings[0]) * devp->num_mappings)); 307 } 308 309 devp->mappings = mappings; 310 311 return err; 312 } 313 314 315 /** 316 * Unmap the specified BAR so that it can no longer be accessed by the CPU. 317 * 318 * Unmaps the specified BAR that was previously mapped via 319 * \c pci_device_map_region. 320 * 321 * \param dev Device whose memory region is to be mapped. 322 * \param region Region, on the range [0, 5], that is to be mapped. 323 * 324 * \return 325 * Zero on success or an \c errno value on failure. 326 * 327 * \sa pci_device_map_range, pci_device_unmap_range 328 * \deprecated 329 */ 330 int 331 pci_device_unmap_region( struct pci_device * dev, unsigned region ) 332 { 333 int err; 334 335 if (dev == NULL) { 336 return EFAULT; 337 } 338 339 if ((region > 5) || (dev->regions[region].size == 0)) { 340 return ENOENT; 341 } 342 343 err = pci_device_unmap_range(dev, dev->regions[region].memory, 344 dev->regions[region].size); 345 if (!err) { 346 dev->regions[region].memory = NULL; 347 } 348 349 return err; 350 } 351 352 353 /** 354 * Unmap the specified memory range so that it can no longer be accessed by the CPU. 355 * 356 * Unmaps the specified memory range that was previously mapped via 357 * \c pci_device_map_memory_range. 358 * 359 * \param dev Device whose memory is to be unmapped. 360 * \param memory Pointer to the base of the mapped range. 361 * \param size Size, in bytes, of the range to be unmapped. 362 * 363 * \return 364 * Zero on success or an \c errno value on failure. 365 * 366 * \sa pci_device_map_range, pci_device_unmap_range 367 * \deprecated 368 */ 369 int 370 pci_device_unmap_memory_range(struct pci_device *dev, void *memory, 371 pciaddr_t size) 372 { 373 return pci_device_unmap_range(dev, memory, size); 374 } 375 376 377 /** 378 * Unmap the specified memory range so that it can no longer be accessed by the CPU. 379 * 380 * Unmaps the specified memory range that was previously mapped via 381 * \c pci_device_map_memory_range. 382 * 383 * \param dev Device whose memory is to be unmapped. 384 * \param memory Pointer to the base of the mapped range. 385 * \param size Size, in bytes, of the range to be unmapped. 386 * 387 * \return 388 * Zero on success or an \c errno value on failure. 389 * 390 * \sa pci_device_map_range 391 */ 392 int 393 pci_device_unmap_range(struct pci_device *dev, void *memory, 394 pciaddr_t size) 395 { 396 struct pci_device_private *const devp = 397 (struct pci_device_private *) dev; 398 unsigned i; 399 int err; 400 401 402 if (dev == NULL) { 403 return EFAULT; 404 } 405 406 for (i = 0; i < devp->num_mappings; i++) { 407 if ((devp->mappings[i].memory == memory) 408 && (devp->mappings[i].size == size)) { 409 break; 410 } 411 } 412 413 if (i == devp->num_mappings) { 414 return ENOENT; 415 } 416 417 418 err = (*pci_sys->methods->unmap_range)(dev, &devp->mappings[i]); 419 if (!err) { 420 const unsigned entries_to_move = (devp->num_mappings - i) - 1; 421 422 if (entries_to_move > 0) { 423 (void) memmove(&devp->mappings[i], 424 &devp->mappings[i + 1], 425 entries_to_move * sizeof(devp->mappings[0])); 426 } 427 428 devp->num_mappings--; 429 devp->mappings = realloc(devp->mappings, 430 (sizeof(devp->mappings[0]) * devp->num_mappings)); 431 } 432 433 return err; 434 } 435 436 437 /** 438 * Read arbitrary bytes from device's PCI config space 439 * 440 * Reads data from the device's PCI configuration space. As with the system 441 * read command, less data may be returned, without an error, than was 442 * requested. This is particularly the case if a non-root user tries to read 443 * beyond the first 64-bytes of configuration space. 444 * 445 * \param dev Device whose PCI configuration data is to be read. 446 * \param data Location to store the data 447 * \param offset Initial byte offset to read 448 * \param size Total number of bytes to read 449 * \param bytes_read Location to store the actual number of bytes read. This 450 * pointer may be \c NULL. 451 * 452 * \returns 453 * Zero on success or an errno value on failure. 454 * 455 * \note 456 * Data read from PCI configuration space using this routine is \b not 457 * byte-swapped to the host's byte order. PCI configuration data is always 458 * stored in little-endian order, and that is what this routine returns. 459 */ 460 int 461 pci_device_cfg_read( struct pci_device * dev, void * data, 462 pciaddr_t offset, pciaddr_t size, 463 pciaddr_t * bytes_read ) 464 { 465 pciaddr_t scratch; 466 467 if ( (dev == NULL) || (data == NULL) ) { 468 return EFAULT; 469 } 470 471 return pci_sys->methods->read( dev, data, offset, size, 472 (bytes_read == NULL) 473 ? & scratch : bytes_read ); 474 } 475 476 477 int 478 pci_device_cfg_read_u8( struct pci_device * dev, uint8_t * data, 479 pciaddr_t offset ) 480 { 481 pciaddr_t bytes; 482 int err = pci_device_cfg_read( dev, data, offset, 1, & bytes ); 483 484 if ( (err == 0) && (bytes != 1) ) { 485 err = ENXIO; 486 } 487 488 return err; 489 } 490 491 492 int 493 pci_device_cfg_read_u16( struct pci_device * dev, uint16_t * data, 494 pciaddr_t offset ) 495 { 496 pciaddr_t bytes; 497 int err = pci_device_cfg_read( dev, data, offset, 2, & bytes ); 498 499 if ( (err == 0) && (bytes != 2) ) { 500 err = ENXIO; 501 } 502 503 *data = LETOH_16( *data ); 504 return err; 505 } 506 507 508 int 509 pci_device_cfg_read_u32( struct pci_device * dev, uint32_t * data, 510 pciaddr_t offset ) 511 { 512 pciaddr_t bytes; 513 int err = pci_device_cfg_read( dev, data, offset, 4, & bytes ); 514 515 if ( (err == 0) && (bytes != 4) ) { 516 err = ENXIO; 517 } 518 519 *data = LETOH_32( *data ); 520 return err; 521 } 522 523 524 /** 525 * Write arbitrary bytes to device's PCI config space 526 * 527 * Writes data to the device's PCI configuration space. As with the system 528 * write command, less data may be written, without an error, than was 529 * requested. 530 * 531 * \param dev Device whose PCI configuration data is to be written. 532 * \param data Location of the source data 533 * \param offset Initial byte offset to write 534 * \param size Total number of bytes to write 535 * \param bytes_read Location to store the actual number of bytes written. 536 * This pointer may be \c NULL. 537 * 538 * \returns 539 * Zero on success or an errno value on failure. 540 * 541 * \note 542 * Data written to PCI configuration space using this routine is \b not 543 * byte-swapped from the host's byte order. PCI configuration data is always 544 * stored in little-endian order, so data written with this routine should be 545 * put in that order in advance. 546 */ 547 int 548 pci_device_cfg_write( struct pci_device * dev, const void * data, 549 pciaddr_t offset, pciaddr_t size, 550 pciaddr_t * bytes_written ) 551 { 552 pciaddr_t scratch; 553 554 if ( (dev == NULL) || (data == NULL) ) { 555 return EFAULT; 556 } 557 558 return pci_sys->methods->write( dev, data, offset, size, 559 (bytes_written == NULL) 560 ? & scratch : bytes_written ); 561 } 562 563 564 int 565 pci_device_cfg_write_u8(struct pci_device *dev, uint8_t data, 566 pciaddr_t offset) 567 { 568 pciaddr_t bytes; 569 int err = pci_device_cfg_write(dev, & data, offset, 1, & bytes); 570 571 if ( (err == 0) && (bytes != 1) ) { 572 err = ENOSPC; 573 } 574 575 576 return err; 577 } 578 579 580 int 581 pci_device_cfg_write_u16(struct pci_device *dev, uint16_t data, 582 pciaddr_t offset) 583 { 584 pciaddr_t bytes; 585 const uint16_t temp = HTOLE_16(data); 586 int err = pci_device_cfg_write( dev, & temp, offset, 2, & bytes ); 587 588 if ( (err == 0) && (bytes != 2) ) { 589 err = ENOSPC; 590 } 591 592 593 return err; 594 } 595 596 597 int 598 pci_device_cfg_write_u32(struct pci_device *dev, uint32_t data, 599 pciaddr_t offset) 600 { 601 pciaddr_t bytes; 602 const uint32_t temp = HTOLE_32(data); 603 int err = pci_device_cfg_write( dev, & temp, offset, 4, & bytes ); 604 605 if ( (err == 0) && (bytes != 4) ) { 606 err = ENOSPC; 607 } 608 609 610 return err; 611 } 612 613 614 int 615 pci_device_cfg_write_bits( struct pci_device * dev, uint32_t mask, 616 uint32_t data, pciaddr_t offset ) 617 { 618 uint32_t temp; 619 int err; 620 621 err = pci_device_cfg_read_u32( dev, & temp, offset ); 622 if ( ! err ) { 623 temp &= ~mask; 624 temp |= data; 625 626 err = pci_device_cfg_write_u32(dev, temp, offset); 627 } 628 629 return err; 630 } 631 632 void 633 pci_device_enable(struct pci_device *dev) 634 { 635 if (dev == NULL) { 636 return; 637 } 638 639 if (pci_sys->methods->enable) 640 pci_sys->methods->enable(dev); 641 } 642