1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <[email protected]> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include "opt_inet.h" 30 #include "opt_inet6.h" 31 #include "opt_acpi.h" 32 #include "opt_sched.h" 33 34 #include <sys/param.h> 35 #include <sys/types.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/module.h> 42 #include <sys/kobj.h> 43 #include <sys/rman.h> 44 #include <sys/sbuf.h> 45 #include <sys/smp.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 #include <sys/syslog.h> 50 #include <sys/taskqueue.h> 51 #include <sys/limits.h> 52 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_private.h> 56 #include <net/if_types.h> 57 #include <net/if_media.h> 58 #include <net/bpf.h> 59 #include <net/ethernet.h> 60 #include <net/mp_ring.h> 61 #include <net/debugnet.h> 62 #include <net/pfil.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet6/ip6_var.h> 75 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/led/led.h> 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pci_private.h> 86 87 #include <net/iflib.h> 88 89 #include "ifdi_if.h" 90 91 #ifdef PCI_IOV 92 #include <dev/pci/pci_iov.h> 93 #endif 94 95 #include <sys/bitstring.h> 96 /* 97 * enable accounting of every mbuf as it comes in to and goes out of 98 * iflib's software descriptor references 99 */ 100 #define MEMORY_LOGGING 0 101 /* 102 * Enable mbuf vectors for compressing long mbuf chains 103 */ 104 105 /* 106 * NB: 107 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 108 * we prefetch needs to be determined by the time spent in m_free vis a vis 109 * the cost of a prefetch. This will of course vary based on the workload: 110 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 111 * is quite expensive, thus suggesting very little prefetch. 112 * - small packet forwarding which is just returning a single mbuf to 113 * UMA will typically be very fast vis a vis the cost of a memory 114 * access. 115 */ 116 117 /* 118 * File organization: 119 * - private structures 120 * - iflib private utility functions 121 * - ifnet functions 122 * - vlan registry and other exported functions 123 * - iflib public core functions 124 * 125 * 126 */ 127 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 128 129 #define IFLIB_RXEOF_MORE (1U << 0) 130 #define IFLIB_RXEOF_EMPTY (2U << 0) 131 132 struct iflib_txq; 133 typedef struct iflib_txq *iflib_txq_t; 134 struct iflib_rxq; 135 typedef struct iflib_rxq *iflib_rxq_t; 136 struct iflib_fl; 137 typedef struct iflib_fl *iflib_fl_t; 138 139 struct iflib_ctx; 140 141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 142 static void iflib_timer(void *arg); 143 static void iflib_tqg_detach(if_ctx_t ctx); 144 145 typedef struct iflib_filter_info { 146 driver_filter_t *ifi_filter; 147 void *ifi_filter_arg; 148 struct grouptask *ifi_task; 149 void *ifi_ctx; 150 } *iflib_filter_info_t; 151 152 struct iflib_ctx { 153 KOBJ_FIELDS; 154 /* 155 * Pointer to hardware driver's softc 156 */ 157 void *ifc_softc; 158 device_t ifc_dev; 159 if_t ifc_ifp; 160 161 cpuset_t ifc_cpus; 162 if_shared_ctx_t ifc_sctx; 163 struct if_softc_ctx ifc_softc_ctx; 164 165 struct sx ifc_ctx_sx; 166 struct mtx ifc_state_mtx; 167 168 iflib_txq_t ifc_txqs; 169 iflib_rxq_t ifc_rxqs; 170 uint32_t ifc_if_flags; 171 uint32_t ifc_flags; 172 uint32_t ifc_max_fl_buf_size; 173 uint32_t ifc_rx_mbuf_sz; 174 175 int ifc_link_state; 176 int ifc_watchdog_events; 177 struct cdev *ifc_led_dev; 178 struct resource *ifc_msix_mem; 179 180 struct if_irq ifc_legacy_irq; 181 struct grouptask ifc_admin_task; 182 struct grouptask ifc_vflr_task; 183 struct iflib_filter_info ifc_filter_info; 184 struct ifmedia ifc_media; 185 struct ifmedia *ifc_mediap; 186 187 struct sysctl_oid *ifc_sysctl_node; 188 uint16_t ifc_sysctl_ntxqs; 189 uint16_t ifc_sysctl_nrxqs; 190 uint16_t ifc_sysctl_qs_eq_override; 191 uint16_t ifc_sysctl_rx_budget; 192 uint16_t ifc_sysctl_tx_abdicate; 193 uint16_t ifc_sysctl_core_offset; 194 #define CORE_OFFSET_UNSPECIFIED 0xffff 195 uint8_t ifc_sysctl_separate_txrx; 196 uint8_t ifc_sysctl_use_logical_cores; 197 uint16_t ifc_sysctl_extra_msix_vectors; 198 bool ifc_cpus_are_physical_cores; 199 200 qidx_t ifc_sysctl_ntxds[8]; 201 qidx_t ifc_sysctl_nrxds[8]; 202 struct if_txrx ifc_txrx; 203 #define isc_txd_encap ifc_txrx.ift_txd_encap 204 #define isc_txd_flush ifc_txrx.ift_txd_flush 205 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 206 #define isc_rxd_available ifc_txrx.ift_rxd_available 207 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 208 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 209 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 210 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 211 #define isc_txq_select ifc_txrx.ift_txq_select 212 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2 213 214 eventhandler_tag ifc_vlan_attach_event; 215 eventhandler_tag ifc_vlan_detach_event; 216 struct ether_addr ifc_mac; 217 }; 218 219 void * 220 iflib_get_softc(if_ctx_t ctx) 221 { 222 223 return (ctx->ifc_softc); 224 } 225 226 device_t 227 iflib_get_dev(if_ctx_t ctx) 228 { 229 230 return (ctx->ifc_dev); 231 } 232 233 if_t 234 iflib_get_ifp(if_ctx_t ctx) 235 { 236 237 return (ctx->ifc_ifp); 238 } 239 240 struct ifmedia * 241 iflib_get_media(if_ctx_t ctx) 242 { 243 244 return (ctx->ifc_mediap); 245 } 246 247 void 248 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 249 { 250 251 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 252 } 253 254 if_softc_ctx_t 255 iflib_get_softc_ctx(if_ctx_t ctx) 256 { 257 258 return (&ctx->ifc_softc_ctx); 259 } 260 261 if_shared_ctx_t 262 iflib_get_sctx(if_ctx_t ctx) 263 { 264 265 return (ctx->ifc_sctx); 266 } 267 268 uint16_t 269 iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx) 270 { 271 272 return (ctx->ifc_sysctl_extra_msix_vectors); 273 } 274 275 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 276 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 277 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 278 279 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 280 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 281 282 typedef struct iflib_sw_rx_desc_array { 283 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 284 struct mbuf **ifsd_m; /* pkthdr mbufs */ 285 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 286 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 287 } iflib_rxsd_array_t; 288 289 typedef struct iflib_sw_tx_desc_array { 290 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 291 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 292 struct mbuf **ifsd_m; /* pkthdr mbufs */ 293 } if_txsd_vec_t; 294 295 /* magic number that should be high enough for any hardware */ 296 #define IFLIB_MAX_TX_SEGS 128 297 #define IFLIB_RX_COPY_THRESH 128 298 #define IFLIB_MAX_RX_REFRESH 32 299 /* The minimum descriptors per second before we start coalescing */ 300 #define IFLIB_MIN_DESC_SEC 16384 301 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 302 #define IFLIB_QUEUE_IDLE 0 303 #define IFLIB_QUEUE_HUNG 1 304 #define IFLIB_QUEUE_WORKING 2 305 /* maximum number of txqs that can share an rx interrupt */ 306 #define IFLIB_MAX_TX_SHARED_INTR 4 307 308 /* this should really scale with ring size - this is a fairly arbitrary value */ 309 #define TX_BATCH_SIZE 32 310 311 #define IFLIB_RESTART_BUDGET 8 312 313 #define IFC_LEGACY 0x001 314 #define IFC_QFLUSH 0x002 315 #define IFC_MULTISEG 0x004 316 #define IFC_SPARE1 0x008 317 #define IFC_SC_ALLOCATED 0x010 318 #define IFC_INIT_DONE 0x020 319 #define IFC_PREFETCH 0x040 320 #define IFC_DO_RESET 0x080 321 #define IFC_DO_WATCHDOG 0x100 322 #define IFC_SPARE0 0x200 323 #define IFC_SPARE2 0x400 324 #define IFC_IN_DETACH 0x800 325 326 #define IFC_NETMAP_TX_IRQ 0x80000000 327 328 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 329 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 330 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 331 332 struct iflib_txq { 333 qidx_t ift_in_use; 334 qidx_t ift_cidx; 335 qidx_t ift_cidx_processed; 336 qidx_t ift_pidx; 337 uint8_t ift_gen; 338 uint8_t ift_br_offset; 339 uint16_t ift_npending; 340 uint16_t ift_db_pending; 341 uint16_t ift_rs_pending; 342 /* implicit pad */ 343 uint8_t ift_txd_size[8]; 344 uint64_t ift_processed; 345 uint64_t ift_cleaned; 346 uint64_t ift_cleaned_prev; 347 #if MEMORY_LOGGING 348 uint64_t ift_enqueued; 349 uint64_t ift_dequeued; 350 #endif 351 uint64_t ift_no_tx_dma_setup; 352 uint64_t ift_no_desc_avail; 353 uint64_t ift_mbuf_defrag_failed; 354 uint64_t ift_mbuf_defrag; 355 uint64_t ift_map_failed; 356 uint64_t ift_txd_encap_efbig; 357 uint64_t ift_pullups; 358 uint64_t ift_last_timer_tick; 359 360 struct mtx ift_mtx; 361 struct mtx ift_db_mtx; 362 363 /* constant values */ 364 if_ctx_t ift_ctx; 365 struct ifmp_ring *ift_br; 366 struct grouptask ift_task; 367 qidx_t ift_size; 368 uint16_t ift_id; 369 struct callout ift_timer; 370 #ifdef DEV_NETMAP 371 struct callout ift_netmap_timer; 372 #endif /* DEV_NETMAP */ 373 374 if_txsd_vec_t ift_sds; 375 uint8_t ift_qstatus; 376 uint8_t ift_closed; 377 uint8_t ift_update_freq; 378 struct iflib_filter_info ift_filter_info; 379 bus_dma_tag_t ift_buf_tag; 380 bus_dma_tag_t ift_tso_buf_tag; 381 iflib_dma_info_t ift_ifdi; 382 #define MTX_NAME_LEN 32 383 char ift_mtx_name[MTX_NAME_LEN]; 384 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 385 #ifdef IFLIB_DIAGNOSTICS 386 uint64_t ift_cpu_exec_count[256]; 387 #endif 388 } __aligned(CACHE_LINE_SIZE); 389 390 struct iflib_fl { 391 qidx_t ifl_cidx; 392 qidx_t ifl_pidx; 393 qidx_t ifl_credits; 394 uint8_t ifl_gen; 395 uint8_t ifl_rxd_size; 396 #if MEMORY_LOGGING 397 uint64_t ifl_m_enqueued; 398 uint64_t ifl_m_dequeued; 399 uint64_t ifl_cl_enqueued; 400 uint64_t ifl_cl_dequeued; 401 #endif 402 /* implicit pad */ 403 bitstr_t *ifl_rx_bitmap; 404 qidx_t ifl_fragidx; 405 /* constant */ 406 qidx_t ifl_size; 407 uint16_t ifl_buf_size; 408 uint16_t ifl_cltype; 409 uma_zone_t ifl_zone; 410 iflib_rxsd_array_t ifl_sds; 411 iflib_rxq_t ifl_rxq; 412 uint8_t ifl_id; 413 bus_dma_tag_t ifl_buf_tag; 414 iflib_dma_info_t ifl_ifdi; 415 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 416 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 417 } __aligned(CACHE_LINE_SIZE); 418 419 static inline qidx_t 420 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 421 { 422 qidx_t used; 423 424 if (pidx > cidx) 425 used = pidx - cidx; 426 else if (pidx < cidx) 427 used = size - cidx + pidx; 428 else if (gen == 0 && pidx == cidx) 429 used = 0; 430 else if (gen == 1 && pidx == cidx) 431 used = size; 432 else 433 panic("bad state"); 434 435 return (used); 436 } 437 438 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 439 440 #define IDXDIFF(head, tail, wrap) \ 441 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 442 443 struct iflib_rxq { 444 if_ctx_t ifr_ctx; 445 iflib_fl_t ifr_fl; 446 uint64_t ifr_rx_irq; 447 struct pfil_head *pfil; 448 /* 449 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 450 * the completion queue consumer index. Otherwise it's unused. 451 */ 452 qidx_t ifr_cq_cidx; 453 uint16_t ifr_id; 454 uint8_t ifr_nfl; 455 uint8_t ifr_ntxqirq; 456 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 457 uint8_t ifr_fl_offset; 458 struct lro_ctrl ifr_lc; 459 struct grouptask ifr_task; 460 struct callout ifr_watchdog; 461 struct iflib_filter_info ifr_filter_info; 462 iflib_dma_info_t ifr_ifdi; 463 464 /* dynamically allocate if any drivers need a value substantially larger than this */ 465 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 466 #ifdef IFLIB_DIAGNOSTICS 467 uint64_t ifr_cpu_exec_count[256]; 468 #endif 469 } __aligned(CACHE_LINE_SIZE); 470 471 typedef struct if_rxsd { 472 caddr_t *ifsd_cl; 473 iflib_fl_t ifsd_fl; 474 } *if_rxsd_t; 475 476 /* multiple of word size */ 477 #ifdef __LP64__ 478 #define PKT_INFO_SIZE 6 479 #define RXD_INFO_SIZE 5 480 #define PKT_TYPE uint64_t 481 #else 482 #define PKT_INFO_SIZE 11 483 #define RXD_INFO_SIZE 8 484 #define PKT_TYPE uint32_t 485 #endif 486 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 487 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 488 489 typedef struct if_pkt_info_pad { 490 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 491 } *if_pkt_info_pad_t; 492 typedef struct if_rxd_info_pad { 493 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 494 } *if_rxd_info_pad_t; 495 496 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 497 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 498 499 static inline void 500 pkt_info_zero(if_pkt_info_t pi) 501 { 502 if_pkt_info_pad_t pi_pad; 503 504 pi_pad = (if_pkt_info_pad_t)pi; 505 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 506 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 507 #ifndef __LP64__ 508 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 509 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 510 #endif 511 } 512 513 static inline void 514 rxd_info_zero(if_rxd_info_t ri) 515 { 516 if_rxd_info_pad_t ri_pad; 517 int i; 518 519 ri_pad = (if_rxd_info_pad_t)ri; 520 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 521 ri_pad->rxd_val[i] = 0; 522 ri_pad->rxd_val[i+1] = 0; 523 ri_pad->rxd_val[i+2] = 0; 524 ri_pad->rxd_val[i+3] = 0; 525 } 526 #ifdef __LP64__ 527 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 528 #endif 529 } 530 531 /* 532 * Only allow a single packet to take up most 1/nth of the tx ring 533 */ 534 #define MAX_SINGLE_PACKET_FRACTION 12 535 #define IF_BAD_DMA (bus_addr_t)-1 536 537 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 538 539 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 540 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 541 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 542 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 543 544 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 545 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 546 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 547 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 548 549 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 550 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 551 552 /* Our boot-time initialization hook */ 553 static int iflib_module_event_handler(module_t, int, void *); 554 555 static moduledata_t iflib_moduledata = { 556 "iflib", 557 iflib_module_event_handler, 558 NULL 559 }; 560 561 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 562 MODULE_VERSION(iflib, 1); 563 564 MODULE_DEPEND(iflib, pci, 1, 1, 1); 565 MODULE_DEPEND(iflib, ether, 1, 1, 1); 566 567 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 568 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 569 570 #ifndef IFLIB_DEBUG_COUNTERS 571 #ifdef INVARIANTS 572 #define IFLIB_DEBUG_COUNTERS 1 573 #else 574 #define IFLIB_DEBUG_COUNTERS 0 575 #endif /* !INVARIANTS */ 576 #endif 577 578 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 579 "iflib driver parameters"); 580 581 /* 582 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 583 */ 584 static int iflib_min_tx_latency = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 586 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 587 static int iflib_no_tx_batch = 0; 588 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 589 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 590 static int iflib_timer_default = 1000; 591 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 592 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 593 594 595 #if IFLIB_DEBUG_COUNTERS 596 597 static int iflib_tx_seen; 598 static int iflib_tx_sent; 599 static int iflib_tx_encap; 600 static int iflib_rx_allocs; 601 static int iflib_fl_refills; 602 static int iflib_fl_refills_large; 603 static int iflib_tx_frees; 604 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 606 &iflib_tx_seen, 0, "# TX mbufs seen"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 608 &iflib_tx_sent, 0, "# TX mbufs sent"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 610 &iflib_tx_encap, 0, "# TX mbufs encapped"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 612 &iflib_tx_frees, 0, "# TX frees"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 614 &iflib_rx_allocs, 0, "# RX allocations"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 616 &iflib_fl_refills, 0, "# refills"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 618 &iflib_fl_refills_large, 0, "# large refills"); 619 620 static int iflib_txq_drain_flushing; 621 static int iflib_txq_drain_oactive; 622 static int iflib_txq_drain_notready; 623 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 625 &iflib_txq_drain_flushing, 0, "# drain flushes"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 627 &iflib_txq_drain_oactive, 0, "# drain oactives"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 629 &iflib_txq_drain_notready, 0, "# drain notready"); 630 631 static int iflib_encap_load_mbuf_fail; 632 static int iflib_encap_pad_mbuf_fail; 633 static int iflib_encap_txq_avail_fail; 634 static int iflib_encap_txd_encap_fail; 635 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 637 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 639 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 641 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 643 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 644 645 static int iflib_task_fn_rxs; 646 static int iflib_rx_intr_enables; 647 static int iflib_fast_intrs; 648 static int iflib_rx_unavail; 649 static int iflib_rx_ctx_inactive; 650 static int iflib_rx_if_input; 651 static int iflib_rxd_flush; 652 653 static int iflib_verbose_debug; 654 655 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 656 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 658 &iflib_rx_intr_enables, 0, "# RX intr enables"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 660 &iflib_fast_intrs, 0, "# fast_intr calls"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 662 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 664 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 666 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 668 &iflib_rxd_flush, 0, "# times rxd_flush called"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 670 &iflib_verbose_debug, 0, "enable verbose debugging"); 671 672 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 673 static void 674 iflib_debug_reset(void) 675 { 676 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 677 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 678 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 679 iflib_txq_drain_notready = 680 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 681 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 682 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 683 iflib_rx_unavail = 684 iflib_rx_ctx_inactive = iflib_rx_if_input = 685 iflib_rxd_flush = 0; 686 } 687 688 #else 689 #define DBG_COUNTER_INC(name) 690 static void iflib_debug_reset(void) {} 691 #endif 692 693 #define IFLIB_DEBUG 0 694 695 static void iflib_tx_structures_free(if_ctx_t ctx); 696 static void iflib_rx_structures_free(if_ctx_t ctx); 697 static int iflib_queues_alloc(if_ctx_t ctx); 698 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 699 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 700 static int iflib_qset_structures_setup(if_ctx_t ctx); 701 static int iflib_msix_init(if_ctx_t ctx); 702 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 703 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 704 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 705 #ifdef ALTQ 706 static void iflib_altq_if_start(if_t ifp); 707 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 708 #endif 709 static int iflib_register(if_ctx_t); 710 static void iflib_deregister(if_ctx_t); 711 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 712 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 713 static void iflib_init_locked(if_ctx_t ctx); 714 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 715 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 716 static void iflib_ifmp_purge(iflib_txq_t txq); 717 static void _iflib_pre_assert(if_softc_ctx_t scctx); 718 static void iflib_stop(if_ctx_t ctx); 719 static void iflib_if_init_locked(if_ctx_t ctx); 720 static void iflib_free_intr_mem(if_ctx_t ctx); 721 #ifndef __NO_STRICT_ALIGNMENT 722 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 723 #endif 724 725 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 726 SLIST_HEAD_INITIALIZER(cpu_offsets); 727 struct cpu_offset { 728 SLIST_ENTRY(cpu_offset) entries; 729 cpuset_t set; 730 unsigned int refcount; 731 uint16_t next_cpuid; 732 }; 733 static struct mtx cpu_offset_mtx; 734 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 735 MTX_DEF); 736 737 DEBUGNET_DEFINE(iflib); 738 739 static int 740 iflib_num_rx_descs(if_ctx_t ctx) 741 { 742 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 743 if_shared_ctx_t sctx = ctx->ifc_sctx; 744 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 745 746 return scctx->isc_nrxd[first_rxq]; 747 } 748 749 static int 750 iflib_num_tx_descs(if_ctx_t ctx) 751 { 752 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 753 if_shared_ctx_t sctx = ctx->ifc_sctx; 754 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 755 756 return scctx->isc_ntxd[first_txq]; 757 } 758 759 #ifdef DEV_NETMAP 760 #include <sys/selinfo.h> 761 #include <net/netmap.h> 762 #include <dev/netmap/netmap_kern.h> 763 764 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 765 766 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 767 static void iflib_netmap_timer(void *arg); 768 769 /* 770 * device-specific sysctl variables: 771 * 772 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 773 * During regular operations the CRC is stripped, but on some 774 * hardware reception of frames not multiple of 64 is slower, 775 * so using crcstrip=0 helps in benchmarks. 776 * 777 * iflib_rx_miss, iflib_rx_miss_bufs: 778 * count packets that might be missed due to lost interrupts. 779 */ 780 SYSCTL_DECL(_dev_netmap); 781 /* 782 * The xl driver by default strips CRCs and we do not override it. 783 */ 784 785 int iflib_crcstrip = 1; 786 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 787 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 788 789 int iflib_rx_miss, iflib_rx_miss_bufs; 790 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 791 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 792 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 793 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 794 795 /* 796 * Register/unregister. We are already under netmap lock. 797 * Only called on the first register or the last unregister. 798 */ 799 static int 800 iflib_netmap_register(struct netmap_adapter *na, int onoff) 801 { 802 if_t ifp = na->ifp; 803 if_ctx_t ctx = if_getsoftc(ifp); 804 int status; 805 806 CTX_LOCK(ctx); 807 if (!CTX_IS_VF(ctx)) 808 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 809 810 iflib_stop(ctx); 811 812 /* 813 * Enable (or disable) netmap flags, and intercept (or restore) 814 * ifp->if_transmit. This is done once the device has been stopped 815 * to prevent race conditions. Also, this must be done after 816 * calling netmap_disable_all_rings() and before calling 817 * netmap_enable_all_rings(), so that these two functions see the 818 * updated state of the NAF_NETMAP_ON bit. 819 */ 820 if (onoff) { 821 nm_set_native_flags(na); 822 } else { 823 nm_clear_native_flags(na); 824 } 825 826 iflib_init_locked(ctx); 827 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 828 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1; 829 if (status) 830 nm_clear_native_flags(na); 831 CTX_UNLOCK(ctx); 832 return (status); 833 } 834 835 static int 836 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 837 { 838 if_t ifp = na->ifp; 839 if_ctx_t ctx = if_getsoftc(ifp); 840 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 841 iflib_fl_t fl = &rxq->ifr_fl[0]; 842 843 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 844 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 845 info->num_tx_descs = iflib_num_tx_descs(ctx); 846 info->num_rx_descs = iflib_num_rx_descs(ctx); 847 info->rx_buf_maxsize = fl->ifl_buf_size; 848 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 849 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 850 info->num_rx_descs, info->rx_buf_maxsize); 851 852 return 0; 853 } 854 855 static int 856 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 857 { 858 struct netmap_adapter *na = kring->na; 859 u_int const lim = kring->nkr_num_slots - 1; 860 struct netmap_ring *ring = kring->ring; 861 bus_dmamap_t *map; 862 struct if_rxd_update iru; 863 if_ctx_t ctx = rxq->ifr_ctx; 864 iflib_fl_t fl = &rxq->ifr_fl[0]; 865 u_int nic_i_first, nic_i; 866 u_int nm_i; 867 int i, n; 868 #if IFLIB_DEBUG_COUNTERS 869 int rf_count = 0; 870 #endif 871 872 /* 873 * This function is used both at initialization and in rxsync. 874 * At initialization we need to prepare (with isc_rxd_refill()) 875 * all the netmap buffers currently owned by the kernel, in 876 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 877 * (except for kring->nkr_hwofs). These may be less than 878 * kring->nkr_num_slots if netmap_reset() was called while 879 * an application using the kring that still owned some 880 * buffers. 881 * At rxsync time, both indexes point to the next buffer to be 882 * refilled. 883 * In any case we publish (with isc_rxd_flush()) up to 884 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 885 * pointer to overrun the head/cons pointer, although this is 886 * not necessary for some NICs (e.g. vmx). 887 */ 888 if (__predict_false(init)) { 889 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 890 } else { 891 n = kring->rhead - kring->nr_hwcur; 892 if (n == 0) 893 return (0); /* Nothing to do. */ 894 if (n < 0) 895 n += kring->nkr_num_slots; 896 } 897 898 iru_init(&iru, rxq, 0 /* flid */); 899 map = fl->ifl_sds.ifsd_map; 900 nic_i = fl->ifl_pidx; 901 nm_i = netmap_idx_n2k(kring, nic_i); 902 if (__predict_false(init)) { 903 /* 904 * On init/reset, nic_i must be 0, and we must 905 * start to refill from hwtail (see netmap_reset()). 906 */ 907 MPASS(nic_i == 0); 908 MPASS(nm_i == kring->nr_hwtail); 909 } else 910 MPASS(nm_i == kring->nr_hwcur); 911 DBG_COUNTER_INC(fl_refills); 912 while (n > 0) { 913 #if IFLIB_DEBUG_COUNTERS 914 if (++rf_count == 9) 915 DBG_COUNTER_INC(fl_refills_large); 916 #endif 917 nic_i_first = nic_i; 918 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 919 struct netmap_slot *slot = &ring->slot[nm_i]; 920 uint64_t paddr; 921 void *addr = PNMB(na, slot, &paddr); 922 923 MPASS(i < IFLIB_MAX_RX_REFRESH); 924 925 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 926 return netmap_ring_reinit(kring); 927 928 fl->ifl_bus_addrs[i] = paddr + 929 nm_get_offset(kring, slot); 930 fl->ifl_rxd_idxs[i] = nic_i; 931 932 if (__predict_false(init)) { 933 netmap_load_map(na, fl->ifl_buf_tag, 934 map[nic_i], addr); 935 } else if (slot->flags & NS_BUF_CHANGED) { 936 /* buffer has changed, reload map */ 937 netmap_reload_map(na, fl->ifl_buf_tag, 938 map[nic_i], addr); 939 } 940 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 941 BUS_DMASYNC_PREREAD); 942 slot->flags &= ~NS_BUF_CHANGED; 943 944 nm_i = nm_next(nm_i, lim); 945 nic_i = nm_next(nic_i, lim); 946 } 947 948 iru.iru_pidx = nic_i_first; 949 iru.iru_count = i; 950 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 951 } 952 fl->ifl_pidx = nic_i; 953 /* 954 * At the end of the loop we must have refilled everything 955 * we could possibly refill. 956 */ 957 MPASS(nm_i == kring->rhead); 958 kring->nr_hwcur = nm_i; 959 960 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 961 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 962 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 963 nm_prev(nic_i, lim)); 964 DBG_COUNTER_INC(rxd_flush); 965 966 return (0); 967 } 968 969 #define NETMAP_TX_TIMER_US 90 970 971 /* 972 * Reconcile kernel and user view of the transmit ring. 973 * 974 * All information is in the kring. 975 * Userspace wants to send packets up to the one before kring->rhead, 976 * kernel knows kring->nr_hwcur is the first unsent packet. 977 * 978 * Here we push packets out (as many as possible), and possibly 979 * reclaim buffers from previously completed transmission. 980 * 981 * The caller (netmap) guarantees that there is only one instance 982 * running at any time. Any interference with other driver 983 * methods should be handled by the individual drivers. 984 */ 985 static int 986 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 987 { 988 struct netmap_adapter *na = kring->na; 989 if_t ifp = na->ifp; 990 struct netmap_ring *ring = kring->ring; 991 u_int nm_i; /* index into the netmap kring */ 992 u_int nic_i; /* index into the NIC ring */ 993 u_int const lim = kring->nkr_num_slots - 1; 994 u_int const head = kring->rhead; 995 struct if_pkt_info pi; 996 int tx_pkts = 0, tx_bytes = 0; 997 998 /* 999 * interrupts on every tx packet are expensive so request 1000 * them every half ring, or where NS_REPORT is set 1001 */ 1002 u_int report_frequency = kring->nkr_num_slots >> 1; 1003 /* device-specific */ 1004 if_ctx_t ctx = if_getsoftc(ifp); 1005 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1006 1007 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1008 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1009 1010 /* 1011 * First part: process new packets to send. 1012 * nm_i is the current index in the netmap kring, 1013 * nic_i is the corresponding index in the NIC ring. 1014 * 1015 * If we have packets to send (nm_i != head) 1016 * iterate over the netmap ring, fetch length and update 1017 * the corresponding slot in the NIC ring. Some drivers also 1018 * need to update the buffer's physical address in the NIC slot 1019 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1020 * 1021 * The netmap_reload_map() calls is especially expensive, 1022 * even when (as in this case) the tag is 0, so do only 1023 * when the buffer has actually changed. 1024 * 1025 * If possible do not set the report/intr bit on all slots, 1026 * but only a few times per ring or when NS_REPORT is set. 1027 * 1028 * Finally, on 10G and faster drivers, it might be useful 1029 * to prefetch the next slot and txr entry. 1030 */ 1031 1032 nm_i = kring->nr_hwcur; 1033 if (nm_i != head) { /* we have new packets to send */ 1034 uint32_t pkt_len = 0, seg_idx = 0; 1035 int nic_i_start = -1, flags = 0; 1036 pkt_info_zero(&pi); 1037 pi.ipi_segs = txq->ift_segs; 1038 pi.ipi_qsidx = kring->ring_id; 1039 nic_i = netmap_idx_k2n(kring, nm_i); 1040 1041 __builtin_prefetch(&ring->slot[nm_i]); 1042 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1043 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1044 1045 while (nm_i != head) { 1046 struct netmap_slot *slot = &ring->slot[nm_i]; 1047 uint64_t offset = nm_get_offset(kring, slot); 1048 u_int len = slot->len; 1049 uint64_t paddr; 1050 void *addr = PNMB(na, slot, &paddr); 1051 1052 flags |= (slot->flags & NS_REPORT || 1053 nic_i == 0 || nic_i == report_frequency) ? 1054 IPI_TX_INTR : 0; 1055 1056 /* 1057 * If this is the first packet fragment, save the 1058 * index of the first NIC slot for later. 1059 */ 1060 if (nic_i_start < 0) 1061 nic_i_start = nic_i; 1062 1063 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1064 pi.ipi_segs[seg_idx].ds_len = len; 1065 if (len) { 1066 pkt_len += len; 1067 seg_idx++; 1068 } 1069 1070 if (!(slot->flags & NS_MOREFRAG)) { 1071 pi.ipi_len = pkt_len; 1072 pi.ipi_nsegs = seg_idx; 1073 pi.ipi_pidx = nic_i_start; 1074 pi.ipi_ndescs = 0; 1075 pi.ipi_flags = flags; 1076 1077 /* Prepare the NIC TX ring. */ 1078 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1079 DBG_COUNTER_INC(tx_encap); 1080 1081 /* Update transmit counters */ 1082 tx_bytes += pi.ipi_len; 1083 tx_pkts++; 1084 1085 /* Reinit per-packet info for the next one. */ 1086 flags = seg_idx = pkt_len = 0; 1087 nic_i_start = -1; 1088 } 1089 1090 /* prefetch for next round */ 1091 __builtin_prefetch(&ring->slot[nm_i + 1]); 1092 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1093 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1094 1095 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1096 1097 if (slot->flags & NS_BUF_CHANGED) { 1098 /* buffer has changed, reload map */ 1099 netmap_reload_map(na, txq->ift_buf_tag, 1100 txq->ift_sds.ifsd_map[nic_i], addr); 1101 } 1102 /* make sure changes to the buffer are synced */ 1103 bus_dmamap_sync(txq->ift_buf_tag, 1104 txq->ift_sds.ifsd_map[nic_i], 1105 BUS_DMASYNC_PREWRITE); 1106 1107 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1108 nm_i = nm_next(nm_i, lim); 1109 nic_i = nm_next(nic_i, lim); 1110 } 1111 kring->nr_hwcur = nm_i; 1112 1113 /* synchronize the NIC ring */ 1114 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1115 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1116 1117 /* (re)start the tx unit up to slot nic_i (excluded) */ 1118 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1119 } 1120 1121 /* 1122 * Second part: reclaim buffers for completed transmissions. 1123 * 1124 * If there are unclaimed buffers, attempt to reclaim them. 1125 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1126 * trigger a per-tx-queue timer to try again later. 1127 */ 1128 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1129 if (iflib_tx_credits_update(ctx, txq)) { 1130 /* some tx completed, increment avail */ 1131 nic_i = txq->ift_cidx_processed; 1132 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1133 } 1134 } 1135 1136 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1137 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1138 callout_reset_sbt_on(&txq->ift_netmap_timer, 1139 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1140 iflib_netmap_timer, txq, 1141 txq->ift_netmap_timer.c_cpu, 0); 1142 } 1143 1144 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1145 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1146 1147 return (0); 1148 } 1149 1150 /* 1151 * Reconcile kernel and user view of the receive ring. 1152 * Same as for the txsync, this routine must be efficient. 1153 * The caller guarantees a single invocations, but races against 1154 * the rest of the driver should be handled here. 1155 * 1156 * On call, kring->rhead is the first packet that userspace wants 1157 * to keep, and kring->rcur is the wakeup point. 1158 * The kernel has previously reported packets up to kring->rtail. 1159 * 1160 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1161 * of whether or not we received an interrupt. 1162 */ 1163 static int 1164 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1165 { 1166 struct netmap_adapter *na = kring->na; 1167 struct netmap_ring *ring = kring->ring; 1168 if_t ifp = na->ifp; 1169 uint32_t nm_i; /* index into the netmap ring */ 1170 uint32_t nic_i; /* index into the NIC ring */ 1171 u_int n; 1172 u_int const lim = kring->nkr_num_slots - 1; 1173 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1174 int i = 0, rx_bytes = 0, rx_pkts = 0; 1175 1176 if_ctx_t ctx = if_getsoftc(ifp); 1177 if_shared_ctx_t sctx = ctx->ifc_sctx; 1178 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1179 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1180 iflib_fl_t fl = &rxq->ifr_fl[0]; 1181 struct if_rxd_info ri; 1182 qidx_t *cidxp; 1183 1184 /* 1185 * netmap only uses free list 0, to avoid out of order consumption 1186 * of receive buffers 1187 */ 1188 1189 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1190 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1191 1192 /* 1193 * First part: import newly received packets. 1194 * 1195 * nm_i is the index of the next free slot in the netmap ring, 1196 * nic_i is the index of the next received packet in the NIC ring 1197 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1198 * differ in case if_init() has been called while 1199 * in netmap mode. For the receive ring we have 1200 * 1201 * nic_i = fl->ifl_cidx; 1202 * nm_i = kring->nr_hwtail (previous) 1203 * and 1204 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1205 * 1206 * fl->ifl_cidx is set to 0 on a ring reinit 1207 */ 1208 if (netmap_no_pendintr || force_update) { 1209 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1210 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1211 int crclen = iflib_crcstrip ? 0 : 4; 1212 int error, avail; 1213 1214 /* 1215 * For the free list consumer index, we use the same 1216 * logic as in iflib_rxeof(). 1217 */ 1218 if (have_rxcq) 1219 cidxp = &rxq->ifr_cq_cidx; 1220 else 1221 cidxp = &fl->ifl_cidx; 1222 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1223 rxq->ifr_id, *cidxp, USHRT_MAX); 1224 1225 nic_i = fl->ifl_cidx; 1226 nm_i = netmap_idx_n2k(kring, nic_i); 1227 MPASS(nm_i == kring->nr_hwtail); 1228 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1229 rxd_info_zero(&ri); 1230 ri.iri_frags = rxq->ifr_frags; 1231 ri.iri_qsidx = kring->ring_id; 1232 ri.iri_ifp = ctx->ifc_ifp; 1233 ri.iri_cidx = *cidxp; 1234 1235 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1236 for (i = 0; i < ri.iri_nfrags; i++) { 1237 if (error) { 1238 ring->slot[nm_i].len = 0; 1239 ring->slot[nm_i].flags = 0; 1240 } else { 1241 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1242 if (i == (ri.iri_nfrags - 1)) { 1243 ring->slot[nm_i].len -= crclen; 1244 ring->slot[nm_i].flags = 0; 1245 1246 /* Update receive counters */ 1247 rx_bytes += ri.iri_len; 1248 rx_pkts++; 1249 } else 1250 ring->slot[nm_i].flags = NS_MOREFRAG; 1251 } 1252 1253 bus_dmamap_sync(fl->ifl_buf_tag, 1254 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1255 nm_i = nm_next(nm_i, lim); 1256 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1257 } 1258 1259 if (have_rxcq) { 1260 *cidxp = ri.iri_cidx; 1261 while (*cidxp >= scctx->isc_nrxd[0]) 1262 *cidxp -= scctx->isc_nrxd[0]; 1263 } 1264 1265 } 1266 if (n) { /* update the state variables */ 1267 if (netmap_no_pendintr && !force_update) { 1268 /* diagnostics */ 1269 iflib_rx_miss ++; 1270 iflib_rx_miss_bufs += n; 1271 } 1272 kring->nr_hwtail = nm_i; 1273 } 1274 kring->nr_kflags &= ~NKR_PENDINTR; 1275 } 1276 /* 1277 * Second part: skip past packets that userspace has released. 1278 * (kring->nr_hwcur to head excluded), 1279 * and make the buffers available for reception. 1280 * As usual nm_i is the index in the netmap ring, 1281 * nic_i is the index in the NIC ring, and 1282 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1283 */ 1284 netmap_fl_refill(rxq, kring, false); 1285 1286 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1287 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1288 1289 return (0); 1290 } 1291 1292 static void 1293 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1294 { 1295 if_ctx_t ctx = if_getsoftc(na->ifp); 1296 1297 CTX_LOCK(ctx); 1298 if (onoff) { 1299 IFDI_INTR_ENABLE(ctx); 1300 } else { 1301 IFDI_INTR_DISABLE(ctx); 1302 } 1303 CTX_UNLOCK(ctx); 1304 } 1305 1306 static int 1307 iflib_netmap_attach(if_ctx_t ctx) 1308 { 1309 struct netmap_adapter na; 1310 1311 bzero(&na, sizeof(na)); 1312 1313 na.ifp = ctx->ifc_ifp; 1314 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1315 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1316 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1317 1318 na.num_tx_desc = iflib_num_tx_descs(ctx); 1319 na.num_rx_desc = iflib_num_rx_descs(ctx); 1320 na.nm_txsync = iflib_netmap_txsync; 1321 na.nm_rxsync = iflib_netmap_rxsync; 1322 na.nm_register = iflib_netmap_register; 1323 na.nm_intr = iflib_netmap_intr; 1324 na.nm_config = iflib_netmap_config; 1325 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1326 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1327 return (netmap_attach(&na)); 1328 } 1329 1330 static int 1331 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1332 { 1333 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1334 struct netmap_slot *slot; 1335 1336 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1337 if (slot == NULL) 1338 return (0); 1339 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1340 /* 1341 * In netmap mode, set the map for the packet buffer. 1342 * NOTE: Some drivers (not this one) also need to set 1343 * the physical buffer address in the NIC ring. 1344 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1345 * netmap slot index, si 1346 */ 1347 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1348 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1349 NMB(na, slot + si)); 1350 } 1351 return (1); 1352 } 1353 1354 static int 1355 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1356 { 1357 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1358 struct netmap_kring *kring; 1359 struct netmap_slot *slot; 1360 1361 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1362 if (slot == NULL) 1363 return (0); 1364 kring = na->rx_rings[rxq->ifr_id]; 1365 netmap_fl_refill(rxq, kring, true); 1366 return (1); 1367 } 1368 1369 static void 1370 iflib_netmap_timer(void *arg) 1371 { 1372 iflib_txq_t txq = arg; 1373 if_ctx_t ctx = txq->ift_ctx; 1374 1375 /* 1376 * Wake up the netmap application, to give it a chance to 1377 * call txsync and reclaim more completed TX buffers. 1378 */ 1379 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1380 } 1381 1382 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1383 1384 #else 1385 #define iflib_netmap_txq_init(ctx, txq) (0) 1386 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1387 #define iflib_netmap_detach(ifp) 1388 #define netmap_enable_all_rings(ifp) 1389 #define netmap_disable_all_rings(ifp) 1390 1391 #define iflib_netmap_attach(ctx) (0) 1392 #define netmap_rx_irq(ifp, qid, budget) (0) 1393 #endif 1394 1395 #if defined(__i386__) || defined(__amd64__) 1396 static __inline void 1397 prefetch(void *x) 1398 { 1399 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1400 } 1401 1402 static __inline void 1403 prefetch2cachelines(void *x) 1404 { 1405 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1406 #if (CACHE_LINE_SIZE < 128) 1407 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1408 #endif 1409 } 1410 #else 1411 static __inline void 1412 prefetch(void *x) 1413 { 1414 } 1415 1416 static __inline void 1417 prefetch2cachelines(void *x) 1418 { 1419 } 1420 #endif 1421 1422 static void 1423 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1424 { 1425 iflib_fl_t fl; 1426 1427 fl = &rxq->ifr_fl[flid]; 1428 iru->iru_paddrs = fl->ifl_bus_addrs; 1429 iru->iru_idxs = fl->ifl_rxd_idxs; 1430 iru->iru_qsidx = rxq->ifr_id; 1431 iru->iru_buf_size = fl->ifl_buf_size; 1432 iru->iru_flidx = fl->ifl_id; 1433 } 1434 1435 static void 1436 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1437 { 1438 if (err) 1439 return; 1440 *(bus_addr_t *) arg = segs[0].ds_addr; 1441 } 1442 1443 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1444 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1445 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1446 1447 int 1448 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1449 { 1450 int err; 1451 device_t dev = ctx->ifc_dev; 1452 bus_addr_t lowaddr; 1453 1454 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1455 1456 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1457 align, 0, /* alignment, bounds */ 1458 lowaddr, /* lowaddr */ 1459 BUS_SPACE_MAXADDR, /* highaddr */ 1460 NULL, NULL, /* filter, filterarg */ 1461 size, /* maxsize */ 1462 1, /* nsegments */ 1463 size, /* maxsegsize */ 1464 BUS_DMA_ALLOCNOW, /* flags */ 1465 NULL, /* lockfunc */ 1466 NULL, /* lockarg */ 1467 &dma->idi_tag); 1468 if (err) { 1469 device_printf(dev, 1470 "%s: bus_dma_tag_create failed: %d (size=%d, align=%d)\n", 1471 __func__, err, size, align); 1472 goto fail_0; 1473 } 1474 1475 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1476 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1477 if (err) { 1478 device_printf(dev, 1479 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1480 __func__, (uintmax_t)size, err); 1481 goto fail_1; 1482 } 1483 1484 dma->idi_paddr = IF_BAD_DMA; 1485 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1486 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1487 if (err || dma->idi_paddr == IF_BAD_DMA) { 1488 device_printf(dev, 1489 "%s: bus_dmamap_load failed: %d\n", 1490 __func__, err); 1491 goto fail_2; 1492 } 1493 1494 dma->idi_size = size; 1495 return (0); 1496 1497 fail_2: 1498 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1499 fail_1: 1500 bus_dma_tag_destroy(dma->idi_tag); 1501 fail_0: 1502 dma->idi_tag = NULL; 1503 1504 return (err); 1505 } 1506 1507 int 1508 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1509 { 1510 if_shared_ctx_t sctx = ctx->ifc_sctx; 1511 1512 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1513 1514 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1515 } 1516 1517 int 1518 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1519 { 1520 int i, err; 1521 iflib_dma_info_t *dmaiter; 1522 1523 dmaiter = dmalist; 1524 for (i = 0; i < count; i++, dmaiter++) { 1525 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1526 break; 1527 } 1528 if (err) 1529 iflib_dma_free_multi(dmalist, i); 1530 return (err); 1531 } 1532 1533 void 1534 iflib_dma_free(iflib_dma_info_t dma) 1535 { 1536 if (dma->idi_tag == NULL) 1537 return; 1538 if (dma->idi_paddr != IF_BAD_DMA) { 1539 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1540 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1541 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1542 dma->idi_paddr = IF_BAD_DMA; 1543 } 1544 if (dma->idi_vaddr != NULL) { 1545 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1546 dma->idi_vaddr = NULL; 1547 } 1548 bus_dma_tag_destroy(dma->idi_tag); 1549 dma->idi_tag = NULL; 1550 } 1551 1552 void 1553 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1554 { 1555 int i; 1556 iflib_dma_info_t *dmaiter = dmalist; 1557 1558 for (i = 0; i < count; i++, dmaiter++) 1559 iflib_dma_free(*dmaiter); 1560 } 1561 1562 static int 1563 iflib_fast_intr(void *arg) 1564 { 1565 iflib_filter_info_t info = arg; 1566 struct grouptask *gtask = info->ifi_task; 1567 int result; 1568 1569 DBG_COUNTER_INC(fast_intrs); 1570 if (info->ifi_filter != NULL) { 1571 result = info->ifi_filter(info->ifi_filter_arg); 1572 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1573 return (result); 1574 } 1575 1576 GROUPTASK_ENQUEUE(gtask); 1577 return (FILTER_HANDLED); 1578 } 1579 1580 static int 1581 iflib_fast_intr_rxtx(void *arg) 1582 { 1583 iflib_filter_info_t info = arg; 1584 struct grouptask *gtask = info->ifi_task; 1585 if_ctx_t ctx; 1586 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1587 iflib_txq_t txq; 1588 void *sc; 1589 int i, cidx, result; 1590 qidx_t txqid; 1591 bool intr_enable, intr_legacy; 1592 1593 DBG_COUNTER_INC(fast_intrs); 1594 if (info->ifi_filter != NULL) { 1595 result = info->ifi_filter(info->ifi_filter_arg); 1596 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1597 return (result); 1598 } 1599 1600 ctx = rxq->ifr_ctx; 1601 sc = ctx->ifc_softc; 1602 intr_enable = false; 1603 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1604 MPASS(rxq->ifr_ntxqirq); 1605 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1606 txqid = rxq->ifr_txqid[i]; 1607 txq = &ctx->ifc_txqs[txqid]; 1608 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1609 BUS_DMASYNC_POSTREAD); 1610 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1611 if (intr_legacy) 1612 intr_enable = true; 1613 else 1614 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1615 continue; 1616 } 1617 GROUPTASK_ENQUEUE(&txq->ift_task); 1618 } 1619 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1620 cidx = rxq->ifr_cq_cidx; 1621 else 1622 cidx = rxq->ifr_fl[0].ifl_cidx; 1623 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1624 GROUPTASK_ENQUEUE(gtask); 1625 else { 1626 if (intr_legacy) 1627 intr_enable = true; 1628 else 1629 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1630 DBG_COUNTER_INC(rx_intr_enables); 1631 } 1632 if (intr_enable) 1633 IFDI_INTR_ENABLE(ctx); 1634 return (FILTER_HANDLED); 1635 } 1636 1637 static int 1638 iflib_fast_intr_ctx(void *arg) 1639 { 1640 iflib_filter_info_t info = arg; 1641 struct grouptask *gtask = info->ifi_task; 1642 int result; 1643 1644 DBG_COUNTER_INC(fast_intrs); 1645 if (info->ifi_filter != NULL) { 1646 result = info->ifi_filter(info->ifi_filter_arg); 1647 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1648 return (result); 1649 } 1650 1651 if (gtask->gt_taskqueue != NULL) 1652 GROUPTASK_ENQUEUE(gtask); 1653 return (FILTER_HANDLED); 1654 } 1655 1656 static int 1657 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1658 driver_filter_t filter, driver_intr_t handler, void *arg, 1659 const char *name) 1660 { 1661 struct resource *res; 1662 void *tag = NULL; 1663 device_t dev = ctx->ifc_dev; 1664 int flags, i, rc; 1665 1666 flags = RF_ACTIVE; 1667 if (ctx->ifc_flags & IFC_LEGACY) 1668 flags |= RF_SHAREABLE; 1669 MPASS(rid < 512); 1670 i = rid; 1671 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1672 if (res == NULL) { 1673 device_printf(dev, 1674 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1675 return (ENOMEM); 1676 } 1677 irq->ii_res = res; 1678 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1679 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1680 filter, handler, arg, &tag); 1681 if (rc != 0) { 1682 device_printf(dev, 1683 "failed to setup interrupt for rid %d, name %s: %d\n", 1684 rid, name ? name : "unknown", rc); 1685 return (rc); 1686 } else if (name) 1687 bus_describe_intr(dev, res, tag, "%s", name); 1688 1689 irq->ii_tag = tag; 1690 return (0); 1691 } 1692 1693 /********************************************************************* 1694 * 1695 * Allocate DMA resources for TX buffers as well as memory for the TX 1696 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1697 * iflib_sw_tx_desc_array structure, storing all the information that 1698 * is needed to transmit a packet on the wire. This is called only 1699 * once at attach, setup is done every reset. 1700 * 1701 **********************************************************************/ 1702 static int 1703 iflib_txsd_alloc(iflib_txq_t txq) 1704 { 1705 if_ctx_t ctx = txq->ift_ctx; 1706 if_shared_ctx_t sctx = ctx->ifc_sctx; 1707 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1708 device_t dev = ctx->ifc_dev; 1709 bus_size_t tsomaxsize; 1710 bus_addr_t lowaddr; 1711 int err, nsegments, ntsosegments; 1712 bool tso; 1713 1714 nsegments = scctx->isc_tx_nsegments; 1715 ntsosegments = scctx->isc_tx_tso_segments_max; 1716 tsomaxsize = scctx->isc_tx_tso_size_max; 1717 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1718 tsomaxsize += sizeof(struct ether_vlan_header); 1719 MPASS(scctx->isc_ntxd[0] > 0); 1720 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1721 MPASS(nsegments > 0); 1722 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1723 MPASS(ntsosegments > 0); 1724 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1725 } 1726 1727 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1728 1729 /* 1730 * Set up DMA tags for TX buffers. 1731 */ 1732 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1733 1, 0, /* alignment, bounds */ 1734 lowaddr, /* lowaddr */ 1735 BUS_SPACE_MAXADDR, /* highaddr */ 1736 NULL, NULL, /* filter, filterarg */ 1737 sctx->isc_tx_maxsize, /* maxsize */ 1738 nsegments, /* nsegments */ 1739 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1740 0, /* flags */ 1741 NULL, /* lockfunc */ 1742 NULL, /* lockfuncarg */ 1743 &txq->ift_buf_tag))) { 1744 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1745 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1746 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1747 goto fail; 1748 } 1749 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1750 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1751 1, 0, /* alignment, bounds */ 1752 lowaddr, /* lowaddr */ 1753 BUS_SPACE_MAXADDR, /* highaddr */ 1754 NULL, NULL, /* filter, filterarg */ 1755 tsomaxsize, /* maxsize */ 1756 ntsosegments, /* nsegments */ 1757 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1758 0, /* flags */ 1759 NULL, /* lockfunc */ 1760 NULL, /* lockfuncarg */ 1761 &txq->ift_tso_buf_tag))) { 1762 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1763 err); 1764 goto fail; 1765 } 1766 1767 /* Allocate memory for the TX mbuf map. */ 1768 if (!(txq->ift_sds.ifsd_m = 1769 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1770 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1771 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1772 err = ENOMEM; 1773 goto fail; 1774 } 1775 1776 /* 1777 * Create the DMA maps for TX buffers. 1778 */ 1779 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1780 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1781 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1782 device_printf(dev, 1783 "Unable to allocate TX buffer DMA map memory\n"); 1784 err = ENOMEM; 1785 goto fail; 1786 } 1787 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1788 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1789 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1790 device_printf(dev, 1791 "Unable to allocate TSO TX buffer map memory\n"); 1792 err = ENOMEM; 1793 goto fail; 1794 } 1795 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1796 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1797 &txq->ift_sds.ifsd_map[i]); 1798 if (err != 0) { 1799 device_printf(dev, "Unable to create TX DMA map\n"); 1800 goto fail; 1801 } 1802 if (!tso) 1803 continue; 1804 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1805 &txq->ift_sds.ifsd_tso_map[i]); 1806 if (err != 0) { 1807 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1808 goto fail; 1809 } 1810 } 1811 return (0); 1812 fail: 1813 /* We free all, it handles case where we are in the middle */ 1814 iflib_tx_structures_free(ctx); 1815 return (err); 1816 } 1817 1818 static void 1819 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1820 { 1821 bus_dmamap_t map; 1822 1823 if (txq->ift_sds.ifsd_map != NULL) { 1824 map = txq->ift_sds.ifsd_map[i]; 1825 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1826 bus_dmamap_unload(txq->ift_buf_tag, map); 1827 bus_dmamap_destroy(txq->ift_buf_tag, map); 1828 txq->ift_sds.ifsd_map[i] = NULL; 1829 } 1830 1831 if (txq->ift_sds.ifsd_tso_map != NULL) { 1832 map = txq->ift_sds.ifsd_tso_map[i]; 1833 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1834 BUS_DMASYNC_POSTWRITE); 1835 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1836 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1837 txq->ift_sds.ifsd_tso_map[i] = NULL; 1838 } 1839 } 1840 1841 static void 1842 iflib_txq_destroy(iflib_txq_t txq) 1843 { 1844 if_ctx_t ctx = txq->ift_ctx; 1845 1846 for (int i = 0; i < txq->ift_size; i++) 1847 iflib_txsd_destroy(ctx, txq, i); 1848 1849 if (txq->ift_br != NULL) { 1850 ifmp_ring_free(txq->ift_br); 1851 txq->ift_br = NULL; 1852 } 1853 1854 mtx_destroy(&txq->ift_mtx); 1855 1856 if (txq->ift_sds.ifsd_map != NULL) { 1857 free(txq->ift_sds.ifsd_map, M_IFLIB); 1858 txq->ift_sds.ifsd_map = NULL; 1859 } 1860 if (txq->ift_sds.ifsd_tso_map != NULL) { 1861 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1862 txq->ift_sds.ifsd_tso_map = NULL; 1863 } 1864 if (txq->ift_sds.ifsd_m != NULL) { 1865 free(txq->ift_sds.ifsd_m, M_IFLIB); 1866 txq->ift_sds.ifsd_m = NULL; 1867 } 1868 if (txq->ift_buf_tag != NULL) { 1869 bus_dma_tag_destroy(txq->ift_buf_tag); 1870 txq->ift_buf_tag = NULL; 1871 } 1872 if (txq->ift_tso_buf_tag != NULL) { 1873 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1874 txq->ift_tso_buf_tag = NULL; 1875 } 1876 if (txq->ift_ifdi != NULL) { 1877 free(txq->ift_ifdi, M_IFLIB); 1878 } 1879 } 1880 1881 static void 1882 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1883 { 1884 struct mbuf **mp; 1885 1886 mp = &txq->ift_sds.ifsd_m[i]; 1887 if (*mp == NULL) 1888 return; 1889 1890 if (txq->ift_sds.ifsd_map != NULL) { 1891 bus_dmamap_sync(txq->ift_buf_tag, 1892 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1893 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1894 } 1895 if (txq->ift_sds.ifsd_tso_map != NULL) { 1896 bus_dmamap_sync(txq->ift_tso_buf_tag, 1897 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1898 bus_dmamap_unload(txq->ift_tso_buf_tag, 1899 txq->ift_sds.ifsd_tso_map[i]); 1900 } 1901 m_freem(*mp); 1902 DBG_COUNTER_INC(tx_frees); 1903 *mp = NULL; 1904 } 1905 1906 static int 1907 iflib_txq_setup(iflib_txq_t txq) 1908 { 1909 if_ctx_t ctx = txq->ift_ctx; 1910 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1911 if_shared_ctx_t sctx = ctx->ifc_sctx; 1912 iflib_dma_info_t di; 1913 int i; 1914 1915 /* Set number of descriptors available */ 1916 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1917 /* XXX make configurable */ 1918 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1919 1920 /* Reset indices */ 1921 txq->ift_cidx_processed = 0; 1922 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1923 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1924 1925 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1926 bzero((void *)di->idi_vaddr, di->idi_size); 1927 1928 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1929 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1930 bus_dmamap_sync(di->idi_tag, di->idi_map, 1931 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1932 return (0); 1933 } 1934 1935 /********************************************************************* 1936 * 1937 * Allocate DMA resources for RX buffers as well as memory for the RX 1938 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1939 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1940 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1941 * Since we use use one entry in iflib_sw_rx_desc_array per received 1942 * packet, the maximum number of entries we'll need is equal to the 1943 * number of hardware receive descriptors that we've allocated. 1944 * 1945 **********************************************************************/ 1946 static int 1947 iflib_rxsd_alloc(iflib_rxq_t rxq) 1948 { 1949 if_ctx_t ctx = rxq->ifr_ctx; 1950 if_shared_ctx_t sctx = ctx->ifc_sctx; 1951 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1952 device_t dev = ctx->ifc_dev; 1953 iflib_fl_t fl; 1954 bus_addr_t lowaddr; 1955 int err; 1956 1957 MPASS(scctx->isc_nrxd[0] > 0); 1958 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1959 1960 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1961 1962 fl = rxq->ifr_fl; 1963 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1964 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1965 /* Set up DMA tag for RX buffers. */ 1966 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1967 1, 0, /* alignment, bounds */ 1968 lowaddr, /* lowaddr */ 1969 BUS_SPACE_MAXADDR, /* highaddr */ 1970 NULL, NULL, /* filter, filterarg */ 1971 sctx->isc_rx_maxsize, /* maxsize */ 1972 sctx->isc_rx_nsegments, /* nsegments */ 1973 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1974 0, /* flags */ 1975 NULL, /* lockfunc */ 1976 NULL, /* lockarg */ 1977 &fl->ifl_buf_tag); 1978 if (err) { 1979 device_printf(dev, 1980 "Unable to allocate RX DMA tag: %d\n", err); 1981 goto fail; 1982 } 1983 1984 /* Allocate memory for the RX mbuf map. */ 1985 if (!(fl->ifl_sds.ifsd_m = 1986 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1987 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1988 device_printf(dev, 1989 "Unable to allocate RX mbuf map memory\n"); 1990 err = ENOMEM; 1991 goto fail; 1992 } 1993 1994 /* Allocate memory for the direct RX cluster pointer map. */ 1995 if (!(fl->ifl_sds.ifsd_cl = 1996 (caddr_t *) malloc(sizeof(caddr_t) * 1997 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1998 device_printf(dev, 1999 "Unable to allocate RX cluster map memory\n"); 2000 err = ENOMEM; 2001 goto fail; 2002 } 2003 2004 /* Allocate memory for the RX cluster bus address map. */ 2005 if (!(fl->ifl_sds.ifsd_ba = 2006 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 2007 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2008 device_printf(dev, 2009 "Unable to allocate RX bus address map memory\n"); 2010 err = ENOMEM; 2011 goto fail; 2012 } 2013 2014 /* 2015 * Create the DMA maps for RX buffers. 2016 */ 2017 if (!(fl->ifl_sds.ifsd_map = 2018 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2019 device_printf(dev, 2020 "Unable to allocate RX buffer DMA map memory\n"); 2021 err = ENOMEM; 2022 goto fail; 2023 } 2024 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2025 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2026 &fl->ifl_sds.ifsd_map[i]); 2027 if (err != 0) { 2028 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2029 goto fail; 2030 } 2031 } 2032 } 2033 return (0); 2034 2035 fail: 2036 iflib_rx_structures_free(ctx); 2037 return (err); 2038 } 2039 2040 /* 2041 * Internal service routines 2042 */ 2043 2044 struct rxq_refill_cb_arg { 2045 int error; 2046 bus_dma_segment_t seg; 2047 int nseg; 2048 }; 2049 2050 static void 2051 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2052 { 2053 struct rxq_refill_cb_arg *cb_arg = arg; 2054 2055 cb_arg->error = error; 2056 cb_arg->seg = segs[0]; 2057 cb_arg->nseg = nseg; 2058 } 2059 2060 /** 2061 * iflib_fl_refill - refill an rxq free-buffer list 2062 * @ctx: the iflib context 2063 * @fl: the free list to refill 2064 * @count: the number of new buffers to allocate 2065 * 2066 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2067 * The caller must assure that @count does not exceed the queue's capacity 2068 * minus one (since we always leave a descriptor unavailable). 2069 */ 2070 static uint8_t 2071 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2072 { 2073 struct if_rxd_update iru; 2074 struct rxq_refill_cb_arg cb_arg; 2075 struct mbuf *m; 2076 caddr_t cl, *sd_cl; 2077 struct mbuf **sd_m; 2078 bus_dmamap_t *sd_map; 2079 bus_addr_t bus_addr, *sd_ba; 2080 int err, frag_idx, i, idx, n, pidx; 2081 qidx_t credits; 2082 2083 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2084 2085 sd_m = fl->ifl_sds.ifsd_m; 2086 sd_map = fl->ifl_sds.ifsd_map; 2087 sd_cl = fl->ifl_sds.ifsd_cl; 2088 sd_ba = fl->ifl_sds.ifsd_ba; 2089 pidx = fl->ifl_pidx; 2090 idx = pidx; 2091 frag_idx = fl->ifl_fragidx; 2092 credits = fl->ifl_credits; 2093 2094 i = 0; 2095 n = count; 2096 MPASS(n > 0); 2097 MPASS(credits + n <= fl->ifl_size); 2098 2099 if (pidx < fl->ifl_cidx) 2100 MPASS(pidx + n <= fl->ifl_cidx); 2101 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2102 MPASS(fl->ifl_gen == 0); 2103 if (pidx > fl->ifl_cidx) 2104 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2105 2106 DBG_COUNTER_INC(fl_refills); 2107 if (n > 8) 2108 DBG_COUNTER_INC(fl_refills_large); 2109 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2110 while (n-- > 0) { 2111 /* 2112 * We allocate an uninitialized mbuf + cluster, mbuf is 2113 * initialized after rx. 2114 * 2115 * If the cluster is still set then we know a minimum sized 2116 * packet was received 2117 */ 2118 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2119 &frag_idx); 2120 if (frag_idx < 0) 2121 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2122 MPASS(frag_idx >= 0); 2123 if ((cl = sd_cl[frag_idx]) == NULL) { 2124 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2125 if (__predict_false(cl == NULL)) 2126 break; 2127 2128 cb_arg.error = 0; 2129 MPASS(sd_map != NULL); 2130 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2131 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2132 BUS_DMA_NOWAIT); 2133 if (__predict_false(err != 0 || cb_arg.error)) { 2134 uma_zfree(fl->ifl_zone, cl); 2135 break; 2136 } 2137 2138 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2139 sd_cl[frag_idx] = cl; 2140 #if MEMORY_LOGGING 2141 fl->ifl_cl_enqueued++; 2142 #endif 2143 } else { 2144 bus_addr = sd_ba[frag_idx]; 2145 } 2146 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2147 BUS_DMASYNC_PREREAD); 2148 2149 if (sd_m[frag_idx] == NULL) { 2150 m = m_gethdr_raw(M_NOWAIT, 0); 2151 if (__predict_false(m == NULL)) 2152 break; 2153 sd_m[frag_idx] = m; 2154 } 2155 bit_set(fl->ifl_rx_bitmap, frag_idx); 2156 #if MEMORY_LOGGING 2157 fl->ifl_m_enqueued++; 2158 #endif 2159 2160 DBG_COUNTER_INC(rx_allocs); 2161 fl->ifl_rxd_idxs[i] = frag_idx; 2162 fl->ifl_bus_addrs[i] = bus_addr; 2163 credits++; 2164 i++; 2165 MPASS(credits <= fl->ifl_size); 2166 if (++idx == fl->ifl_size) { 2167 #ifdef INVARIANTS 2168 fl->ifl_gen = 1; 2169 #endif 2170 idx = 0; 2171 } 2172 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2173 iru.iru_pidx = pidx; 2174 iru.iru_count = i; 2175 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2176 fl->ifl_pidx = idx; 2177 fl->ifl_credits = credits; 2178 pidx = idx; 2179 i = 0; 2180 } 2181 } 2182 2183 if (n < count - 1) { 2184 if (i != 0) { 2185 iru.iru_pidx = pidx; 2186 iru.iru_count = i; 2187 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2188 fl->ifl_pidx = idx; 2189 fl->ifl_credits = credits; 2190 } 2191 DBG_COUNTER_INC(rxd_flush); 2192 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2193 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2194 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2195 fl->ifl_id, fl->ifl_pidx); 2196 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2197 fl->ifl_fragidx = frag_idx + 1; 2198 if (fl->ifl_fragidx == fl->ifl_size) 2199 fl->ifl_fragidx = 0; 2200 } else { 2201 fl->ifl_fragidx = frag_idx; 2202 } 2203 } 2204 2205 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2206 } 2207 2208 static inline uint8_t 2209 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2210 { 2211 /* 2212 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2213 * This is important as it confuses most NICs. For instance, 2214 * Intel NICs have (per receive ring) RDH and RDT registers, where 2215 * RDH points to the next receive descriptor to be used by the NIC, 2216 * and RDT for the next receive descriptor to be published by the 2217 * driver to the NIC (RDT - 1 is thus the last valid one). 2218 * The condition RDH == RDT means no descriptors are available to 2219 * the NIC, and thus it would be ambiguous if it also meant that 2220 * all the descriptors are available to the NIC. 2221 */ 2222 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2223 #ifdef INVARIANTS 2224 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2225 #endif 2226 2227 MPASS(fl->ifl_credits <= fl->ifl_size); 2228 MPASS(reclaimable == delta); 2229 2230 if (reclaimable > 0) 2231 return (iflib_fl_refill(ctx, fl, reclaimable)); 2232 return (0); 2233 } 2234 2235 uint8_t 2236 iflib_in_detach(if_ctx_t ctx) 2237 { 2238 bool in_detach; 2239 2240 STATE_LOCK(ctx); 2241 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2242 STATE_UNLOCK(ctx); 2243 return (in_detach); 2244 } 2245 2246 static void 2247 iflib_fl_bufs_free(iflib_fl_t fl) 2248 { 2249 iflib_dma_info_t idi = fl->ifl_ifdi; 2250 bus_dmamap_t sd_map; 2251 uint32_t i; 2252 2253 for (i = 0; i < fl->ifl_size; i++) { 2254 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2255 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2256 2257 if (*sd_cl != NULL) { 2258 sd_map = fl->ifl_sds.ifsd_map[i]; 2259 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2260 BUS_DMASYNC_POSTREAD); 2261 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2262 uma_zfree(fl->ifl_zone, *sd_cl); 2263 *sd_cl = NULL; 2264 if (*sd_m != NULL) { 2265 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2266 m_free_raw(*sd_m); 2267 *sd_m = NULL; 2268 } 2269 } else { 2270 MPASS(*sd_m == NULL); 2271 } 2272 #if MEMORY_LOGGING 2273 fl->ifl_m_dequeued++; 2274 fl->ifl_cl_dequeued++; 2275 #endif 2276 } 2277 #ifdef INVARIANTS 2278 for (i = 0; i < fl->ifl_size; i++) { 2279 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2280 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2281 } 2282 #endif 2283 /* 2284 * Reset free list values 2285 */ 2286 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2287 bzero(idi->idi_vaddr, idi->idi_size); 2288 } 2289 2290 /********************************************************************* 2291 * 2292 * Initialize a free list and its buffers. 2293 * 2294 **********************************************************************/ 2295 static int 2296 iflib_fl_setup(iflib_fl_t fl) 2297 { 2298 iflib_rxq_t rxq = fl->ifl_rxq; 2299 if_ctx_t ctx = rxq->ifr_ctx; 2300 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2301 int qidx; 2302 2303 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2304 /* 2305 ** Free current RX buffer structs and their mbufs 2306 */ 2307 iflib_fl_bufs_free(fl); 2308 /* Now replenish the mbufs */ 2309 MPASS(fl->ifl_credits == 0); 2310 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2311 if (scctx->isc_rxd_buf_size[qidx] != 0) 2312 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2313 else 2314 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2315 /* 2316 * ifl_buf_size may be a driver-supplied value, so pull it up 2317 * to the selected mbuf size. 2318 */ 2319 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2320 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2321 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2322 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2323 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2324 2325 /* 2326 * Avoid pre-allocating zillions of clusters to an idle card 2327 * potentially speeding up attach. In any case make sure 2328 * to leave a descriptor unavailable. See the comment in 2329 * iflib_fl_refill_all(). 2330 */ 2331 MPASS(fl->ifl_size > 0); 2332 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2333 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2334 return (ENOBUFS); 2335 /* 2336 * handle failure 2337 */ 2338 MPASS(rxq != NULL); 2339 MPASS(fl->ifl_ifdi != NULL); 2340 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2341 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2342 return (0); 2343 } 2344 2345 /********************************************************************* 2346 * 2347 * Free receive ring data structures 2348 * 2349 **********************************************************************/ 2350 static void 2351 iflib_rx_sds_free(iflib_rxq_t rxq) 2352 { 2353 iflib_fl_t fl; 2354 int i, j; 2355 2356 if (rxq->ifr_fl != NULL) { 2357 for (i = 0; i < rxq->ifr_nfl; i++) { 2358 fl = &rxq->ifr_fl[i]; 2359 if (fl->ifl_buf_tag != NULL) { 2360 if (fl->ifl_sds.ifsd_map != NULL) { 2361 for (j = 0; j < fl->ifl_size; j++) { 2362 bus_dmamap_sync( 2363 fl->ifl_buf_tag, 2364 fl->ifl_sds.ifsd_map[j], 2365 BUS_DMASYNC_POSTREAD); 2366 bus_dmamap_unload( 2367 fl->ifl_buf_tag, 2368 fl->ifl_sds.ifsd_map[j]); 2369 bus_dmamap_destroy( 2370 fl->ifl_buf_tag, 2371 fl->ifl_sds.ifsd_map[j]); 2372 } 2373 } 2374 bus_dma_tag_destroy(fl->ifl_buf_tag); 2375 fl->ifl_buf_tag = NULL; 2376 } 2377 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2378 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2379 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2380 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2381 free(fl->ifl_rx_bitmap, M_IFLIB); 2382 fl->ifl_sds.ifsd_m = NULL; 2383 fl->ifl_sds.ifsd_cl = NULL; 2384 fl->ifl_sds.ifsd_ba = NULL; 2385 fl->ifl_sds.ifsd_map = NULL; 2386 fl->ifl_rx_bitmap = NULL; 2387 } 2388 free(rxq->ifr_fl, M_IFLIB); 2389 rxq->ifr_fl = NULL; 2390 free(rxq->ifr_ifdi, M_IFLIB); 2391 rxq->ifr_ifdi = NULL; 2392 rxq->ifr_cq_cidx = 0; 2393 } 2394 } 2395 2396 /* 2397 * Timer routine 2398 */ 2399 static void 2400 iflib_timer(void *arg) 2401 { 2402 iflib_txq_t txq = arg; 2403 if_ctx_t ctx = txq->ift_ctx; 2404 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2405 uint64_t this_tick = ticks; 2406 2407 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2408 return; 2409 2410 /* 2411 ** Check on the state of the TX queue(s), this 2412 ** can be done without the lock because its RO 2413 ** and the HUNG state will be static if set. 2414 */ 2415 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2416 txq->ift_last_timer_tick = this_tick; 2417 IFDI_TIMER(ctx, txq->ift_id); 2418 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2419 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2420 (sctx->isc_pause_frames == 0))) 2421 goto hung; 2422 2423 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2424 ifmp_ring_is_stalled(txq->ift_br)) { 2425 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2426 ("queue can't be marked as hung if interface is down")); 2427 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2428 } 2429 txq->ift_cleaned_prev = txq->ift_cleaned; 2430 } 2431 /* handle any laggards */ 2432 if (txq->ift_db_pending) 2433 GROUPTASK_ENQUEUE(&txq->ift_task); 2434 2435 sctx->isc_pause_frames = 0; 2436 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2437 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2438 txq, txq->ift_timer.c_cpu); 2439 return; 2440 2441 hung: 2442 device_printf(ctx->ifc_dev, 2443 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2444 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2445 STATE_LOCK(ctx); 2446 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2447 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2448 iflib_admin_intr_deferred(ctx); 2449 STATE_UNLOCK(ctx); 2450 } 2451 2452 static uint16_t 2453 iflib_get_mbuf_size_for(unsigned int size) 2454 { 2455 2456 if (size <= MCLBYTES) 2457 return (MCLBYTES); 2458 else 2459 return (MJUMPAGESIZE); 2460 } 2461 2462 static void 2463 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2464 { 2465 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2466 2467 /* 2468 * XXX don't set the max_frame_size to larger 2469 * than the hardware can handle 2470 */ 2471 ctx->ifc_rx_mbuf_sz = 2472 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2473 } 2474 2475 uint32_t 2476 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2477 { 2478 2479 return (ctx->ifc_rx_mbuf_sz); 2480 } 2481 2482 static void 2483 iflib_init_locked(if_ctx_t ctx) 2484 { 2485 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2486 if_t ifp = ctx->ifc_ifp; 2487 iflib_fl_t fl; 2488 iflib_txq_t txq; 2489 iflib_rxq_t rxq; 2490 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2491 2492 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2493 IFDI_INTR_DISABLE(ctx); 2494 2495 /* 2496 * See iflib_stop(). Useful in case iflib_init_locked() is 2497 * called without first calling iflib_stop(). 2498 */ 2499 netmap_disable_all_rings(ifp); 2500 2501 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2502 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2503 /* Set hardware offload abilities */ 2504 if_clearhwassist(ifp); 2505 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2506 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2507 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2508 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2509 if (if_getcapenable(ifp) & IFCAP_TSO4) 2510 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2511 if (if_getcapenable(ifp) & IFCAP_TSO6) 2512 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2513 2514 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 2515 CALLOUT_LOCK(txq); 2516 callout_stop(&txq->ift_timer); 2517 #ifdef DEV_NETMAP 2518 callout_stop(&txq->ift_netmap_timer); 2519 #endif /* DEV_NETMAP */ 2520 CALLOUT_UNLOCK(txq); 2521 (void)iflib_netmap_txq_init(ctx, txq); 2522 } 2523 2524 /* 2525 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2526 * that drivers can use the value when setting up the hardware receive 2527 * buffers. 2528 */ 2529 iflib_calc_rx_mbuf_sz(ctx); 2530 2531 #ifdef INVARIANTS 2532 i = if_getdrvflags(ifp); 2533 #endif 2534 IFDI_INIT(ctx); 2535 MPASS(if_getdrvflags(ifp) == i); 2536 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 2537 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2538 /* This rxq is in netmap mode. Skip normal init. */ 2539 continue; 2540 } 2541 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2542 if (iflib_fl_setup(fl)) { 2543 device_printf(ctx->ifc_dev, 2544 "setting up free list %d failed - " 2545 "check cluster settings\n", j); 2546 goto done; 2547 } 2548 } 2549 } 2550 done: 2551 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2552 IFDI_INTR_ENABLE(ctx); 2553 txq = ctx->ifc_txqs; 2554 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) 2555 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2556 txq->ift_timer.c_cpu); 2557 2558 /* Re-enable txsync/rxsync. */ 2559 netmap_enable_all_rings(ifp); 2560 } 2561 2562 static int 2563 iflib_media_change(if_t ifp) 2564 { 2565 if_ctx_t ctx = if_getsoftc(ifp); 2566 int err; 2567 2568 CTX_LOCK(ctx); 2569 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2570 iflib_if_init_locked(ctx); 2571 CTX_UNLOCK(ctx); 2572 return (err); 2573 } 2574 2575 static void 2576 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2577 { 2578 if_ctx_t ctx = if_getsoftc(ifp); 2579 2580 CTX_LOCK(ctx); 2581 IFDI_UPDATE_ADMIN_STATUS(ctx); 2582 IFDI_MEDIA_STATUS(ctx, ifmr); 2583 CTX_UNLOCK(ctx); 2584 } 2585 2586 void 2587 iflib_stop(if_ctx_t ctx) 2588 { 2589 iflib_txq_t txq = ctx->ifc_txqs; 2590 iflib_rxq_t rxq = ctx->ifc_rxqs; 2591 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2592 if_shared_ctx_t sctx = ctx->ifc_sctx; 2593 iflib_dma_info_t di; 2594 iflib_fl_t fl; 2595 int i, j; 2596 2597 /* Tell the stack that the interface is no longer active */ 2598 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2599 2600 IFDI_INTR_DISABLE(ctx); 2601 DELAY(1000); 2602 IFDI_STOP(ctx); 2603 DELAY(1000); 2604 2605 /* 2606 * Stop any pending txsync/rxsync and prevent new ones 2607 * form starting. Processes blocked in poll() will get 2608 * POLLERR. 2609 */ 2610 netmap_disable_all_rings(ctx->ifc_ifp); 2611 2612 iflib_debug_reset(); 2613 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2614 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2615 /* make sure all transmitters have completed before proceeding XXX */ 2616 2617 CALLOUT_LOCK(txq); 2618 callout_stop(&txq->ift_timer); 2619 #ifdef DEV_NETMAP 2620 callout_stop(&txq->ift_netmap_timer); 2621 #endif /* DEV_NETMAP */ 2622 CALLOUT_UNLOCK(txq); 2623 2624 /* clean any enqueued buffers */ 2625 iflib_ifmp_purge(txq); 2626 /* Free any existing tx buffers. */ 2627 for (j = 0; j < txq->ift_size; j++) { 2628 iflib_txsd_free(ctx, txq, j); 2629 } 2630 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2631 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2632 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2633 txq->ift_cidx = txq->ift_pidx; 2634 else 2635 txq->ift_cidx = txq->ift_pidx = 0; 2636 2637 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2638 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2639 txq->ift_pullups = 0; 2640 ifmp_ring_reset_stats(txq->ift_br); 2641 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2642 bzero((void *)di->idi_vaddr, di->idi_size); 2643 } 2644 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2645 if (rxq->ifr_task.gt_taskqueue != NULL) 2646 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2647 &rxq->ifr_task.gt_task); 2648 2649 rxq->ifr_cq_cidx = 0; 2650 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2651 bzero((void *)di->idi_vaddr, di->idi_size); 2652 /* also resets the free lists pidx/cidx */ 2653 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2654 iflib_fl_bufs_free(fl); 2655 } 2656 } 2657 2658 static inline caddr_t 2659 calc_next_rxd(iflib_fl_t fl, int cidx) 2660 { 2661 qidx_t size; 2662 int nrxd; 2663 caddr_t start, end, cur, next; 2664 2665 nrxd = fl->ifl_size; 2666 size = fl->ifl_rxd_size; 2667 start = fl->ifl_ifdi->idi_vaddr; 2668 2669 if (__predict_false(size == 0)) 2670 return (start); 2671 cur = start + size*cidx; 2672 end = start + size*nrxd; 2673 next = CACHE_PTR_NEXT(cur); 2674 return (next < end ? next : start); 2675 } 2676 2677 static inline void 2678 prefetch_pkts(iflib_fl_t fl, int cidx) 2679 { 2680 int nextptr; 2681 int nrxd = fl->ifl_size; 2682 caddr_t next_rxd; 2683 2684 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2685 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2686 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2687 next_rxd = calc_next_rxd(fl, cidx); 2688 prefetch(next_rxd); 2689 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2690 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2691 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2692 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2693 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2694 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2695 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2696 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2697 } 2698 2699 static struct mbuf * 2700 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2701 int *pf_rv, if_rxd_info_t ri) 2702 { 2703 bus_dmamap_t map; 2704 iflib_fl_t fl; 2705 caddr_t payload; 2706 struct mbuf *m; 2707 int flid, cidx, len, next; 2708 2709 map = NULL; 2710 flid = irf->irf_flid; 2711 cidx = irf->irf_idx; 2712 fl = &rxq->ifr_fl[flid]; 2713 sd->ifsd_fl = fl; 2714 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2715 fl->ifl_credits--; 2716 #if MEMORY_LOGGING 2717 fl->ifl_m_dequeued++; 2718 #endif 2719 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2720 prefetch_pkts(fl, cidx); 2721 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2722 prefetch(&fl->ifl_sds.ifsd_map[next]); 2723 map = fl->ifl_sds.ifsd_map[cidx]; 2724 2725 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2726 2727 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2728 irf->irf_len != 0) { 2729 payload = *sd->ifsd_cl; 2730 payload += ri->iri_pad; 2731 len = ri->iri_len - ri->iri_pad; 2732 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m); 2733 switch (*pf_rv) { 2734 case PFIL_DROPPED: 2735 case PFIL_CONSUMED: 2736 /* 2737 * The filter ate it. Everything is recycled. 2738 */ 2739 m = NULL; 2740 unload = 0; 2741 break; 2742 case PFIL_REALLOCED: 2743 /* 2744 * The filter copied it. Everything is recycled. 2745 * 'm' points at new mbuf. 2746 */ 2747 unload = 0; 2748 break; 2749 case PFIL_PASS: 2750 /* 2751 * Filter said it was OK, so receive like 2752 * normal 2753 */ 2754 m = fl->ifl_sds.ifsd_m[cidx]; 2755 fl->ifl_sds.ifsd_m[cidx] = NULL; 2756 break; 2757 default: 2758 MPASS(0); 2759 } 2760 } else { 2761 m = fl->ifl_sds.ifsd_m[cidx]; 2762 fl->ifl_sds.ifsd_m[cidx] = NULL; 2763 if (pf_rv != NULL) 2764 *pf_rv = PFIL_PASS; 2765 } 2766 2767 if (unload && irf->irf_len != 0) 2768 bus_dmamap_unload(fl->ifl_buf_tag, map); 2769 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2770 if (__predict_false(fl->ifl_cidx == 0)) 2771 fl->ifl_gen = 0; 2772 bit_clear(fl->ifl_rx_bitmap, cidx); 2773 return (m); 2774 } 2775 2776 static struct mbuf * 2777 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2778 { 2779 struct mbuf *m, *mh, *mt; 2780 caddr_t cl; 2781 int *pf_rv_ptr, flags, i, padlen; 2782 bool consumed; 2783 2784 i = 0; 2785 mh = NULL; 2786 consumed = false; 2787 *pf_rv = PFIL_PASS; 2788 pf_rv_ptr = pf_rv; 2789 do { 2790 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2791 pf_rv_ptr, ri); 2792 2793 MPASS(*sd->ifsd_cl != NULL); 2794 2795 /* 2796 * Exclude zero-length frags & frags from 2797 * packets the filter has consumed or dropped 2798 */ 2799 if (ri->iri_frags[i].irf_len == 0 || consumed || 2800 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2801 if (mh == NULL) { 2802 /* everything saved here */ 2803 consumed = true; 2804 pf_rv_ptr = NULL; 2805 continue; 2806 } 2807 /* XXX we can save the cluster here, but not the mbuf */ 2808 m_init(m, M_NOWAIT, MT_DATA, 0); 2809 m_free(m); 2810 continue; 2811 } 2812 if (mh == NULL) { 2813 flags = M_PKTHDR|M_EXT; 2814 mh = mt = m; 2815 padlen = ri->iri_pad; 2816 } else { 2817 flags = M_EXT; 2818 mt->m_next = m; 2819 mt = m; 2820 /* assuming padding is only on the first fragment */ 2821 padlen = 0; 2822 } 2823 cl = *sd->ifsd_cl; 2824 *sd->ifsd_cl = NULL; 2825 2826 /* Can these two be made one ? */ 2827 m_init(m, M_NOWAIT, MT_DATA, flags); 2828 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2829 /* 2830 * These must follow m_init and m_cljset 2831 */ 2832 m->m_data += padlen; 2833 ri->iri_len -= padlen; 2834 m->m_len = ri->iri_frags[i].irf_len; 2835 } while (++i < ri->iri_nfrags); 2836 2837 return (mh); 2838 } 2839 2840 /* 2841 * Process one software descriptor 2842 */ 2843 static struct mbuf * 2844 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2845 { 2846 struct if_rxsd sd; 2847 struct mbuf *m; 2848 int pf_rv; 2849 2850 /* should I merge this back in now that the two paths are basically duplicated? */ 2851 if (ri->iri_nfrags == 1 && 2852 ri->iri_frags[0].irf_len != 0 && 2853 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2854 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2855 &pf_rv, ri); 2856 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2857 return (m); 2858 if (pf_rv == PFIL_PASS) { 2859 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2860 #ifndef __NO_STRICT_ALIGNMENT 2861 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2862 m->m_data += 2; 2863 #endif 2864 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2865 m->m_len = ri->iri_frags[0].irf_len; 2866 m->m_data += ri->iri_pad; 2867 ri->iri_len -= ri->iri_pad; 2868 } 2869 } else { 2870 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2871 if (m == NULL) 2872 return (NULL); 2873 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2874 return (m); 2875 } 2876 m->m_pkthdr.len = ri->iri_len; 2877 m->m_pkthdr.rcvif = ri->iri_ifp; 2878 m->m_flags |= ri->iri_flags; 2879 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2880 m->m_pkthdr.flowid = ri->iri_flowid; 2881 M_HASHTYPE_SET(m, ri->iri_rsstype); 2882 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2883 m->m_pkthdr.csum_data = ri->iri_csum_data; 2884 return (m); 2885 } 2886 2887 #if defined(INET6) || defined(INET) 2888 static void 2889 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2890 { 2891 CURVNET_SET(if_getvnet(lc->ifp)); 2892 #if defined(INET6) 2893 *v6 = V_ip6_forwarding; 2894 #endif 2895 #if defined(INET) 2896 *v4 = V_ipforwarding; 2897 #endif 2898 CURVNET_RESTORE(); 2899 } 2900 2901 /* 2902 * Returns true if it's possible this packet could be LROed. 2903 * if it returns false, it is guaranteed that tcp_lro_rx() 2904 * would not return zero. 2905 */ 2906 static bool 2907 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2908 { 2909 struct ether_header *eh; 2910 2911 eh = mtod(m, struct ether_header *); 2912 switch (eh->ether_type) { 2913 #if defined(INET6) 2914 case htons(ETHERTYPE_IPV6): 2915 return (!v6_forwarding); 2916 #endif 2917 #if defined (INET) 2918 case htons(ETHERTYPE_IP): 2919 return (!v4_forwarding); 2920 #endif 2921 } 2922 2923 return false; 2924 } 2925 #else 2926 static void 2927 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2928 { 2929 } 2930 #endif 2931 2932 static void 2933 _task_fn_rx_watchdog(void *context) 2934 { 2935 iflib_rxq_t rxq = context; 2936 2937 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2938 } 2939 2940 static uint8_t 2941 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2942 { 2943 if_t ifp; 2944 if_ctx_t ctx = rxq->ifr_ctx; 2945 if_shared_ctx_t sctx = ctx->ifc_sctx; 2946 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2947 int avail, i; 2948 qidx_t *cidxp; 2949 struct if_rxd_info ri; 2950 int err, budget_left, rx_bytes, rx_pkts; 2951 iflib_fl_t fl; 2952 int lro_enabled; 2953 bool v4_forwarding, v6_forwarding, lro_possible; 2954 uint8_t retval = 0; 2955 2956 /* 2957 * XXX early demux data packets so that if_input processing only handles 2958 * acks in interrupt context 2959 */ 2960 struct mbuf *m, *mh, *mt, *mf; 2961 2962 NET_EPOCH_ASSERT(); 2963 2964 lro_possible = v4_forwarding = v6_forwarding = false; 2965 ifp = ctx->ifc_ifp; 2966 mh = mt = NULL; 2967 MPASS(budget > 0); 2968 rx_pkts = rx_bytes = 0; 2969 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2970 cidxp = &rxq->ifr_cq_cidx; 2971 else 2972 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2973 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2974 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2975 retval |= iflib_fl_refill_all(ctx, fl); 2976 DBG_COUNTER_INC(rx_unavail); 2977 return (retval); 2978 } 2979 2980 /* pfil needs the vnet to be set */ 2981 CURVNET_SET_QUIET(if_getvnet(ifp)); 2982 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2983 if (__predict_false(!CTX_ACTIVE(ctx))) { 2984 DBG_COUNTER_INC(rx_ctx_inactive); 2985 break; 2986 } 2987 /* 2988 * Reset client set fields to their default values 2989 */ 2990 rxd_info_zero(&ri); 2991 ri.iri_qsidx = rxq->ifr_id; 2992 ri.iri_cidx = *cidxp; 2993 ri.iri_ifp = ifp; 2994 ri.iri_frags = rxq->ifr_frags; 2995 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2996 2997 if (err) 2998 goto err; 2999 rx_pkts += 1; 3000 rx_bytes += ri.iri_len; 3001 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 3002 *cidxp = ri.iri_cidx; 3003 /* Update our consumer index */ 3004 /* XXX NB: shurd - check if this is still safe */ 3005 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 3006 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 3007 /* was this only a completion queue message? */ 3008 if (__predict_false(ri.iri_nfrags == 0)) 3009 continue; 3010 } 3011 MPASS(ri.iri_nfrags != 0); 3012 MPASS(ri.iri_len != 0); 3013 3014 /* will advance the cidx on the corresponding free lists */ 3015 m = iflib_rxd_pkt_get(rxq, &ri); 3016 avail--; 3017 budget_left--; 3018 if (avail == 0 && budget_left) 3019 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 3020 3021 if (__predict_false(m == NULL)) 3022 continue; 3023 3024 /* imm_pkt: -- cxgb */ 3025 if (mh == NULL) 3026 mh = mt = m; 3027 else { 3028 mt->m_nextpkt = m; 3029 mt = m; 3030 } 3031 } 3032 CURVNET_RESTORE(); 3033 /* make sure that we can refill faster than drain */ 3034 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3035 retval |= iflib_fl_refill_all(ctx, fl); 3036 3037 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3038 if (lro_enabled) 3039 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 3040 mt = mf = NULL; 3041 while (mh != NULL) { 3042 m = mh; 3043 mh = mh->m_nextpkt; 3044 m->m_nextpkt = NULL; 3045 #ifndef __NO_STRICT_ALIGNMENT 3046 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3047 continue; 3048 #endif 3049 #if defined(INET6) || defined(INET) 3050 if (lro_enabled) { 3051 if (!lro_possible) { 3052 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 3053 if (lro_possible && mf != NULL) { 3054 if_input(ifp, mf); 3055 DBG_COUNTER_INC(rx_if_input); 3056 mt = mf = NULL; 3057 } 3058 } 3059 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3060 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3061 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3062 continue; 3063 } 3064 } 3065 #endif 3066 if (lro_possible) { 3067 if_input(ifp, m); 3068 DBG_COUNTER_INC(rx_if_input); 3069 continue; 3070 } 3071 3072 if (mf == NULL) 3073 mf = m; 3074 if (mt != NULL) 3075 mt->m_nextpkt = m; 3076 mt = m; 3077 } 3078 if (mf != NULL) { 3079 if_input(ifp, mf); 3080 DBG_COUNTER_INC(rx_if_input); 3081 } 3082 3083 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3084 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3085 3086 /* 3087 * Flush any outstanding LRO work 3088 */ 3089 #if defined(INET6) || defined(INET) 3090 tcp_lro_flush_all(&rxq->ifr_lc); 3091 #endif 3092 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3093 retval |= IFLIB_RXEOF_MORE; 3094 return (retval); 3095 err: 3096 STATE_LOCK(ctx); 3097 ctx->ifc_flags |= IFC_DO_RESET; 3098 iflib_admin_intr_deferred(ctx); 3099 STATE_UNLOCK(ctx); 3100 return (0); 3101 } 3102 3103 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3104 static inline qidx_t 3105 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3106 { 3107 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3108 qidx_t minthresh = txq->ift_size / 8; 3109 if (in_use > 4*minthresh) 3110 return (notify_count); 3111 if (in_use > 2*minthresh) 3112 return (notify_count >> 1); 3113 if (in_use > minthresh) 3114 return (notify_count >> 3); 3115 return (0); 3116 } 3117 3118 static inline qidx_t 3119 txq_max_rs_deferred(iflib_txq_t txq) 3120 { 3121 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3122 qidx_t minthresh = txq->ift_size / 8; 3123 if (txq->ift_in_use > 4*minthresh) 3124 return (notify_count); 3125 if (txq->ift_in_use > 2*minthresh) 3126 return (notify_count >> 1); 3127 if (txq->ift_in_use > minthresh) 3128 return (notify_count >> 2); 3129 return (2); 3130 } 3131 3132 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3133 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3134 3135 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3136 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3137 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3138 3139 /* forward compatibility for cxgb */ 3140 #define FIRST_QSET(ctx) 0 3141 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3142 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3143 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3144 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3145 3146 /* XXX we should be setting this to something other than zero */ 3147 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3148 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3149 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3150 3151 static inline bool 3152 iflib_txd_db_check(iflib_txq_t txq, int ring) 3153 { 3154 if_ctx_t ctx = txq->ift_ctx; 3155 qidx_t dbval, max; 3156 3157 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3158 3159 /* force || threshold exceeded || at the edge of the ring */ 3160 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3161 3162 /* 3163 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3164 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3165 * producer index explicitly (INTC). 3166 */ 3167 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3168 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3169 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3170 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3171 3172 /* 3173 * Absent bugs there are zero packets pending so reset pending counts to zero. 3174 */ 3175 txq->ift_db_pending = txq->ift_npending = 0; 3176 return (true); 3177 } 3178 return (false); 3179 } 3180 3181 #ifdef PKT_DEBUG 3182 static void 3183 print_pkt(if_pkt_info_t pi) 3184 { 3185 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3186 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3187 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3188 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3189 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3190 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3191 } 3192 #endif 3193 3194 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3195 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3196 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3197 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3198 3199 /** 3200 * Parses out ethernet header information in the given mbuf. 3201 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length) 3202 * 3203 * This will account for the VLAN header if present. 3204 * 3205 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those 3206 * types of packets. 3207 */ 3208 static int 3209 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3210 { 3211 struct ether_vlan_header *eh; 3212 struct mbuf *m; 3213 3214 m = *mp; 3215 if (__predict_false(m->m_len < sizeof(*eh))) { 3216 (*pullups)++; 3217 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3218 return (ENOMEM); 3219 } 3220 eh = mtod(m, struct ether_vlan_header *); 3221 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3222 pi->ipi_etype = ntohs(eh->evl_proto); 3223 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3224 } else { 3225 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3226 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3227 } 3228 *mp = m; 3229 3230 return (0); 3231 } 3232 3233 /** 3234 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi. 3235 * Currently this information includes: IP ToS value, IP header version/presence 3236 * 3237 * This is missing some checks and doesn't edit the packet content as it goes, 3238 * unlike iflib_parse_header(), in order to keep the amount of code here minimal. 3239 */ 3240 static int 3241 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups) 3242 { 3243 struct mbuf *m; 3244 int err; 3245 3246 *pullups = 0; 3247 m = *mp; 3248 if (!M_WRITABLE(m)) { 3249 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3250 return (ENOMEM); 3251 } else { 3252 m_freem(*mp); 3253 DBG_COUNTER_INC(tx_frees); 3254 *mp = m; 3255 } 3256 } 3257 3258 /* Fills out pi->ipi_etype */ 3259 err = iflib_parse_ether_header(pi, mp, pullups); 3260 if (err) 3261 return (err); 3262 m = *mp; 3263 3264 switch (pi->ipi_etype) { 3265 #ifdef INET 3266 case ETHERTYPE_IP: 3267 { 3268 struct mbuf *n; 3269 struct ip *ip = NULL; 3270 int miniplen; 3271 3272 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip)); 3273 if (__predict_false(m->m_len < miniplen)) { 3274 /* 3275 * Check for common case where the first mbuf only contains 3276 * the Ethernet header 3277 */ 3278 if (m->m_len == pi->ipi_ehdrlen) { 3279 n = m->m_next; 3280 MPASS(n); 3281 /* If next mbuf contains at least the minimal IP header, then stop */ 3282 if (n->m_len >= sizeof(*ip)) { 3283 ip = (struct ip *)n->m_data; 3284 } else { 3285 (*pullups)++; 3286 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3287 return (ENOMEM); 3288 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3289 } 3290 } else { 3291 (*pullups)++; 3292 if (__predict_false((m = m_pullup(m, miniplen)) == NULL)) 3293 return (ENOMEM); 3294 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3295 } 3296 } else { 3297 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3298 } 3299 3300 /* Have the IPv4 header w/ no options here */ 3301 pi->ipi_ip_hlen = ip->ip_hl << 2; 3302 pi->ipi_ipproto = ip->ip_p; 3303 pi->ipi_ip_tos = ip->ip_tos; 3304 pi->ipi_flags |= IPI_TX_IPV4; 3305 3306 break; 3307 } 3308 #endif 3309 #ifdef INET6 3310 case ETHERTYPE_IPV6: 3311 { 3312 struct ip6_hdr *ip6; 3313 3314 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3315 (*pullups)++; 3316 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3317 return (ENOMEM); 3318 } 3319 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3320 3321 /* Have the IPv6 fixed header here */ 3322 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3323 pi->ipi_ipproto = ip6->ip6_nxt; 3324 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3325 pi->ipi_flags |= IPI_TX_IPV6; 3326 3327 break; 3328 } 3329 #endif 3330 default: 3331 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3332 pi->ipi_ip_hlen = 0; 3333 break; 3334 } 3335 *mp = m; 3336 3337 return (0); 3338 3339 } 3340 3341 static int 3342 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3343 { 3344 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3345 struct mbuf *m; 3346 int err; 3347 3348 m = *mp; 3349 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3350 M_WRITABLE(m) == 0) { 3351 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3352 return (ENOMEM); 3353 } else { 3354 m_freem(*mp); 3355 DBG_COUNTER_INC(tx_frees); 3356 *mp = m; 3357 } 3358 } 3359 3360 /* Fills out pi->ipi_etype */ 3361 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups); 3362 if (__predict_false(err)) 3363 return (err); 3364 m = *mp; 3365 3366 switch (pi->ipi_etype) { 3367 #ifdef INET 3368 case ETHERTYPE_IP: 3369 { 3370 struct mbuf *n; 3371 struct ip *ip = NULL; 3372 struct tcphdr *th = NULL; 3373 int minthlen; 3374 3375 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3376 if (__predict_false(m->m_len < minthlen)) { 3377 /* 3378 * if this code bloat is causing too much of a hit 3379 * move it to a separate function and mark it noinline 3380 */ 3381 if (m->m_len == pi->ipi_ehdrlen) { 3382 n = m->m_next; 3383 MPASS(n); 3384 if (n->m_len >= sizeof(*ip)) { 3385 ip = (struct ip *)n->m_data; 3386 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3387 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3388 } else { 3389 txq->ift_pullups++; 3390 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3391 return (ENOMEM); 3392 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3393 } 3394 } else { 3395 txq->ift_pullups++; 3396 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3397 return (ENOMEM); 3398 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3399 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3400 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3401 } 3402 } else { 3403 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3404 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3405 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3406 } 3407 pi->ipi_ip_hlen = ip->ip_hl << 2; 3408 pi->ipi_ipproto = ip->ip_p; 3409 pi->ipi_ip_tos = ip->ip_tos; 3410 pi->ipi_flags |= IPI_TX_IPV4; 3411 3412 /* TCP checksum offload may require TCP header length */ 3413 if (IS_TX_OFFLOAD4(pi)) { 3414 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3415 if (__predict_false(th == NULL)) { 3416 txq->ift_pullups++; 3417 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3418 return (ENOMEM); 3419 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3420 } 3421 pi->ipi_tcp_hflags = th->th_flags; 3422 pi->ipi_tcp_hlen = th->th_off << 2; 3423 pi->ipi_tcp_seq = th->th_seq; 3424 } 3425 if (IS_TSO4(pi)) { 3426 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3427 return (ENXIO); 3428 /* 3429 * TSO always requires hardware checksum offload. 3430 */ 3431 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3432 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3433 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3434 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3435 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3436 ip->ip_sum = 0; 3437 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3438 } 3439 } 3440 } 3441 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3442 ip->ip_sum = 0; 3443 3444 break; 3445 } 3446 #endif 3447 #ifdef INET6 3448 case ETHERTYPE_IPV6: 3449 { 3450 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3451 struct tcphdr *th; 3452 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3453 3454 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3455 txq->ift_pullups++; 3456 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3457 return (ENOMEM); 3458 } 3459 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3460 3461 /* XXX-BZ this will go badly in case of ext hdrs. */ 3462 pi->ipi_ipproto = ip6->ip6_nxt; 3463 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6); 3464 pi->ipi_flags |= IPI_TX_IPV6; 3465 3466 /* TCP checksum offload may require TCP header length */ 3467 if (IS_TX_OFFLOAD6(pi)) { 3468 if (pi->ipi_ipproto == IPPROTO_TCP) { 3469 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3470 txq->ift_pullups++; 3471 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3472 return (ENOMEM); 3473 } 3474 pi->ipi_tcp_hflags = th->th_flags; 3475 pi->ipi_tcp_hlen = th->th_off << 2; 3476 pi->ipi_tcp_seq = th->th_seq; 3477 } 3478 if (IS_TSO6(pi)) { 3479 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3480 return (ENXIO); 3481 /* 3482 * TSO always requires hardware checksum offload. 3483 */ 3484 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3485 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3486 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3487 } 3488 } 3489 break; 3490 } 3491 #endif 3492 default: 3493 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3494 pi->ipi_ip_hlen = 0; 3495 break; 3496 } 3497 *mp = m; 3498 3499 return (0); 3500 } 3501 3502 /* 3503 * If dodgy hardware rejects the scatter gather chain we've handed it 3504 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3505 * m_defrag'd mbufs 3506 */ 3507 static __noinline struct mbuf * 3508 iflib_remove_mbuf(iflib_txq_t txq) 3509 { 3510 int ntxd, pidx; 3511 struct mbuf *m, **ifsd_m; 3512 3513 ifsd_m = txq->ift_sds.ifsd_m; 3514 ntxd = txq->ift_size; 3515 pidx = txq->ift_pidx & (ntxd - 1); 3516 ifsd_m = txq->ift_sds.ifsd_m; 3517 m = ifsd_m[pidx]; 3518 ifsd_m[pidx] = NULL; 3519 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3520 if (txq->ift_sds.ifsd_tso_map != NULL) 3521 bus_dmamap_unload(txq->ift_tso_buf_tag, 3522 txq->ift_sds.ifsd_tso_map[pidx]); 3523 #if MEMORY_LOGGING 3524 txq->ift_dequeued++; 3525 #endif 3526 return (m); 3527 } 3528 3529 static inline caddr_t 3530 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3531 { 3532 qidx_t size; 3533 int ntxd; 3534 caddr_t start, end, cur, next; 3535 3536 ntxd = txq->ift_size; 3537 size = txq->ift_txd_size[qid]; 3538 start = txq->ift_ifdi[qid].idi_vaddr; 3539 3540 if (__predict_false(size == 0)) 3541 return (start); 3542 cur = start + size*cidx; 3543 end = start + size*ntxd; 3544 next = CACHE_PTR_NEXT(cur); 3545 return (next < end ? next : start); 3546 } 3547 3548 /* 3549 * Pad an mbuf to ensure a minimum ethernet frame size. 3550 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3551 */ 3552 static __noinline int 3553 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3554 { 3555 /* 3556 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3557 * and ARP message is the smallest common payload I can think of 3558 */ 3559 static char pad[18]; /* just zeros */ 3560 int n; 3561 struct mbuf *new_head; 3562 3563 if (!M_WRITABLE(*m_head)) { 3564 new_head = m_dup(*m_head, M_NOWAIT); 3565 if (new_head == NULL) { 3566 m_freem(*m_head); 3567 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3568 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3569 DBG_COUNTER_INC(tx_frees); 3570 return ENOMEM; 3571 } 3572 m_freem(*m_head); 3573 *m_head = new_head; 3574 } 3575 3576 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3577 n > 0; n -= sizeof(pad)) 3578 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3579 break; 3580 3581 if (n > 0) { 3582 m_freem(*m_head); 3583 device_printf(dev, "cannot pad short frame\n"); 3584 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3585 DBG_COUNTER_INC(tx_frees); 3586 return (ENOBUFS); 3587 } 3588 3589 return 0; 3590 } 3591 3592 static int 3593 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3594 { 3595 if_ctx_t ctx; 3596 if_shared_ctx_t sctx; 3597 if_softc_ctx_t scctx; 3598 bus_dma_tag_t buf_tag; 3599 bus_dma_segment_t *segs; 3600 struct mbuf *m_head, **ifsd_m; 3601 void *next_txd; 3602 bus_dmamap_t map; 3603 struct if_pkt_info pi; 3604 int remap = 0; 3605 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3606 3607 ctx = txq->ift_ctx; 3608 sctx = ctx->ifc_sctx; 3609 scctx = &ctx->ifc_softc_ctx; 3610 segs = txq->ift_segs; 3611 ntxd = txq->ift_size; 3612 m_head = *m_headp; 3613 map = NULL; 3614 3615 /* 3616 * If we're doing TSO the next descriptor to clean may be quite far ahead 3617 */ 3618 cidx = txq->ift_cidx; 3619 pidx = txq->ift_pidx; 3620 if (ctx->ifc_flags & IFC_PREFETCH) { 3621 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3622 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3623 next_txd = calc_next_txd(txq, cidx, 0); 3624 prefetch(next_txd); 3625 } 3626 3627 /* prefetch the next cache line of mbuf pointers and flags */ 3628 prefetch(&txq->ift_sds.ifsd_m[next]); 3629 prefetch(&txq->ift_sds.ifsd_map[next]); 3630 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3631 } 3632 map = txq->ift_sds.ifsd_map[pidx]; 3633 ifsd_m = txq->ift_sds.ifsd_m; 3634 3635 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3636 buf_tag = txq->ift_tso_buf_tag; 3637 max_segs = scctx->isc_tx_tso_segments_max; 3638 map = txq->ift_sds.ifsd_tso_map[pidx]; 3639 MPASS(buf_tag != NULL); 3640 MPASS(max_segs > 0); 3641 } else { 3642 buf_tag = txq->ift_buf_tag; 3643 max_segs = scctx->isc_tx_nsegments; 3644 map = txq->ift_sds.ifsd_map[pidx]; 3645 } 3646 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3647 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3648 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3649 if (err) { 3650 DBG_COUNTER_INC(encap_txd_encap_fail); 3651 return err; 3652 } 3653 } 3654 m_head = *m_headp; 3655 3656 pkt_info_zero(&pi); 3657 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3658 pi.ipi_pidx = pidx; 3659 pi.ipi_qsidx = txq->ift_id; 3660 pi.ipi_len = m_head->m_pkthdr.len; 3661 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3662 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3663 3664 /* deliberate bitwise OR to make one condition */ 3665 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3666 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3667 DBG_COUNTER_INC(encap_txd_encap_fail); 3668 return (err); 3669 } 3670 m_head = *m_headp; 3671 } 3672 3673 retry: 3674 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3675 BUS_DMA_NOWAIT); 3676 defrag: 3677 if (__predict_false(err)) { 3678 switch (err) { 3679 case EFBIG: 3680 /* try collapse once and defrag once */ 3681 if (remap == 0) { 3682 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3683 /* try defrag if collapsing fails */ 3684 if (m_head == NULL) 3685 remap++; 3686 } 3687 if (remap == 1) { 3688 txq->ift_mbuf_defrag++; 3689 m_head = m_defrag(*m_headp, M_NOWAIT); 3690 } 3691 /* 3692 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3693 * failed to map an mbuf that was run through m_defrag 3694 */ 3695 MPASS(remap <= 1); 3696 if (__predict_false(m_head == NULL || remap > 1)) 3697 goto defrag_failed; 3698 remap++; 3699 *m_headp = m_head; 3700 goto retry; 3701 break; 3702 case ENOMEM: 3703 txq->ift_no_tx_dma_setup++; 3704 break; 3705 default: 3706 txq->ift_no_tx_dma_setup++; 3707 m_freem(*m_headp); 3708 DBG_COUNTER_INC(tx_frees); 3709 *m_headp = NULL; 3710 break; 3711 } 3712 txq->ift_map_failed++; 3713 DBG_COUNTER_INC(encap_load_mbuf_fail); 3714 DBG_COUNTER_INC(encap_txd_encap_fail); 3715 return (err); 3716 } 3717 ifsd_m[pidx] = m_head; 3718 /* 3719 * XXX assumes a 1 to 1 relationship between segments and 3720 * descriptors - this does not hold true on all drivers, e.g. 3721 * cxgb 3722 */ 3723 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3724 txq->ift_no_desc_avail++; 3725 bus_dmamap_unload(buf_tag, map); 3726 DBG_COUNTER_INC(encap_txq_avail_fail); 3727 DBG_COUNTER_INC(encap_txd_encap_fail); 3728 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3729 GROUPTASK_ENQUEUE(&txq->ift_task); 3730 return (ENOBUFS); 3731 } 3732 /* 3733 * On Intel cards we can greatly reduce the number of TX interrupts 3734 * we see by only setting report status on every Nth descriptor. 3735 * However, this also means that the driver will need to keep track 3736 * of the descriptors that RS was set on to check them for the DD bit. 3737 */ 3738 txq->ift_rs_pending += nsegs + 1; 3739 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3740 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3741 pi.ipi_flags |= IPI_TX_INTR; 3742 txq->ift_rs_pending = 0; 3743 } 3744 3745 pi.ipi_segs = segs; 3746 pi.ipi_nsegs = nsegs; 3747 3748 MPASS(pidx >= 0 && pidx < txq->ift_size); 3749 #ifdef PKT_DEBUG 3750 print_pkt(&pi); 3751 #endif 3752 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3753 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3754 DBG_COUNTER_INC(tx_encap); 3755 MPASS(pi.ipi_new_pidx < txq->ift_size); 3756 3757 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3758 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3759 ndesc += txq->ift_size; 3760 txq->ift_gen = 1; 3761 } 3762 /* 3763 * drivers can need as many as 3764 * two sentinels 3765 */ 3766 MPASS(ndesc <= pi.ipi_nsegs + 2); 3767 MPASS(pi.ipi_new_pidx != pidx); 3768 MPASS(ndesc > 0); 3769 txq->ift_in_use += ndesc; 3770 txq->ift_db_pending += ndesc; 3771 3772 /* 3773 * We update the last software descriptor again here because there may 3774 * be a sentinel and/or there may be more mbufs than segments 3775 */ 3776 txq->ift_pidx = pi.ipi_new_pidx; 3777 txq->ift_npending += pi.ipi_ndescs; 3778 } else { 3779 *m_headp = m_head = iflib_remove_mbuf(txq); 3780 if (err == EFBIG) { 3781 txq->ift_txd_encap_efbig++; 3782 if (remap < 2) { 3783 remap = 1; 3784 goto defrag; 3785 } 3786 } 3787 goto defrag_failed; 3788 } 3789 /* 3790 * err can't possibly be non-zero here, so we don't neet to test it 3791 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3792 */ 3793 return (err); 3794 3795 defrag_failed: 3796 txq->ift_mbuf_defrag_failed++; 3797 txq->ift_map_failed++; 3798 m_freem(*m_headp); 3799 DBG_COUNTER_INC(tx_frees); 3800 *m_headp = NULL; 3801 DBG_COUNTER_INC(encap_txd_encap_fail); 3802 return (ENOMEM); 3803 } 3804 3805 static void 3806 iflib_tx_desc_free(iflib_txq_t txq, int n) 3807 { 3808 uint32_t qsize, cidx, mask, gen; 3809 struct mbuf *m, **ifsd_m; 3810 bool do_prefetch; 3811 3812 cidx = txq->ift_cidx; 3813 gen = txq->ift_gen; 3814 qsize = txq->ift_size; 3815 mask = qsize-1; 3816 ifsd_m = txq->ift_sds.ifsd_m; 3817 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3818 3819 while (n-- > 0) { 3820 if (do_prefetch) { 3821 prefetch(ifsd_m[(cidx + 3) & mask]); 3822 prefetch(ifsd_m[(cidx + 4) & mask]); 3823 } 3824 if ((m = ifsd_m[cidx]) != NULL) { 3825 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3826 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3827 bus_dmamap_sync(txq->ift_tso_buf_tag, 3828 txq->ift_sds.ifsd_tso_map[cidx], 3829 BUS_DMASYNC_POSTWRITE); 3830 bus_dmamap_unload(txq->ift_tso_buf_tag, 3831 txq->ift_sds.ifsd_tso_map[cidx]); 3832 } else { 3833 bus_dmamap_sync(txq->ift_buf_tag, 3834 txq->ift_sds.ifsd_map[cidx], 3835 BUS_DMASYNC_POSTWRITE); 3836 bus_dmamap_unload(txq->ift_buf_tag, 3837 txq->ift_sds.ifsd_map[cidx]); 3838 } 3839 /* XXX we don't support any drivers that batch packets yet */ 3840 MPASS(m->m_nextpkt == NULL); 3841 m_freem(m); 3842 ifsd_m[cidx] = NULL; 3843 #if MEMORY_LOGGING 3844 txq->ift_dequeued++; 3845 #endif 3846 DBG_COUNTER_INC(tx_frees); 3847 } 3848 if (__predict_false(++cidx == qsize)) { 3849 cidx = 0; 3850 gen = 0; 3851 } 3852 } 3853 txq->ift_cidx = cidx; 3854 txq->ift_gen = gen; 3855 } 3856 3857 static __inline int 3858 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3859 { 3860 int reclaim; 3861 if_ctx_t ctx = txq->ift_ctx; 3862 3863 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3864 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3865 3866 /* 3867 * Need a rate-limiting check so that this isn't called every time 3868 */ 3869 iflib_tx_credits_update(ctx, txq); 3870 reclaim = DESC_RECLAIMABLE(txq); 3871 3872 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3873 #ifdef INVARIANTS 3874 if (iflib_verbose_debug) { 3875 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3876 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3877 reclaim, thresh); 3878 } 3879 #endif 3880 return (0); 3881 } 3882 iflib_tx_desc_free(txq, reclaim); 3883 txq->ift_cleaned += reclaim; 3884 txq->ift_in_use -= reclaim; 3885 3886 return (reclaim); 3887 } 3888 3889 static struct mbuf ** 3890 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3891 { 3892 int next, size; 3893 struct mbuf **items; 3894 3895 size = r->size; 3896 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3897 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3898 3899 prefetch(items[(cidx + offset) & (size-1)]); 3900 if (remaining > 1) { 3901 prefetch2cachelines(&items[next]); 3902 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3903 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3904 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3905 } 3906 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3907 } 3908 3909 static void 3910 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3911 { 3912 3913 ifmp_ring_check_drainage(txq->ift_br, budget); 3914 } 3915 3916 static uint32_t 3917 iflib_txq_can_drain(struct ifmp_ring *r) 3918 { 3919 iflib_txq_t txq = r->cookie; 3920 if_ctx_t ctx = txq->ift_ctx; 3921 3922 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3923 return (1); 3924 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3925 BUS_DMASYNC_POSTREAD); 3926 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3927 false)); 3928 } 3929 3930 static uint32_t 3931 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3932 { 3933 iflib_txq_t txq = r->cookie; 3934 if_ctx_t ctx = txq->ift_ctx; 3935 if_t ifp = ctx->ifc_ifp; 3936 struct mbuf *m, **mp; 3937 int avail, bytes_sent, skipped, count, err, i; 3938 int mcast_sent, pkt_sent, reclaimed; 3939 bool do_prefetch, rang, ring; 3940 3941 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3942 !LINK_ACTIVE(ctx))) { 3943 DBG_COUNTER_INC(txq_drain_notready); 3944 return (0); 3945 } 3946 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3947 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3948 avail = IDXDIFF(pidx, cidx, r->size); 3949 3950 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3951 /* 3952 * The driver is unloading so we need to free all pending packets. 3953 */ 3954 DBG_COUNTER_INC(txq_drain_flushing); 3955 for (i = 0; i < avail; i++) { 3956 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3957 m_freem(r->items[(cidx + i) & (r->size-1)]); 3958 r->items[(cidx + i) & (r->size-1)] = NULL; 3959 } 3960 return (avail); 3961 } 3962 3963 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3964 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3965 CALLOUT_LOCK(txq); 3966 callout_stop(&txq->ift_timer); 3967 CALLOUT_UNLOCK(txq); 3968 DBG_COUNTER_INC(txq_drain_oactive); 3969 return (0); 3970 } 3971 3972 /* 3973 * If we've reclaimed any packets this queue cannot be hung. 3974 */ 3975 if (reclaimed) 3976 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3977 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3978 count = MIN(avail, TX_BATCH_SIZE); 3979 #ifdef INVARIANTS 3980 if (iflib_verbose_debug) 3981 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3982 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3983 #endif 3984 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3985 err = 0; 3986 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3987 int rem = do_prefetch ? count - i : 0; 3988 3989 mp = _ring_peek_one(r, cidx, i, rem); 3990 MPASS(mp != NULL && *mp != NULL); 3991 3992 /* 3993 * Completion interrupts will use the address of the txq 3994 * as a sentinel to enqueue _something_ in order to acquire 3995 * the lock on the mp_ring (there's no direct lock call). 3996 * We obviously whave to check for these sentinel cases 3997 * and skip them. 3998 */ 3999 if (__predict_false(*mp == (struct mbuf *)txq)) { 4000 skipped++; 4001 continue; 4002 } 4003 err = iflib_encap(txq, mp); 4004 if (__predict_false(err)) { 4005 /* no room - bail out */ 4006 if (err == ENOBUFS) 4007 break; 4008 skipped++; 4009 /* we can't send this packet - skip it */ 4010 continue; 4011 } 4012 pkt_sent++; 4013 m = *mp; 4014 DBG_COUNTER_INC(tx_sent); 4015 bytes_sent += m->m_pkthdr.len; 4016 mcast_sent += !!(m->m_flags & M_MCAST); 4017 4018 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))) 4019 break; 4020 ETHER_BPF_MTAP(ifp, m); 4021 rang = iflib_txd_db_check(txq, false); 4022 } 4023 4024 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 4025 ring = rang ? false : (iflib_min_tx_latency | err); 4026 iflib_txd_db_check(txq, ring); 4027 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 4028 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 4029 if (mcast_sent) 4030 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 4031 #ifdef INVARIANTS 4032 if (iflib_verbose_debug) 4033 printf("consumed=%d\n", skipped + pkt_sent); 4034 #endif 4035 return (skipped + pkt_sent); 4036 } 4037 4038 static uint32_t 4039 iflib_txq_drain_always(struct ifmp_ring *r) 4040 { 4041 return (1); 4042 } 4043 4044 static uint32_t 4045 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 4046 { 4047 int i, avail; 4048 struct mbuf **mp; 4049 iflib_txq_t txq; 4050 4051 txq = r->cookie; 4052 4053 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 4054 CALLOUT_LOCK(txq); 4055 callout_stop(&txq->ift_timer); 4056 CALLOUT_UNLOCK(txq); 4057 4058 avail = IDXDIFF(pidx, cidx, r->size); 4059 for (i = 0; i < avail; i++) { 4060 mp = _ring_peek_one(r, cidx, i, avail - i); 4061 if (__predict_false(*mp == (struct mbuf *)txq)) 4062 continue; 4063 m_freem(*mp); 4064 DBG_COUNTER_INC(tx_frees); 4065 } 4066 MPASS(ifmp_ring_is_stalled(r) == 0); 4067 return (avail); 4068 } 4069 4070 static void 4071 iflib_ifmp_purge(iflib_txq_t txq) 4072 { 4073 struct ifmp_ring *r; 4074 4075 r = txq->ift_br; 4076 r->drain = iflib_txq_drain_free; 4077 r->can_drain = iflib_txq_drain_always; 4078 4079 ifmp_ring_check_drainage(r, r->size); 4080 4081 r->drain = iflib_txq_drain; 4082 r->can_drain = iflib_txq_can_drain; 4083 } 4084 4085 static void 4086 _task_fn_tx(void *context) 4087 { 4088 iflib_txq_t txq = context; 4089 if_ctx_t ctx = txq->ift_ctx; 4090 if_t ifp = ctx->ifc_ifp; 4091 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4092 4093 #ifdef IFLIB_DIAGNOSTICS 4094 txq->ift_cpu_exec_count[curcpu]++; 4095 #endif 4096 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4097 return; 4098 #ifdef DEV_NETMAP 4099 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 4100 netmap_tx_irq(ifp, txq->ift_id)) 4101 goto skip_ifmp; 4102 #endif 4103 #ifdef ALTQ 4104 if (if_altq_is_enabled(ifp)) 4105 iflib_altq_if_start(ifp); 4106 #endif 4107 if (txq->ift_db_pending) 4108 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 4109 else if (!abdicate) 4110 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4111 /* 4112 * When abdicating, we always need to check drainage, not just when we don't enqueue 4113 */ 4114 if (abdicate) 4115 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4116 #ifdef DEV_NETMAP 4117 skip_ifmp: 4118 #endif 4119 if (ctx->ifc_flags & IFC_LEGACY) 4120 IFDI_INTR_ENABLE(ctx); 4121 else 4122 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 4123 } 4124 4125 static void 4126 _task_fn_rx(void *context) 4127 { 4128 iflib_rxq_t rxq = context; 4129 if_ctx_t ctx = rxq->ifr_ctx; 4130 uint8_t more; 4131 uint16_t budget; 4132 #ifdef DEV_NETMAP 4133 u_int work = 0; 4134 int nmirq; 4135 #endif 4136 4137 #ifdef IFLIB_DIAGNOSTICS 4138 rxq->ifr_cpu_exec_count[curcpu]++; 4139 #endif 4140 DBG_COUNTER_INC(task_fn_rxs); 4141 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4142 return; 4143 #ifdef DEV_NETMAP 4144 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4145 if (nmirq != NM_IRQ_PASS) { 4146 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4147 goto skip_rxeof; 4148 } 4149 #endif 4150 budget = ctx->ifc_sysctl_rx_budget; 4151 if (budget == 0) 4152 budget = 16; /* XXX */ 4153 more = iflib_rxeof(rxq, budget); 4154 #ifdef DEV_NETMAP 4155 skip_rxeof: 4156 #endif 4157 if ((more & IFLIB_RXEOF_MORE) == 0) { 4158 if (ctx->ifc_flags & IFC_LEGACY) 4159 IFDI_INTR_ENABLE(ctx); 4160 else 4161 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4162 DBG_COUNTER_INC(rx_intr_enables); 4163 } 4164 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4165 return; 4166 4167 if (more & IFLIB_RXEOF_MORE) 4168 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4169 else if (more & IFLIB_RXEOF_EMPTY) 4170 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4171 } 4172 4173 static void 4174 _task_fn_admin(void *context) 4175 { 4176 if_ctx_t ctx = context; 4177 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4178 iflib_txq_t txq; 4179 int i; 4180 bool oactive, running, do_reset, do_watchdog, in_detach; 4181 4182 STATE_LOCK(ctx); 4183 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4184 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4185 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4186 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4187 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4188 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 4189 STATE_UNLOCK(ctx); 4190 4191 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4192 return; 4193 if (in_detach) 4194 return; 4195 4196 CTX_LOCK(ctx); 4197 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4198 CALLOUT_LOCK(txq); 4199 callout_stop(&txq->ift_timer); 4200 CALLOUT_UNLOCK(txq); 4201 } 4202 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4203 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4204 if (do_watchdog) { 4205 ctx->ifc_watchdog_events++; 4206 IFDI_WATCHDOG_RESET(ctx); 4207 } 4208 IFDI_UPDATE_ADMIN_STATUS(ctx); 4209 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4210 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4211 txq->ift_timer.c_cpu); 4212 } 4213 IFDI_LINK_INTR_ENABLE(ctx); 4214 if (do_reset) 4215 iflib_if_init_locked(ctx); 4216 CTX_UNLOCK(ctx); 4217 4218 if (LINK_ACTIVE(ctx) == 0) 4219 return; 4220 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4221 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4222 } 4223 4224 static void 4225 _task_fn_iov(void *context) 4226 { 4227 if_ctx_t ctx = context; 4228 4229 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4230 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4231 return; 4232 4233 CTX_LOCK(ctx); 4234 IFDI_VFLR_HANDLE(ctx); 4235 CTX_UNLOCK(ctx); 4236 } 4237 4238 static int 4239 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4240 { 4241 int err; 4242 if_int_delay_info_t info; 4243 if_ctx_t ctx; 4244 4245 info = (if_int_delay_info_t)arg1; 4246 ctx = info->iidi_ctx; 4247 info->iidi_req = req; 4248 info->iidi_oidp = oidp; 4249 CTX_LOCK(ctx); 4250 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4251 CTX_UNLOCK(ctx); 4252 return (err); 4253 } 4254 4255 /********************************************************************* 4256 * 4257 * IFNET FUNCTIONS 4258 * 4259 **********************************************************************/ 4260 4261 static void 4262 iflib_if_init_locked(if_ctx_t ctx) 4263 { 4264 iflib_stop(ctx); 4265 iflib_init_locked(ctx); 4266 } 4267 4268 static void 4269 iflib_if_init(void *arg) 4270 { 4271 if_ctx_t ctx = arg; 4272 4273 CTX_LOCK(ctx); 4274 iflib_if_init_locked(ctx); 4275 CTX_UNLOCK(ctx); 4276 } 4277 4278 static int 4279 iflib_if_transmit(if_t ifp, struct mbuf *m) 4280 { 4281 if_ctx_t ctx = if_getsoftc(ifp); 4282 iflib_txq_t txq; 4283 int err, qidx; 4284 int abdicate; 4285 4286 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4287 DBG_COUNTER_INC(tx_frees); 4288 m_freem(m); 4289 return (ENETDOWN); 4290 } 4291 4292 MPASS(m->m_nextpkt == NULL); 4293 /* ALTQ-enabled interfaces always use queue 0. */ 4294 qidx = 0; 4295 /* Use driver-supplied queue selection method if it exists */ 4296 if (ctx->isc_txq_select_v2) { 4297 struct if_pkt_info pi; 4298 uint64_t early_pullups = 0; 4299 pkt_info_zero(&pi); 4300 4301 err = iflib_parse_header_partial(&pi, &m, &early_pullups); 4302 if (__predict_false(err != 0)) { 4303 /* Assign pullups for bad pkts to default queue */ 4304 ctx->ifc_txqs[0].ift_pullups += early_pullups; 4305 DBG_COUNTER_INC(encap_txd_encap_fail); 4306 return (err); 4307 } 4308 /* Let driver make queueing decision */ 4309 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi); 4310 ctx->ifc_txqs[qidx].ift_pullups += early_pullups; 4311 } 4312 /* Backwards compatibility w/ simpler queue select */ 4313 else if (ctx->isc_txq_select) 4314 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4315 /* If not, use iflib's standard method */ 4316 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp)) 4317 qidx = QIDX(ctx, m); 4318 4319 /* Set TX queue */ 4320 txq = &ctx->ifc_txqs[qidx]; 4321 4322 #ifdef DRIVER_BACKPRESSURE 4323 if (txq->ift_closed) { 4324 while (m != NULL) { 4325 next = m->m_nextpkt; 4326 m->m_nextpkt = NULL; 4327 m_freem(m); 4328 DBG_COUNTER_INC(tx_frees); 4329 m = next; 4330 } 4331 return (ENOBUFS); 4332 } 4333 #endif 4334 #ifdef notyet 4335 qidx = count = 0; 4336 mp = marr; 4337 next = m; 4338 do { 4339 count++; 4340 next = next->m_nextpkt; 4341 } while (next != NULL); 4342 4343 if (count > nitems(marr)) 4344 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4345 /* XXX check nextpkt */ 4346 m_freem(m); 4347 /* XXX simplify for now */ 4348 DBG_COUNTER_INC(tx_frees); 4349 return (ENOBUFS); 4350 } 4351 for (next = m, i = 0; next != NULL; i++) { 4352 mp[i] = next; 4353 next = next->m_nextpkt; 4354 mp[i]->m_nextpkt = NULL; 4355 } 4356 #endif 4357 DBG_COUNTER_INC(tx_seen); 4358 abdicate = ctx->ifc_sysctl_tx_abdicate; 4359 4360 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4361 4362 if (abdicate) 4363 GROUPTASK_ENQUEUE(&txq->ift_task); 4364 if (err) { 4365 if (!abdicate) 4366 GROUPTASK_ENQUEUE(&txq->ift_task); 4367 /* support forthcoming later */ 4368 #ifdef DRIVER_BACKPRESSURE 4369 txq->ift_closed = TRUE; 4370 #endif 4371 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4372 m_freem(m); 4373 DBG_COUNTER_INC(tx_frees); 4374 } 4375 4376 return (err); 4377 } 4378 4379 #ifdef ALTQ 4380 /* 4381 * The overall approach to integrating iflib with ALTQ is to continue to use 4382 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4383 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4384 * is redundant/unnecessary, but doing so minimizes the amount of 4385 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4386 * redundantly queueing to an intermediate mp_ring is swamped by the 4387 * performance limitations inherent in using ALTQ. 4388 * 4389 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4390 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4391 * given interface. If ALTQ is enabled for an interface, then all 4392 * transmitted packets for that interface will be submitted to the ALTQ 4393 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4394 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4395 * update stats that the iflib machinery handles, and which is sensitve to 4396 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4397 * will be installed as the start routine for use by ALTQ facilities that 4398 * need to trigger queue drains on a scheduled basis. 4399 * 4400 */ 4401 static void 4402 iflib_altq_if_start(if_t ifp) 4403 { 4404 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */ 4405 struct mbuf *m; 4406 4407 IFQ_LOCK(ifq); 4408 IFQ_DEQUEUE_NOLOCK(ifq, m); 4409 while (m != NULL) { 4410 iflib_if_transmit(ifp, m); 4411 IFQ_DEQUEUE_NOLOCK(ifq, m); 4412 } 4413 IFQ_UNLOCK(ifq); 4414 } 4415 4416 static int 4417 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4418 { 4419 int err; 4420 4421 if (if_altq_is_enabled(ifp)) { 4422 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */ 4423 if (err == 0) 4424 iflib_altq_if_start(ifp); 4425 } else 4426 err = iflib_if_transmit(ifp, m); 4427 4428 return (err); 4429 } 4430 #endif /* ALTQ */ 4431 4432 static void 4433 iflib_if_qflush(if_t ifp) 4434 { 4435 if_ctx_t ctx = if_getsoftc(ifp); 4436 iflib_txq_t txq = ctx->ifc_txqs; 4437 int i; 4438 4439 STATE_LOCK(ctx); 4440 ctx->ifc_flags |= IFC_QFLUSH; 4441 STATE_UNLOCK(ctx); 4442 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4443 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4444 iflib_txq_check_drain(txq, 0); 4445 STATE_LOCK(ctx); 4446 ctx->ifc_flags &= ~IFC_QFLUSH; 4447 STATE_UNLOCK(ctx); 4448 4449 /* 4450 * When ALTQ is enabled, this will also take care of purging the 4451 * ALTQ queue(s). 4452 */ 4453 if_qflush(ifp); 4454 } 4455 4456 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4457 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4458 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4459 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4460 4461 static int 4462 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4463 { 4464 if_ctx_t ctx = if_getsoftc(ifp); 4465 struct ifreq *ifr = (struct ifreq *)data; 4466 #if defined(INET) || defined(INET6) 4467 struct ifaddr *ifa = (struct ifaddr *)data; 4468 #endif 4469 bool avoid_reset = false; 4470 int err = 0, reinit = 0, bits; 4471 4472 switch (command) { 4473 case SIOCSIFADDR: 4474 #ifdef INET 4475 if (ifa->ifa_addr->sa_family == AF_INET) 4476 avoid_reset = true; 4477 #endif 4478 #ifdef INET6 4479 if (ifa->ifa_addr->sa_family == AF_INET6) 4480 avoid_reset = true; 4481 #endif 4482 /* 4483 ** Calling init results in link renegotiation, 4484 ** so we avoid doing it when possible. 4485 */ 4486 if (avoid_reset) { 4487 if_setflagbits(ifp, IFF_UP,0); 4488 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4489 reinit = 1; 4490 #ifdef INET 4491 if (!(if_getflags(ifp) & IFF_NOARP)) 4492 arp_ifinit(ifp, ifa); 4493 #endif 4494 } else 4495 err = ether_ioctl(ifp, command, data); 4496 break; 4497 case SIOCSIFMTU: 4498 CTX_LOCK(ctx); 4499 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4500 CTX_UNLOCK(ctx); 4501 break; 4502 } 4503 bits = if_getdrvflags(ifp); 4504 /* stop the driver and free any clusters before proceeding */ 4505 iflib_stop(ctx); 4506 4507 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4508 STATE_LOCK(ctx); 4509 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4510 ctx->ifc_flags |= IFC_MULTISEG; 4511 else 4512 ctx->ifc_flags &= ~IFC_MULTISEG; 4513 STATE_UNLOCK(ctx); 4514 err = if_setmtu(ifp, ifr->ifr_mtu); 4515 } 4516 iflib_init_locked(ctx); 4517 STATE_LOCK(ctx); 4518 if_setdrvflags(ifp, bits); 4519 STATE_UNLOCK(ctx); 4520 CTX_UNLOCK(ctx); 4521 break; 4522 case SIOCSIFFLAGS: 4523 CTX_LOCK(ctx); 4524 if (if_getflags(ifp) & IFF_UP) { 4525 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4526 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4527 (IFF_PROMISC | IFF_ALLMULTI)) { 4528 CTX_UNLOCK(ctx); 4529 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4530 CTX_LOCK(ctx); 4531 } 4532 } else 4533 reinit = 1; 4534 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4535 iflib_stop(ctx); 4536 } 4537 ctx->ifc_if_flags = if_getflags(ifp); 4538 CTX_UNLOCK(ctx); 4539 break; 4540 case SIOCADDMULTI: 4541 case SIOCDELMULTI: 4542 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4543 CTX_LOCK(ctx); 4544 IFDI_INTR_DISABLE(ctx); 4545 IFDI_MULTI_SET(ctx); 4546 IFDI_INTR_ENABLE(ctx); 4547 CTX_UNLOCK(ctx); 4548 } 4549 break; 4550 case SIOCSIFMEDIA: 4551 CTX_LOCK(ctx); 4552 IFDI_MEDIA_SET(ctx); 4553 CTX_UNLOCK(ctx); 4554 /* FALLTHROUGH */ 4555 case SIOCGIFMEDIA: 4556 case SIOCGIFXMEDIA: 4557 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4558 break; 4559 case SIOCGI2C: 4560 { 4561 struct ifi2creq i2c; 4562 4563 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4564 if (err != 0) 4565 break; 4566 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4567 err = EINVAL; 4568 break; 4569 } 4570 if (i2c.len > sizeof(i2c.data)) { 4571 err = EINVAL; 4572 break; 4573 } 4574 4575 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4576 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4577 sizeof(i2c)); 4578 break; 4579 } 4580 case SIOCSIFCAP: 4581 { 4582 int mask, setmask, oldmask; 4583 4584 oldmask = if_getcapenable(ifp); 4585 mask = ifr->ifr_reqcap ^ oldmask; 4586 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4587 setmask = 0; 4588 #ifdef TCP_OFFLOAD 4589 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4590 #endif 4591 setmask |= (mask & IFCAP_FLAGS); 4592 setmask |= (mask & IFCAP_WOL); 4593 4594 /* 4595 * If any RX csum has changed, change all the ones that 4596 * are supported by the driver. 4597 */ 4598 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4599 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4600 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4601 } 4602 4603 /* 4604 * want to ensure that traffic has stopped before we change any of the flags 4605 */ 4606 if (setmask) { 4607 CTX_LOCK(ctx); 4608 bits = if_getdrvflags(ifp); 4609 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4610 iflib_stop(ctx); 4611 STATE_LOCK(ctx); 4612 if_togglecapenable(ifp, setmask); 4613 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4614 STATE_UNLOCK(ctx); 4615 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4616 iflib_init_locked(ctx); 4617 STATE_LOCK(ctx); 4618 if_setdrvflags(ifp, bits); 4619 STATE_UNLOCK(ctx); 4620 CTX_UNLOCK(ctx); 4621 } 4622 if_vlancap(ifp); 4623 break; 4624 } 4625 case SIOCGPRIVATE_0: 4626 case SIOCSDRVSPEC: 4627 case SIOCGDRVSPEC: 4628 CTX_LOCK(ctx); 4629 err = IFDI_PRIV_IOCTL(ctx, command, data); 4630 CTX_UNLOCK(ctx); 4631 break; 4632 default: 4633 err = ether_ioctl(ifp, command, data); 4634 break; 4635 } 4636 if (reinit) 4637 iflib_if_init(ctx); 4638 return (err); 4639 } 4640 4641 static uint64_t 4642 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4643 { 4644 if_ctx_t ctx = if_getsoftc(ifp); 4645 4646 return (IFDI_GET_COUNTER(ctx, cnt)); 4647 } 4648 4649 /********************************************************************* 4650 * 4651 * OTHER FUNCTIONS EXPORTED TO THE STACK 4652 * 4653 **********************************************************************/ 4654 4655 static void 4656 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4657 { 4658 if_ctx_t ctx = if_getsoftc(ifp); 4659 4660 if ((void *)ctx != arg) 4661 return; 4662 4663 if ((vtag == 0) || (vtag > 4095)) 4664 return; 4665 4666 if (iflib_in_detach(ctx)) 4667 return; 4668 4669 CTX_LOCK(ctx); 4670 /* Driver may need all untagged packets to be flushed */ 4671 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4672 iflib_stop(ctx); 4673 IFDI_VLAN_REGISTER(ctx, vtag); 4674 /* Re-init to load the changes, if required */ 4675 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4676 iflib_init_locked(ctx); 4677 CTX_UNLOCK(ctx); 4678 } 4679 4680 static void 4681 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4682 { 4683 if_ctx_t ctx = if_getsoftc(ifp); 4684 4685 if ((void *)ctx != arg) 4686 return; 4687 4688 if ((vtag == 0) || (vtag > 4095)) 4689 return; 4690 4691 CTX_LOCK(ctx); 4692 /* Driver may need all tagged packets to be flushed */ 4693 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4694 iflib_stop(ctx); 4695 IFDI_VLAN_UNREGISTER(ctx, vtag); 4696 /* Re-init to load the changes, if required */ 4697 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4698 iflib_init_locked(ctx); 4699 CTX_UNLOCK(ctx); 4700 } 4701 4702 static void 4703 iflib_led_func(void *arg, int onoff) 4704 { 4705 if_ctx_t ctx = arg; 4706 4707 CTX_LOCK(ctx); 4708 IFDI_LED_FUNC(ctx, onoff); 4709 CTX_UNLOCK(ctx); 4710 } 4711 4712 /********************************************************************* 4713 * 4714 * BUS FUNCTION DEFINITIONS 4715 * 4716 **********************************************************************/ 4717 4718 int 4719 iflib_device_probe(device_t dev) 4720 { 4721 const pci_vendor_info_t *ent; 4722 if_shared_ctx_t sctx; 4723 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4724 uint16_t pci_vendor_id; 4725 4726 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4727 return (ENOTSUP); 4728 4729 pci_vendor_id = pci_get_vendor(dev); 4730 pci_device_id = pci_get_device(dev); 4731 pci_subvendor_id = pci_get_subvendor(dev); 4732 pci_subdevice_id = pci_get_subdevice(dev); 4733 pci_rev_id = pci_get_revid(dev); 4734 if (sctx->isc_parse_devinfo != NULL) 4735 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4736 4737 ent = sctx->isc_vendor_info; 4738 while (ent->pvi_vendor_id != 0) { 4739 if (pci_vendor_id != ent->pvi_vendor_id) { 4740 ent++; 4741 continue; 4742 } 4743 if ((pci_device_id == ent->pvi_device_id) && 4744 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4745 (ent->pvi_subvendor_id == 0)) && 4746 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4747 (ent->pvi_subdevice_id == 0)) && 4748 ((pci_rev_id == ent->pvi_rev_id) || 4749 (ent->pvi_rev_id == 0))) { 4750 device_set_desc_copy(dev, ent->pvi_name); 4751 /* this needs to be changed to zero if the bus probing code 4752 * ever stops re-probing on best match because the sctx 4753 * may have its values over written by register calls 4754 * in subsequent probes 4755 */ 4756 return (BUS_PROBE_DEFAULT); 4757 } 4758 ent++; 4759 } 4760 return (ENXIO); 4761 } 4762 4763 int 4764 iflib_device_probe_vendor(device_t dev) 4765 { 4766 int probe; 4767 4768 probe = iflib_device_probe(dev); 4769 if (probe == BUS_PROBE_DEFAULT) 4770 return (BUS_PROBE_VENDOR); 4771 else 4772 return (probe); 4773 } 4774 4775 static void 4776 iflib_reset_qvalues(if_ctx_t ctx) 4777 { 4778 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4779 if_shared_ctx_t sctx = ctx->ifc_sctx; 4780 device_t dev = ctx->ifc_dev; 4781 int i; 4782 4783 if (ctx->ifc_sysctl_ntxqs != 0) 4784 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4785 if (ctx->ifc_sysctl_nrxqs != 0) 4786 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4787 4788 for (i = 0; i < sctx->isc_ntxqs; i++) { 4789 if (ctx->ifc_sysctl_ntxds[i] != 0) 4790 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4791 else 4792 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4793 } 4794 4795 for (i = 0; i < sctx->isc_nrxqs; i++) { 4796 if (ctx->ifc_sysctl_nrxds[i] != 0) 4797 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4798 else 4799 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4800 } 4801 4802 for (i = 0; i < sctx->isc_nrxqs; i++) { 4803 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4804 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4805 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4806 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4807 } 4808 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4809 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4810 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4811 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4812 } 4813 if (!powerof2(scctx->isc_nrxd[i])) { 4814 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4815 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4816 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4817 } 4818 } 4819 4820 for (i = 0; i < sctx->isc_ntxqs; i++) { 4821 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4822 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4823 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4824 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4825 } 4826 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4827 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4828 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4829 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4830 } 4831 if (!powerof2(scctx->isc_ntxd[i])) { 4832 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4833 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4834 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4835 } 4836 } 4837 } 4838 4839 static void 4840 iflib_add_pfil(if_ctx_t ctx) 4841 { 4842 struct pfil_head *pfil; 4843 struct pfil_head_args pa; 4844 iflib_rxq_t rxq; 4845 int i; 4846 4847 pa.pa_version = PFIL_VERSION; 4848 pa.pa_flags = PFIL_IN; 4849 pa.pa_type = PFIL_TYPE_ETHERNET; 4850 pa.pa_headname = if_name(ctx->ifc_ifp); 4851 pfil = pfil_head_register(&pa); 4852 4853 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4854 rxq->pfil = pfil; 4855 } 4856 } 4857 4858 static void 4859 iflib_rem_pfil(if_ctx_t ctx) 4860 { 4861 struct pfil_head *pfil; 4862 iflib_rxq_t rxq; 4863 int i; 4864 4865 rxq = ctx->ifc_rxqs; 4866 pfil = rxq->pfil; 4867 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4868 rxq->pfil = NULL; 4869 } 4870 pfil_head_unregister(pfil); 4871 } 4872 4873 4874 /* 4875 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4876 * cpuid and wrapping as necessary. 4877 */ 4878 static unsigned int 4879 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4880 { 4881 unsigned int first_valid; 4882 unsigned int last_valid; 4883 4884 /* cpuid should always be in the valid set */ 4885 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4886 4887 /* valid set should never be empty */ 4888 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4889 4890 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4891 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4892 n = n % CPU_COUNT(&ctx->ifc_cpus); 4893 while (n > 0) { 4894 do { 4895 cpuid++; 4896 if (cpuid > last_valid) 4897 cpuid = first_valid; 4898 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4899 n--; 4900 } 4901 4902 return (cpuid); 4903 } 4904 4905 #if defined(SMP) && defined(SCHED_ULE) 4906 extern struct cpu_group *cpu_top; /* CPU topology */ 4907 4908 static int 4909 find_child_with_core(int cpu, struct cpu_group *grp) 4910 { 4911 int i; 4912 4913 if (grp->cg_children == 0) 4914 return -1; 4915 4916 MPASS(grp->cg_child); 4917 for (i = 0; i < grp->cg_children; i++) { 4918 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4919 return i; 4920 } 4921 4922 return -1; 4923 } 4924 4925 4926 /* 4927 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4928 * does not distinguish among multiple L2 neighbors if the given CPU has 4929 * more than one (it will always return the same result in that case). 4930 */ 4931 static int 4932 find_l2_neighbor(int cpu) 4933 { 4934 struct cpu_group *grp; 4935 int i; 4936 4937 grp = cpu_top; 4938 if (grp == NULL) 4939 return -1; 4940 4941 /* 4942 * Find the smallest CPU group that contains the given core. 4943 */ 4944 i = 0; 4945 while ((i = find_child_with_core(cpu, grp)) != -1) { 4946 /* 4947 * If the smallest group containing the given CPU has less 4948 * than two members, we conclude the given CPU has no 4949 * L2 neighbor. 4950 */ 4951 if (grp->cg_child[i].cg_count <= 1) 4952 return (-1); 4953 grp = &grp->cg_child[i]; 4954 } 4955 4956 /* Must share L2. */ 4957 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4958 return -1; 4959 4960 /* 4961 * Select the first member of the set that isn't the reference 4962 * CPU, which at this point is guaranteed to exist. 4963 */ 4964 for (i = 0; i < CPU_SETSIZE; i++) { 4965 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4966 return (i); 4967 } 4968 4969 /* Should never be reached */ 4970 return (-1); 4971 } 4972 4973 #else 4974 static int 4975 find_l2_neighbor(int cpu) 4976 { 4977 4978 return (-1); 4979 } 4980 #endif 4981 4982 /* 4983 * CPU mapping behaviors 4984 * --------------------- 4985 * 'separate txrx' refers to the separate_txrx sysctl 4986 * 'use logical' refers to the use_logical_cores sysctl 4987 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4988 * 4989 * separate use INTR 4990 * txrx logical CPUS result 4991 * ---------- --------- ------ ------------------------------------------------ 4992 * - - X RX and TX queues mapped to consecutive physical 4993 * cores with RX/TX pairs on same core and excess 4994 * of either following 4995 * - X X RX and TX queues mapped to consecutive cores 4996 * of any type with RX/TX pairs on same core and 4997 * excess of either following 4998 * X - X RX and TX queues mapped to consecutive physical 4999 * cores; all RX then all TX 5000 * X X X RX queues mapped to consecutive physical cores 5001 * first, then TX queues mapped to L2 neighbor of 5002 * the corresponding RX queue if one exists, 5003 * otherwise to consecutive physical cores 5004 * - n/a - RX and TX queues mapped to consecutive cores of 5005 * any type with RX/TX pairs on same core and excess 5006 * of either following 5007 * X n/a - RX and TX queues mapped to consecutive cores of 5008 * any type; all RX then all TX 5009 */ 5010 static unsigned int 5011 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 5012 bool is_tx) 5013 { 5014 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5015 unsigned int core_index; 5016 5017 if (ctx->ifc_sysctl_separate_txrx) { 5018 /* 5019 * When using separate CPUs for TX and RX, the assignment 5020 * will always be of a consecutive CPU out of the set of 5021 * context CPUs, except for the specific case where the 5022 * context CPUs are phsyical cores, the use of logical cores 5023 * has been enabled, the assignment is for TX, the TX qid 5024 * corresponds to an RX qid, and the CPU assigned to the 5025 * corresponding RX queue has an L2 neighbor. 5026 */ 5027 if (ctx->ifc_sysctl_use_logical_cores && 5028 ctx->ifc_cpus_are_physical_cores && 5029 is_tx && qid < scctx->isc_nrxqsets) { 5030 int l2_neighbor; 5031 unsigned int rx_cpuid; 5032 5033 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 5034 l2_neighbor = find_l2_neighbor(rx_cpuid); 5035 if (l2_neighbor != -1) { 5036 return (l2_neighbor); 5037 } 5038 /* 5039 * ... else fall through to the normal 5040 * consecutive-after-RX assignment scheme. 5041 * 5042 * Note that we are assuming that all RX queue CPUs 5043 * have an L2 neighbor, or all do not. If a mixed 5044 * scenario is possible, we will have to keep track 5045 * separately of how many queues prior to this one 5046 * were not able to be assigned to an L2 neighbor. 5047 */ 5048 } 5049 if (is_tx) 5050 core_index = scctx->isc_nrxqsets + qid; 5051 else 5052 core_index = qid; 5053 } else { 5054 core_index = qid; 5055 } 5056 5057 return (cpuid_advance(ctx, base_cpuid, core_index)); 5058 } 5059 5060 static uint16_t 5061 get_ctx_core_offset(if_ctx_t ctx) 5062 { 5063 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5064 struct cpu_offset *op; 5065 cpuset_t assigned_cpus; 5066 unsigned int cores_consumed; 5067 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 5068 unsigned int first_valid; 5069 unsigned int last_valid; 5070 unsigned int i; 5071 5072 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 5073 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 5074 5075 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 5076 /* 5077 * Align the user-chosen base CPU ID to the next valid CPU 5078 * for this device. If the chosen base CPU ID is smaller 5079 * than the first valid CPU or larger than the last valid 5080 * CPU, we assume the user does not know what the valid 5081 * range is for this device and is thinking in terms of a 5082 * zero-based reference frame, and so we shift the given 5083 * value into the valid range (and wrap accordingly) so the 5084 * intent is translated to the proper frame of reference. 5085 * If the base CPU ID is within the valid first/last, but 5086 * does not correspond to a valid CPU, it is advanced to the 5087 * next valid CPU (wrapping if necessary). 5088 */ 5089 if (base_cpuid < first_valid || base_cpuid > last_valid) { 5090 /* shift from zero-based to first_valid-based */ 5091 base_cpuid += first_valid; 5092 /* wrap to range [first_valid, last_valid] */ 5093 base_cpuid = (base_cpuid - first_valid) % 5094 (last_valid - first_valid + 1); 5095 } 5096 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 5097 /* 5098 * base_cpuid is in [first_valid, last_valid], but 5099 * not a member of the valid set. In this case, 5100 * there will always be a member of the valid set 5101 * with a CPU ID that is greater than base_cpuid, 5102 * and we simply advance to it. 5103 */ 5104 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 5105 base_cpuid++; 5106 } 5107 return (base_cpuid); 5108 } 5109 5110 /* 5111 * Determine how many cores will be consumed by performing the CPU 5112 * assignments and counting how many of the assigned CPUs correspond 5113 * to CPUs in the set of context CPUs. This is done using the CPU 5114 * ID first_valid as the base CPU ID, as the base CPU must be within 5115 * the set of context CPUs. 5116 * 5117 * Note not all assigned CPUs will be in the set of context CPUs 5118 * when separate CPUs are being allocated to TX and RX queues, 5119 * assignment to logical cores has been enabled, the set of context 5120 * CPUs contains only physical CPUs, and TX queues are mapped to L2 5121 * neighbors of CPUs that RX queues have been mapped to - in this 5122 * case we do only want to count how many CPUs in the set of context 5123 * CPUs have been consumed, as that determines the next CPU in that 5124 * set to start allocating at for the next device for which 5125 * core_offset is not set. 5126 */ 5127 CPU_ZERO(&assigned_cpus); 5128 for (i = 0; i < scctx->isc_ntxqsets; i++) 5129 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 5130 &assigned_cpus); 5131 for (i = 0; i < scctx->isc_nrxqsets; i++) 5132 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 5133 &assigned_cpus); 5134 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 5135 cores_consumed = CPU_COUNT(&assigned_cpus); 5136 5137 mtx_lock(&cpu_offset_mtx); 5138 SLIST_FOREACH(op, &cpu_offsets, entries) { 5139 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5140 base_cpuid = op->next_cpuid; 5141 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 5142 cores_consumed); 5143 MPASS(op->refcount < UINT_MAX); 5144 op->refcount++; 5145 break; 5146 } 5147 } 5148 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 5149 base_cpuid = first_valid; 5150 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 5151 M_NOWAIT | M_ZERO); 5152 if (op == NULL) { 5153 device_printf(ctx->ifc_dev, 5154 "allocation for cpu offset failed.\n"); 5155 } else { 5156 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5157 cores_consumed); 5158 op->refcount = 1; 5159 CPU_COPY(&ctx->ifc_cpus, &op->set); 5160 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5161 } 5162 } 5163 mtx_unlock(&cpu_offset_mtx); 5164 5165 return (base_cpuid); 5166 } 5167 5168 static void 5169 unref_ctx_core_offset(if_ctx_t ctx) 5170 { 5171 struct cpu_offset *op, *top; 5172 5173 mtx_lock(&cpu_offset_mtx); 5174 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5175 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5176 MPASS(op->refcount > 0); 5177 op->refcount--; 5178 if (op->refcount == 0) { 5179 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5180 free(op, M_IFLIB); 5181 } 5182 break; 5183 } 5184 } 5185 mtx_unlock(&cpu_offset_mtx); 5186 } 5187 5188 int 5189 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5190 { 5191 if_ctx_t ctx; 5192 if_t ifp; 5193 if_softc_ctx_t scctx; 5194 kobjop_desc_t kobj_desc; 5195 kobj_method_t *kobj_method; 5196 int err, msix, rid; 5197 int num_txd, num_rxd; 5198 5199 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 5200 5201 if (sc == NULL) { 5202 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5203 device_set_softc(dev, ctx); 5204 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5205 } 5206 5207 ctx->ifc_sctx = sctx; 5208 ctx->ifc_dev = dev; 5209 ctx->ifc_softc = sc; 5210 5211 if ((err = iflib_register(ctx)) != 0) { 5212 device_printf(dev, "iflib_register failed %d\n", err); 5213 goto fail_ctx_free; 5214 } 5215 iflib_add_device_sysctl_pre(ctx); 5216 5217 scctx = &ctx->ifc_softc_ctx; 5218 ifp = ctx->ifc_ifp; 5219 5220 iflib_reset_qvalues(ctx); 5221 IFNET_WLOCK(); 5222 CTX_LOCK(ctx); 5223 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5224 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5225 goto fail_unlock; 5226 } 5227 _iflib_pre_assert(scctx); 5228 ctx->ifc_txrx = *scctx->isc_txrx; 5229 5230 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5231 5232 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5233 ctx->ifc_mediap = scctx->isc_media; 5234 5235 #ifdef INVARIANTS 5236 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5237 MPASS(scctx->isc_tx_csum_flags); 5238 #endif 5239 5240 if_setcapabilities(ifp, 5241 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5242 if_setcapenable(ifp, 5243 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5244 5245 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5246 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5247 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5248 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5249 5250 num_txd = iflib_num_tx_descs(ctx); 5251 num_rxd = iflib_num_rx_descs(ctx); 5252 5253 /* XXX change for per-queue sizes */ 5254 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5255 num_txd, num_rxd); 5256 5257 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5258 scctx->isc_tx_nsegments = max(1, num_txd / 5259 MAX_SINGLE_PACKET_FRACTION); 5260 if (scctx->isc_tx_tso_segments_max > num_txd / 5261 MAX_SINGLE_PACKET_FRACTION) 5262 scctx->isc_tx_tso_segments_max = max(1, 5263 num_txd / MAX_SINGLE_PACKET_FRACTION); 5264 5265 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5266 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5267 /* 5268 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5269 * but some MACs do. 5270 */ 5271 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5272 IP_MAXPACKET)); 5273 /* 5274 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5275 * into account. In the worst case, each of these calls will 5276 * add another mbuf and, thus, the requirement for another DMA 5277 * segment. So for best performance, it doesn't make sense to 5278 * advertize a maximum of TSO segments that typically will 5279 * require defragmentation in iflib_encap(). 5280 */ 5281 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5282 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5283 } 5284 if (scctx->isc_rss_table_size == 0) 5285 scctx->isc_rss_table_size = 64; 5286 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5287 5288 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5289 /* XXX format name */ 5290 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5291 NULL, NULL, "admin"); 5292 5293 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5294 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5295 device_printf(dev, "Unable to fetch CPU list\n"); 5296 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5297 ctx->ifc_cpus_are_physical_cores = false; 5298 } else 5299 ctx->ifc_cpus_are_physical_cores = true; 5300 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5301 5302 /* 5303 ** Now set up MSI or MSI-X, should return us the number of supported 5304 ** vectors (will be 1 for a legacy interrupt and MSI). 5305 */ 5306 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5307 msix = scctx->isc_vectors; 5308 } else if (scctx->isc_msix_bar != 0) 5309 /* 5310 * The simple fact that isc_msix_bar is not 0 does not mean we 5311 * we have a good value there that is known to work. 5312 */ 5313 msix = iflib_msix_init(ctx); 5314 else { 5315 scctx->isc_vectors = 1; 5316 scctx->isc_ntxqsets = 1; 5317 scctx->isc_nrxqsets = 1; 5318 scctx->isc_intr = IFLIB_INTR_LEGACY; 5319 msix = 0; 5320 } 5321 /* Get memory for the station queues */ 5322 if ((err = iflib_queues_alloc(ctx))) { 5323 device_printf(dev, "Unable to allocate queue memory\n"); 5324 goto fail_intr_free; 5325 } 5326 5327 if ((err = iflib_qset_structures_setup(ctx))) 5328 goto fail_queues; 5329 5330 /* 5331 * Now that we know how many queues there are, get the core offset. 5332 */ 5333 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5334 5335 if (msix > 1) { 5336 /* 5337 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5338 * aren't the default NULL implementation. 5339 */ 5340 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5341 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5342 kobj_desc); 5343 if (kobj_method == &kobj_desc->deflt) { 5344 device_printf(dev, 5345 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5346 err = EOPNOTSUPP; 5347 goto fail_queues; 5348 } 5349 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5350 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5351 kobj_desc); 5352 if (kobj_method == &kobj_desc->deflt) { 5353 device_printf(dev, 5354 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5355 err = EOPNOTSUPP; 5356 goto fail_queues; 5357 } 5358 5359 /* 5360 * Assign the MSI-X vectors. 5361 * Note that the default NULL ifdi_msix_intr_assign method will 5362 * fail here, too. 5363 */ 5364 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5365 if (err != 0) { 5366 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5367 err); 5368 goto fail_queues; 5369 } 5370 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5371 rid = 0; 5372 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5373 MPASS(msix == 1); 5374 rid = 1; 5375 } 5376 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5377 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5378 goto fail_queues; 5379 } 5380 } else { 5381 device_printf(dev, 5382 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5383 err = ENODEV; 5384 goto fail_queues; 5385 } 5386 5387 /* 5388 * It prevents a double-locking panic with iflib_media_status when 5389 * the driver loads. 5390 */ 5391 CTX_UNLOCK(ctx); 5392 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5393 CTX_LOCK(ctx); 5394 5395 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5396 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5397 goto fail_detach; 5398 } 5399 5400 /* 5401 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5402 * This must appear after the call to ether_ifattach() because 5403 * ether_ifattach() sets if_hdrlen to the default value. 5404 */ 5405 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5406 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5407 5408 if ((err = iflib_netmap_attach(ctx))) { 5409 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5410 goto fail_detach; 5411 } 5412 *ctxp = ctx; 5413 5414 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5415 5416 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5417 iflib_add_device_sysctl_post(ctx); 5418 iflib_add_pfil(ctx); 5419 ctx->ifc_flags |= IFC_INIT_DONE; 5420 CTX_UNLOCK(ctx); 5421 IFNET_WUNLOCK(); 5422 5423 return (0); 5424 5425 fail_detach: 5426 ether_ifdetach(ctx->ifc_ifp); 5427 fail_queues: 5428 iflib_tqg_detach(ctx); 5429 iflib_tx_structures_free(ctx); 5430 iflib_rx_structures_free(ctx); 5431 IFDI_DETACH(ctx); 5432 IFDI_QUEUES_FREE(ctx); 5433 fail_intr_free: 5434 iflib_free_intr_mem(ctx); 5435 fail_unlock: 5436 CTX_UNLOCK(ctx); 5437 IFNET_WUNLOCK(); 5438 iflib_deregister(ctx); 5439 fail_ctx_free: 5440 device_set_softc(ctx->ifc_dev, NULL); 5441 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5442 free(ctx->ifc_softc, M_IFLIB); 5443 free(ctx, M_IFLIB); 5444 return (err); 5445 } 5446 5447 int 5448 iflib_device_attach(device_t dev) 5449 { 5450 if_ctx_t ctx; 5451 if_shared_ctx_t sctx; 5452 5453 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5454 return (ENOTSUP); 5455 5456 pci_enable_busmaster(dev); 5457 5458 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5459 } 5460 5461 int 5462 iflib_device_deregister(if_ctx_t ctx) 5463 { 5464 if_t ifp = ctx->ifc_ifp; 5465 device_t dev = ctx->ifc_dev; 5466 5467 /* Make sure VLANS are not using driver */ 5468 if (if_vlantrunkinuse(ifp)) { 5469 device_printf(dev, "Vlan in use, detach first\n"); 5470 return (EBUSY); 5471 } 5472 #ifdef PCI_IOV 5473 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5474 device_printf(dev, "SR-IOV in use; detach first.\n"); 5475 return (EBUSY); 5476 } 5477 #endif 5478 5479 STATE_LOCK(ctx); 5480 ctx->ifc_flags |= IFC_IN_DETACH; 5481 STATE_UNLOCK(ctx); 5482 5483 /* Unregister VLAN handlers before calling iflib_stop() */ 5484 iflib_unregister_vlan_handlers(ctx); 5485 5486 iflib_netmap_detach(ifp); 5487 ether_ifdetach(ifp); 5488 5489 CTX_LOCK(ctx); 5490 iflib_stop(ctx); 5491 CTX_UNLOCK(ctx); 5492 5493 iflib_rem_pfil(ctx); 5494 if (ctx->ifc_led_dev != NULL) 5495 led_destroy(ctx->ifc_led_dev); 5496 5497 iflib_tqg_detach(ctx); 5498 iflib_tx_structures_free(ctx); 5499 iflib_rx_structures_free(ctx); 5500 5501 CTX_LOCK(ctx); 5502 IFDI_DETACH(ctx); 5503 IFDI_QUEUES_FREE(ctx); 5504 CTX_UNLOCK(ctx); 5505 5506 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5507 iflib_free_intr_mem(ctx); 5508 5509 bus_generic_detach(dev); 5510 5511 iflib_deregister(ctx); 5512 5513 device_set_softc(ctx->ifc_dev, NULL); 5514 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5515 free(ctx->ifc_softc, M_IFLIB); 5516 unref_ctx_core_offset(ctx); 5517 free(ctx, M_IFLIB); 5518 return (0); 5519 } 5520 5521 static void 5522 iflib_tqg_detach(if_ctx_t ctx) 5523 { 5524 iflib_txq_t txq; 5525 iflib_rxq_t rxq; 5526 int i; 5527 struct taskqgroup *tqg; 5528 5529 /* XXX drain any dependent tasks */ 5530 tqg = qgroup_if_io_tqg; 5531 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5532 callout_drain(&txq->ift_timer); 5533 #ifdef DEV_NETMAP 5534 callout_drain(&txq->ift_netmap_timer); 5535 #endif /* DEV_NETMAP */ 5536 if (txq->ift_task.gt_uniq != NULL) 5537 taskqgroup_detach(tqg, &txq->ift_task); 5538 } 5539 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5540 if (rxq->ifr_task.gt_uniq != NULL) 5541 taskqgroup_detach(tqg, &rxq->ifr_task); 5542 } 5543 tqg = qgroup_if_config_tqg; 5544 if (ctx->ifc_admin_task.gt_uniq != NULL) 5545 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5546 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5547 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5548 } 5549 5550 static void 5551 iflib_free_intr_mem(if_ctx_t ctx) 5552 { 5553 5554 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5555 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5556 } 5557 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5558 pci_release_msi(ctx->ifc_dev); 5559 } 5560 if (ctx->ifc_msix_mem != NULL) { 5561 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5562 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5563 ctx->ifc_msix_mem = NULL; 5564 } 5565 } 5566 5567 int 5568 iflib_device_detach(device_t dev) 5569 { 5570 if_ctx_t ctx = device_get_softc(dev); 5571 5572 return (iflib_device_deregister(ctx)); 5573 } 5574 5575 int 5576 iflib_device_suspend(device_t dev) 5577 { 5578 if_ctx_t ctx = device_get_softc(dev); 5579 5580 CTX_LOCK(ctx); 5581 IFDI_SUSPEND(ctx); 5582 CTX_UNLOCK(ctx); 5583 5584 return bus_generic_suspend(dev); 5585 } 5586 int 5587 iflib_device_shutdown(device_t dev) 5588 { 5589 if_ctx_t ctx = device_get_softc(dev); 5590 5591 CTX_LOCK(ctx); 5592 IFDI_SHUTDOWN(ctx); 5593 CTX_UNLOCK(ctx); 5594 5595 return bus_generic_suspend(dev); 5596 } 5597 5598 int 5599 iflib_device_resume(device_t dev) 5600 { 5601 if_ctx_t ctx = device_get_softc(dev); 5602 iflib_txq_t txq = ctx->ifc_txqs; 5603 5604 CTX_LOCK(ctx); 5605 IFDI_RESUME(ctx); 5606 iflib_if_init_locked(ctx); 5607 CTX_UNLOCK(ctx); 5608 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5609 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5610 5611 return (bus_generic_resume(dev)); 5612 } 5613 5614 int 5615 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5616 { 5617 int error; 5618 if_ctx_t ctx = device_get_softc(dev); 5619 5620 CTX_LOCK(ctx); 5621 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5622 CTX_UNLOCK(ctx); 5623 5624 return (error); 5625 } 5626 5627 void 5628 iflib_device_iov_uninit(device_t dev) 5629 { 5630 if_ctx_t ctx = device_get_softc(dev); 5631 5632 CTX_LOCK(ctx); 5633 IFDI_IOV_UNINIT(ctx); 5634 CTX_UNLOCK(ctx); 5635 } 5636 5637 int 5638 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5639 { 5640 int error; 5641 if_ctx_t ctx = device_get_softc(dev); 5642 5643 CTX_LOCK(ctx); 5644 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5645 CTX_UNLOCK(ctx); 5646 5647 return (error); 5648 } 5649 5650 /********************************************************************* 5651 * 5652 * MODULE FUNCTION DEFINITIONS 5653 * 5654 **********************************************************************/ 5655 5656 /* 5657 * - Start a fast taskqueue thread for each core 5658 * - Start a taskqueue for control operations 5659 */ 5660 static int 5661 iflib_module_init(void) 5662 { 5663 iflib_timer_default = hz / 2; 5664 return (0); 5665 } 5666 5667 static int 5668 iflib_module_event_handler(module_t mod, int what, void *arg) 5669 { 5670 int err; 5671 5672 switch (what) { 5673 case MOD_LOAD: 5674 if ((err = iflib_module_init()) != 0) 5675 return (err); 5676 break; 5677 case MOD_UNLOAD: 5678 return (EBUSY); 5679 default: 5680 return (EOPNOTSUPP); 5681 } 5682 5683 return (0); 5684 } 5685 5686 /********************************************************************* 5687 * 5688 * PUBLIC FUNCTION DEFINITIONS 5689 * ordered as in iflib.h 5690 * 5691 **********************************************************************/ 5692 5693 static void 5694 _iflib_assert(if_shared_ctx_t sctx) 5695 { 5696 int i; 5697 5698 MPASS(sctx->isc_tx_maxsize); 5699 MPASS(sctx->isc_tx_maxsegsize); 5700 5701 MPASS(sctx->isc_rx_maxsize); 5702 MPASS(sctx->isc_rx_nsegments); 5703 MPASS(sctx->isc_rx_maxsegsize); 5704 5705 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5706 for (i = 0; i < sctx->isc_nrxqs; i++) { 5707 MPASS(sctx->isc_nrxd_min[i]); 5708 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5709 MPASS(sctx->isc_nrxd_max[i]); 5710 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5711 MPASS(sctx->isc_nrxd_default[i]); 5712 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5713 } 5714 5715 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5716 for (i = 0; i < sctx->isc_ntxqs; i++) { 5717 MPASS(sctx->isc_ntxd_min[i]); 5718 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5719 MPASS(sctx->isc_ntxd_max[i]); 5720 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5721 MPASS(sctx->isc_ntxd_default[i]); 5722 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5723 } 5724 } 5725 5726 static void 5727 _iflib_pre_assert(if_softc_ctx_t scctx) 5728 { 5729 5730 MPASS(scctx->isc_txrx->ift_txd_encap); 5731 MPASS(scctx->isc_txrx->ift_txd_flush); 5732 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5733 MPASS(scctx->isc_txrx->ift_rxd_available); 5734 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5735 MPASS(scctx->isc_txrx->ift_rxd_refill); 5736 MPASS(scctx->isc_txrx->ift_rxd_flush); 5737 } 5738 5739 static int 5740 iflib_register(if_ctx_t ctx) 5741 { 5742 if_shared_ctx_t sctx = ctx->ifc_sctx; 5743 driver_t *driver = sctx->isc_driver; 5744 device_t dev = ctx->ifc_dev; 5745 if_t ifp; 5746 5747 _iflib_assert(sctx); 5748 5749 CTX_LOCK_INIT(ctx); 5750 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5751 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5752 5753 /* 5754 * Initialize our context's device specific methods 5755 */ 5756 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5757 kobj_class_compile((kobj_class_t) driver); 5758 5759 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5760 if_setsoftc(ifp, ctx); 5761 if_setdev(ifp, dev); 5762 if_setinitfn(ifp, iflib_if_init); 5763 if_setioctlfn(ifp, iflib_if_ioctl); 5764 #ifdef ALTQ 5765 if_setstartfn(ifp, iflib_altq_if_start); 5766 if_settransmitfn(ifp, iflib_altq_if_transmit); 5767 if_setsendqready(ifp); 5768 #else 5769 if_settransmitfn(ifp, iflib_if_transmit); 5770 #endif 5771 if_setqflushfn(ifp, iflib_if_qflush); 5772 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5773 ctx->ifc_vlan_attach_event = 5774 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5775 EVENTHANDLER_PRI_FIRST); 5776 ctx->ifc_vlan_detach_event = 5777 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5778 EVENTHANDLER_PRI_FIRST); 5779 5780 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5781 ctx->ifc_mediap = &ctx->ifc_media; 5782 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5783 iflib_media_change, iflib_media_status); 5784 } 5785 return (0); 5786 } 5787 5788 static void 5789 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5790 { 5791 /* Unregister VLAN events */ 5792 if (ctx->ifc_vlan_attach_event != NULL) { 5793 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5794 ctx->ifc_vlan_attach_event = NULL; 5795 } 5796 if (ctx->ifc_vlan_detach_event != NULL) { 5797 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5798 ctx->ifc_vlan_detach_event = NULL; 5799 } 5800 5801 } 5802 5803 static void 5804 iflib_deregister(if_ctx_t ctx) 5805 { 5806 if_t ifp = ctx->ifc_ifp; 5807 5808 /* Remove all media */ 5809 ifmedia_removeall(&ctx->ifc_media); 5810 5811 /* Ensure that VLAN event handlers are unregistered */ 5812 iflib_unregister_vlan_handlers(ctx); 5813 5814 /* Release kobject reference */ 5815 kobj_delete((kobj_t) ctx, NULL); 5816 5817 /* Free the ifnet structure */ 5818 if_free(ifp); 5819 5820 STATE_LOCK_DESTROY(ctx); 5821 5822 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5823 CTX_LOCK_DESTROY(ctx); 5824 } 5825 5826 static int 5827 iflib_queues_alloc(if_ctx_t ctx) 5828 { 5829 if_shared_ctx_t sctx = ctx->ifc_sctx; 5830 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5831 device_t dev = ctx->ifc_dev; 5832 int nrxqsets = scctx->isc_nrxqsets; 5833 int ntxqsets = scctx->isc_ntxqsets; 5834 iflib_txq_t txq; 5835 iflib_rxq_t rxq; 5836 iflib_fl_t fl = NULL; 5837 int i, j, cpu, err, txconf, rxconf; 5838 iflib_dma_info_t ifdip; 5839 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5840 uint32_t *txqsizes = scctx->isc_txqsizes; 5841 uint8_t nrxqs = sctx->isc_nrxqs; 5842 uint8_t ntxqs = sctx->isc_ntxqs; 5843 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5844 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5845 caddr_t *vaddrs; 5846 uint64_t *paddrs; 5847 5848 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5849 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5850 KASSERT(nrxqs >= fl_offset + nfree_lists, 5851 ("there must be at least a rxq for each free list")); 5852 5853 /* Allocate the TX ring struct memory */ 5854 if (!(ctx->ifc_txqs = 5855 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5856 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5857 device_printf(dev, "Unable to allocate TX ring memory\n"); 5858 err = ENOMEM; 5859 goto fail; 5860 } 5861 5862 /* Now allocate the RX */ 5863 if (!(ctx->ifc_rxqs = 5864 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5865 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5866 device_printf(dev, "Unable to allocate RX ring memory\n"); 5867 err = ENOMEM; 5868 goto rx_fail; 5869 } 5870 5871 txq = ctx->ifc_txqs; 5872 rxq = ctx->ifc_rxqs; 5873 5874 /* 5875 * XXX handle allocation failure 5876 */ 5877 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5878 /* Set up some basics */ 5879 5880 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5881 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5882 device_printf(dev, 5883 "Unable to allocate TX DMA info memory\n"); 5884 err = ENOMEM; 5885 goto err_tx_desc; 5886 } 5887 txq->ift_ifdi = ifdip; 5888 for (j = 0; j < ntxqs; j++, ifdip++) { 5889 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5890 device_printf(dev, 5891 "Unable to allocate TX descriptors\n"); 5892 err = ENOMEM; 5893 goto err_tx_desc; 5894 } 5895 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5896 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5897 } 5898 txq->ift_ctx = ctx; 5899 txq->ift_id = i; 5900 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5901 txq->ift_br_offset = 1; 5902 } else { 5903 txq->ift_br_offset = 0; 5904 } 5905 5906 if (iflib_txsd_alloc(txq)) { 5907 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5908 err = ENOMEM; 5909 goto err_tx_desc; 5910 } 5911 5912 /* Initialize the TX lock */ 5913 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5914 device_get_nameunit(dev), txq->ift_id); 5915 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5916 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5917 txq->ift_timer.c_cpu = cpu; 5918 #ifdef DEV_NETMAP 5919 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 5920 txq->ift_netmap_timer.c_cpu = cpu; 5921 #endif /* DEV_NETMAP */ 5922 5923 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5924 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5925 if (err) { 5926 /* XXX free any allocated rings */ 5927 device_printf(dev, "Unable to allocate buf_ring\n"); 5928 goto err_tx_desc; 5929 } 5930 } 5931 5932 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5933 /* Set up some basics */ 5934 callout_init(&rxq->ifr_watchdog, 1); 5935 5936 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5937 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5938 device_printf(dev, 5939 "Unable to allocate RX DMA info memory\n"); 5940 err = ENOMEM; 5941 goto err_tx_desc; 5942 } 5943 5944 rxq->ifr_ifdi = ifdip; 5945 /* XXX this needs to be changed if #rx queues != #tx queues */ 5946 rxq->ifr_ntxqirq = 1; 5947 rxq->ifr_txqid[0] = i; 5948 for (j = 0; j < nrxqs; j++, ifdip++) { 5949 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5950 device_printf(dev, 5951 "Unable to allocate RX descriptors\n"); 5952 err = ENOMEM; 5953 goto err_tx_desc; 5954 } 5955 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5956 } 5957 rxq->ifr_ctx = ctx; 5958 rxq->ifr_id = i; 5959 rxq->ifr_fl_offset = fl_offset; 5960 rxq->ifr_nfl = nfree_lists; 5961 if (!(fl = 5962 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5963 device_printf(dev, "Unable to allocate free list memory\n"); 5964 err = ENOMEM; 5965 goto err_tx_desc; 5966 } 5967 rxq->ifr_fl = fl; 5968 for (j = 0; j < nfree_lists; j++) { 5969 fl[j].ifl_rxq = rxq; 5970 fl[j].ifl_id = j; 5971 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5972 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5973 } 5974 /* Allocate receive buffers for the ring */ 5975 if (iflib_rxsd_alloc(rxq)) { 5976 device_printf(dev, 5977 "Critical Failure setting up receive buffers\n"); 5978 err = ENOMEM; 5979 goto err_rx_desc; 5980 } 5981 5982 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5983 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5984 M_WAITOK); 5985 } 5986 5987 /* TXQs */ 5988 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5989 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5990 for (i = 0; i < ntxqsets; i++) { 5991 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5992 5993 for (j = 0; j < ntxqs; j++, di++) { 5994 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5995 paddrs[i*ntxqs + j] = di->idi_paddr; 5996 } 5997 } 5998 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5999 device_printf(ctx->ifc_dev, 6000 "Unable to allocate device TX queue\n"); 6001 iflib_tx_structures_free(ctx); 6002 free(vaddrs, M_IFLIB); 6003 free(paddrs, M_IFLIB); 6004 goto err_rx_desc; 6005 } 6006 free(vaddrs, M_IFLIB); 6007 free(paddrs, M_IFLIB); 6008 6009 /* RXQs */ 6010 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6011 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6012 for (i = 0; i < nrxqsets; i++) { 6013 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6014 6015 for (j = 0; j < nrxqs; j++, di++) { 6016 vaddrs[i*nrxqs + j] = di->idi_vaddr; 6017 paddrs[i*nrxqs + j] = di->idi_paddr; 6018 } 6019 } 6020 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6021 device_printf(ctx->ifc_dev, 6022 "Unable to allocate device RX queue\n"); 6023 iflib_tx_structures_free(ctx); 6024 free(vaddrs, M_IFLIB); 6025 free(paddrs, M_IFLIB); 6026 goto err_rx_desc; 6027 } 6028 free(vaddrs, M_IFLIB); 6029 free(paddrs, M_IFLIB); 6030 6031 return (0); 6032 6033 /* XXX handle allocation failure changes */ 6034 err_rx_desc: 6035 err_tx_desc: 6036 rx_fail: 6037 if (ctx->ifc_rxqs != NULL) 6038 free(ctx->ifc_rxqs, M_IFLIB); 6039 ctx->ifc_rxqs = NULL; 6040 if (ctx->ifc_txqs != NULL) 6041 free(ctx->ifc_txqs, M_IFLIB); 6042 ctx->ifc_txqs = NULL; 6043 fail: 6044 return (err); 6045 } 6046 6047 static int 6048 iflib_tx_structures_setup(if_ctx_t ctx) 6049 { 6050 iflib_txq_t txq = ctx->ifc_txqs; 6051 int i; 6052 6053 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6054 iflib_txq_setup(txq); 6055 6056 return (0); 6057 } 6058 6059 static void 6060 iflib_tx_structures_free(if_ctx_t ctx) 6061 { 6062 iflib_txq_t txq = ctx->ifc_txqs; 6063 if_shared_ctx_t sctx = ctx->ifc_sctx; 6064 int i, j; 6065 6066 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6067 for (j = 0; j < sctx->isc_ntxqs; j++) 6068 iflib_dma_free(&txq->ift_ifdi[j]); 6069 iflib_txq_destroy(txq); 6070 } 6071 free(ctx->ifc_txqs, M_IFLIB); 6072 ctx->ifc_txqs = NULL; 6073 } 6074 6075 /********************************************************************* 6076 * 6077 * Initialize all receive rings. 6078 * 6079 **********************************************************************/ 6080 static int 6081 iflib_rx_structures_setup(if_ctx_t ctx) 6082 { 6083 iflib_rxq_t rxq = ctx->ifc_rxqs; 6084 int q; 6085 #if defined(INET6) || defined(INET) 6086 int err, i; 6087 #endif 6088 6089 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6090 #if defined(INET6) || defined(INET) 6091 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6092 TCP_LRO_ENTRIES, min(1024, 6093 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6094 if (err != 0) { 6095 device_printf(ctx->ifc_dev, 6096 "LRO Initialization failed!\n"); 6097 goto fail; 6098 } 6099 #endif 6100 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6101 } 6102 return (0); 6103 #if defined(INET6) || defined(INET) 6104 fail: 6105 /* 6106 * Free LRO resources allocated so far, we will only handle 6107 * the rings that completed, the failing case will have 6108 * cleaned up for itself. 'q' failed, so its the terminus. 6109 */ 6110 rxq = ctx->ifc_rxqs; 6111 for (i = 0; i < q; ++i, rxq++) { 6112 tcp_lro_free(&rxq->ifr_lc); 6113 } 6114 return (err); 6115 #endif 6116 } 6117 6118 /********************************************************************* 6119 * 6120 * Free all receive rings. 6121 * 6122 **********************************************************************/ 6123 static void 6124 iflib_rx_structures_free(if_ctx_t ctx) 6125 { 6126 iflib_rxq_t rxq = ctx->ifc_rxqs; 6127 if_shared_ctx_t sctx = ctx->ifc_sctx; 6128 int i, j; 6129 6130 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6131 for (j = 0; j < sctx->isc_nrxqs; j++) 6132 iflib_dma_free(&rxq->ifr_ifdi[j]); 6133 iflib_rx_sds_free(rxq); 6134 #if defined(INET6) || defined(INET) 6135 tcp_lro_free(&rxq->ifr_lc); 6136 #endif 6137 } 6138 free(ctx->ifc_rxqs, M_IFLIB); 6139 ctx->ifc_rxqs = NULL; 6140 } 6141 6142 static int 6143 iflib_qset_structures_setup(if_ctx_t ctx) 6144 { 6145 int err; 6146 6147 /* 6148 * It is expected that the caller takes care of freeing queues if this 6149 * fails. 6150 */ 6151 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6152 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6153 return (err); 6154 } 6155 6156 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6157 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6158 6159 return (err); 6160 } 6161 6162 int 6163 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6164 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6165 { 6166 6167 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6168 } 6169 6170 /* Just to avoid copy/paste */ 6171 static inline int 6172 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6173 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6174 const char *name) 6175 { 6176 device_t dev; 6177 unsigned int base_cpuid, cpuid; 6178 int err; 6179 6180 dev = ctx->ifc_dev; 6181 base_cpuid = ctx->ifc_sysctl_core_offset; 6182 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6183 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6184 irq ? irq->ii_res : NULL, name); 6185 if (err) { 6186 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6187 return (err); 6188 } 6189 #ifdef notyet 6190 if (cpuid > ctx->ifc_cpuid_highest) 6191 ctx->ifc_cpuid_highest = cpuid; 6192 #endif 6193 return (0); 6194 } 6195 6196 /* 6197 * Allocate a hardware interrupt for subctx using the parent (ctx)'s hardware 6198 * resources. 6199 * 6200 * Similar to iflib_irq_alloc_generic(), but for interrupt type IFLIB_INTR_RXTX 6201 * only. 6202 * 6203 * XXX: Could be removed if subctx's dev has its intr resource allocation 6204 * methods replaced with custom ones? 6205 */ 6206 int 6207 iflib_irq_alloc_generic_subctx(if_ctx_t ctx, if_ctx_t subctx, if_irq_t irq, 6208 int rid, iflib_intr_type_t type, 6209 driver_filter_t *filter, void *filter_arg, 6210 int qid, const char *name) 6211 { 6212 device_t dev, subdev; 6213 struct grouptask *gtask; 6214 struct taskqgroup *tqg; 6215 iflib_filter_info_t info; 6216 gtask_fn_t *fn; 6217 int tqrid, err; 6218 driver_filter_t *intr_fast; 6219 void *q; 6220 6221 MPASS(ctx != NULL); 6222 MPASS(subctx != NULL); 6223 6224 tqrid = rid; 6225 dev = ctx->ifc_dev; 6226 subdev = subctx->ifc_dev; 6227 6228 switch (type) { 6229 case IFLIB_INTR_RXTX: 6230 q = &subctx->ifc_rxqs[qid]; 6231 info = &subctx->ifc_rxqs[qid].ifr_filter_info; 6232 gtask = &subctx->ifc_rxqs[qid].ifr_task; 6233 tqg = qgroup_if_io_tqg; 6234 fn = _task_fn_rx; 6235 intr_fast = iflib_fast_intr_rxtx; 6236 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6237 break; 6238 default: 6239 device_printf(dev, "%s: unknown net intr type for subctx %s (%d)\n", 6240 __func__, device_get_nameunit(subdev), type); 6241 return (EINVAL); 6242 } 6243 6244 info->ifi_filter = filter; 6245 info->ifi_filter_arg = filter_arg; 6246 info->ifi_task = gtask; 6247 info->ifi_ctx = q; 6248 6249 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6250 6251 /* Allocate interrupts from hardware using parent context */ 6252 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6253 if (err != 0) { 6254 device_printf(dev, "_iflib_irq_alloc failed for subctx %s: %d\n", 6255 device_get_nameunit(subdev), err); 6256 return (err); 6257 } 6258 6259 if (tqrid != -1) { 6260 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6261 name); 6262 if (err) 6263 return (err); 6264 } else { 6265 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6266 } 6267 6268 return (0); 6269 } 6270 6271 int 6272 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6273 iflib_intr_type_t type, driver_filter_t *filter, 6274 void *filter_arg, int qid, const char *name) 6275 { 6276 device_t dev; 6277 struct grouptask *gtask; 6278 struct taskqgroup *tqg; 6279 iflib_filter_info_t info; 6280 gtask_fn_t *fn; 6281 int tqrid, err; 6282 driver_filter_t *intr_fast; 6283 void *q; 6284 6285 info = &ctx->ifc_filter_info; 6286 tqrid = rid; 6287 6288 switch (type) { 6289 /* XXX merge tx/rx for netmap? */ 6290 case IFLIB_INTR_TX: 6291 q = &ctx->ifc_txqs[qid]; 6292 info = &ctx->ifc_txqs[qid].ift_filter_info; 6293 gtask = &ctx->ifc_txqs[qid].ift_task; 6294 tqg = qgroup_if_io_tqg; 6295 fn = _task_fn_tx; 6296 intr_fast = iflib_fast_intr; 6297 GROUPTASK_INIT(gtask, 0, fn, q); 6298 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6299 break; 6300 case IFLIB_INTR_RX: 6301 q = &ctx->ifc_rxqs[qid]; 6302 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6303 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6304 tqg = qgroup_if_io_tqg; 6305 fn = _task_fn_rx; 6306 intr_fast = iflib_fast_intr; 6307 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6308 break; 6309 case IFLIB_INTR_RXTX: 6310 q = &ctx->ifc_rxqs[qid]; 6311 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6312 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6313 tqg = qgroup_if_io_tqg; 6314 fn = _task_fn_rx; 6315 intr_fast = iflib_fast_intr_rxtx; 6316 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6317 break; 6318 case IFLIB_INTR_ADMIN: 6319 q = ctx; 6320 tqrid = -1; 6321 info = &ctx->ifc_filter_info; 6322 gtask = &ctx->ifc_admin_task; 6323 tqg = qgroup_if_config_tqg; 6324 fn = _task_fn_admin; 6325 intr_fast = iflib_fast_intr_ctx; 6326 break; 6327 default: 6328 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6329 __func__); 6330 return (EINVAL); 6331 } 6332 6333 info->ifi_filter = filter; 6334 info->ifi_filter_arg = filter_arg; 6335 info->ifi_task = gtask; 6336 info->ifi_ctx = q; 6337 6338 dev = ctx->ifc_dev; 6339 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6340 if (err != 0) { 6341 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6342 return (err); 6343 } 6344 if (type == IFLIB_INTR_ADMIN) 6345 return (0); 6346 6347 if (tqrid != -1) { 6348 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6349 name); 6350 if (err) 6351 return (err); 6352 } else { 6353 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6354 } 6355 6356 return (0); 6357 } 6358 6359 void 6360 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6361 void *arg, int qid, const char *name) 6362 { 6363 device_t dev; 6364 struct grouptask *gtask; 6365 struct taskqgroup *tqg; 6366 gtask_fn_t *fn; 6367 void *q; 6368 int err; 6369 6370 switch (type) { 6371 case IFLIB_INTR_TX: 6372 q = &ctx->ifc_txqs[qid]; 6373 gtask = &ctx->ifc_txqs[qid].ift_task; 6374 tqg = qgroup_if_io_tqg; 6375 fn = _task_fn_tx; 6376 GROUPTASK_INIT(gtask, 0, fn, q); 6377 break; 6378 case IFLIB_INTR_RX: 6379 q = &ctx->ifc_rxqs[qid]; 6380 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6381 tqg = qgroup_if_io_tqg; 6382 fn = _task_fn_rx; 6383 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6384 break; 6385 case IFLIB_INTR_IOV: 6386 q = ctx; 6387 gtask = &ctx->ifc_vflr_task; 6388 tqg = qgroup_if_config_tqg; 6389 fn = _task_fn_iov; 6390 GROUPTASK_INIT(gtask, 0, fn, q); 6391 break; 6392 default: 6393 panic("unknown net intr type"); 6394 } 6395 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6396 if (err) { 6397 dev = ctx->ifc_dev; 6398 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6399 name); 6400 } 6401 } 6402 6403 void 6404 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6405 { 6406 6407 if (irq->ii_tag) 6408 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6409 6410 if (irq->ii_res) 6411 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6412 rman_get_rid(irq->ii_res), irq->ii_res); 6413 } 6414 6415 static int 6416 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6417 { 6418 iflib_txq_t txq = ctx->ifc_txqs; 6419 iflib_rxq_t rxq = ctx->ifc_rxqs; 6420 if_irq_t irq = &ctx->ifc_legacy_irq; 6421 iflib_filter_info_t info; 6422 device_t dev; 6423 struct grouptask *gtask; 6424 struct resource *res; 6425 struct taskqgroup *tqg; 6426 void *q; 6427 int err, tqrid; 6428 bool rx_only; 6429 6430 q = &ctx->ifc_rxqs[0]; 6431 info = &rxq[0].ifr_filter_info; 6432 gtask = &rxq[0].ifr_task; 6433 tqg = qgroup_if_io_tqg; 6434 tqrid = *rid; 6435 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6436 6437 ctx->ifc_flags |= IFC_LEGACY; 6438 info->ifi_filter = filter; 6439 info->ifi_filter_arg = filter_arg; 6440 info->ifi_task = gtask; 6441 info->ifi_ctx = rx_only ? ctx : q; 6442 6443 dev = ctx->ifc_dev; 6444 /* We allocate a single interrupt resource */ 6445 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6446 iflib_fast_intr_rxtx, NULL, info, name); 6447 if (err != 0) 6448 return (err); 6449 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6450 res = irq->ii_res; 6451 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6452 6453 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6454 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6455 "tx"); 6456 return (0); 6457 } 6458 6459 void 6460 iflib_led_create(if_ctx_t ctx) 6461 { 6462 6463 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6464 device_get_nameunit(ctx->ifc_dev)); 6465 } 6466 6467 void 6468 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6469 { 6470 6471 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6472 } 6473 6474 void 6475 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6476 { 6477 6478 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6479 } 6480 6481 void 6482 iflib_admin_intr_deferred(if_ctx_t ctx) 6483 { 6484 6485 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6486 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6487 } 6488 6489 void 6490 iflib_iov_intr_deferred(if_ctx_t ctx) 6491 { 6492 6493 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6494 } 6495 6496 void 6497 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6498 { 6499 6500 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6501 name); 6502 } 6503 6504 void 6505 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6506 const char *name) 6507 { 6508 6509 GROUPTASK_INIT(gtask, 0, fn, ctx); 6510 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6511 name); 6512 } 6513 6514 void 6515 iflib_config_gtask_deinit(struct grouptask *gtask) 6516 { 6517 6518 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6519 } 6520 6521 void 6522 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6523 { 6524 if_t ifp = ctx->ifc_ifp; 6525 iflib_txq_t txq = ctx->ifc_txqs; 6526 6527 if_setbaudrate(ifp, baudrate); 6528 if (baudrate >= IF_Gbps(10)) { 6529 STATE_LOCK(ctx); 6530 ctx->ifc_flags |= IFC_PREFETCH; 6531 STATE_UNLOCK(ctx); 6532 } 6533 /* If link down, disable watchdog */ 6534 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6535 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6536 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6537 } 6538 ctx->ifc_link_state = link_state; 6539 if_link_state_change(ifp, link_state); 6540 } 6541 6542 static int 6543 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6544 { 6545 int credits; 6546 #ifdef INVARIANTS 6547 int credits_pre = txq->ift_cidx_processed; 6548 #endif 6549 6550 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6551 BUS_DMASYNC_POSTREAD); 6552 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6553 return (0); 6554 6555 txq->ift_processed += credits; 6556 txq->ift_cidx_processed += credits; 6557 6558 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6559 if (txq->ift_cidx_processed >= txq->ift_size) 6560 txq->ift_cidx_processed -= txq->ift_size; 6561 return (credits); 6562 } 6563 6564 static int 6565 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6566 { 6567 iflib_fl_t fl; 6568 u_int i; 6569 6570 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6571 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6572 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6573 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6574 budget)); 6575 } 6576 6577 void 6578 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6579 const char *description, if_int_delay_info_t info, 6580 int offset, int value) 6581 { 6582 info->iidi_ctx = ctx; 6583 info->iidi_offset = offset; 6584 info->iidi_value = value; 6585 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6586 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6587 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6588 info, 0, iflib_sysctl_int_delay, "I", description); 6589 } 6590 6591 struct sx * 6592 iflib_ctx_lock_get(if_ctx_t ctx) 6593 { 6594 6595 return (&ctx->ifc_ctx_sx); 6596 } 6597 6598 static int 6599 iflib_msix_init(if_ctx_t ctx) 6600 { 6601 device_t dev = ctx->ifc_dev; 6602 if_shared_ctx_t sctx = ctx->ifc_sctx; 6603 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6604 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6605 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6606 6607 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6608 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6609 6610 if (bootverbose) 6611 device_printf(dev, "msix_init qsets capped at %d\n", 6612 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6613 6614 /* Override by tuneable */ 6615 if (scctx->isc_disable_msix) 6616 goto msi; 6617 6618 /* First try MSI-X */ 6619 if ((msgs = pci_msix_count(dev)) == 0) { 6620 if (bootverbose) 6621 device_printf(dev, "MSI-X not supported or disabled\n"); 6622 goto msi; 6623 } 6624 6625 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6626 /* 6627 * bar == -1 => "trust me I know what I'm doing" 6628 * Some drivers are for hardware that is so shoddily 6629 * documented that no one knows which bars are which 6630 * so the developer has to map all bars. This hack 6631 * allows shoddy garbage to use MSI-X in this framework. 6632 */ 6633 if (bar != -1) { 6634 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6635 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6636 if (ctx->ifc_msix_mem == NULL) { 6637 device_printf(dev, "Unable to map MSI-X table\n"); 6638 goto msi; 6639 } 6640 } 6641 6642 admincnt = sctx->isc_admin_intrcnt; 6643 #if IFLIB_DEBUG 6644 /* use only 1 qset in debug mode */ 6645 queuemsgs = min(msgs - admincnt, 1); 6646 #else 6647 queuemsgs = msgs - admincnt; 6648 #endif 6649 #ifdef RSS 6650 queues = imin(queuemsgs, rss_getnumbuckets()); 6651 #else 6652 queues = queuemsgs; 6653 #endif 6654 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6655 if (bootverbose) 6656 device_printf(dev, 6657 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6658 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6659 #ifdef RSS 6660 /* If we're doing RSS, clamp at the number of RSS buckets */ 6661 if (queues > rss_getnumbuckets()) 6662 queues = rss_getnumbuckets(); 6663 #endif 6664 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6665 rx_queues = iflib_num_rx_queues; 6666 else 6667 rx_queues = queues; 6668 6669 if (rx_queues > scctx->isc_nrxqsets) 6670 rx_queues = scctx->isc_nrxqsets; 6671 6672 /* 6673 * We want this to be all logical CPUs by default 6674 */ 6675 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6676 tx_queues = iflib_num_tx_queues; 6677 else 6678 tx_queues = mp_ncpus; 6679 6680 if (tx_queues > scctx->isc_ntxqsets) 6681 tx_queues = scctx->isc_ntxqsets; 6682 6683 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6684 #ifdef INVARIANTS 6685 if (tx_queues != rx_queues) 6686 device_printf(dev, 6687 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6688 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6689 #endif 6690 tx_queues = min(rx_queues, tx_queues); 6691 rx_queues = min(rx_queues, tx_queues); 6692 } 6693 6694 vectors = rx_queues + admincnt; 6695 if (msgs < vectors) { 6696 device_printf(dev, 6697 "insufficient number of MSI-X vectors " 6698 "(supported %d, need %d)\n", msgs, vectors); 6699 goto msi; 6700 } 6701 6702 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6703 tx_queues); 6704 msgs = vectors; 6705 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6706 if (vectors != msgs) { 6707 device_printf(dev, 6708 "Unable to allocate sufficient MSI-X vectors " 6709 "(got %d, need %d)\n", vectors, msgs); 6710 pci_release_msi(dev); 6711 if (bar != -1) { 6712 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6713 ctx->ifc_msix_mem); 6714 ctx->ifc_msix_mem = NULL; 6715 } 6716 goto msi; 6717 } 6718 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6719 vectors); 6720 scctx->isc_vectors = vectors; 6721 scctx->isc_nrxqsets = rx_queues; 6722 scctx->isc_ntxqsets = tx_queues; 6723 scctx->isc_intr = IFLIB_INTR_MSIX; 6724 6725 return (vectors); 6726 } else { 6727 device_printf(dev, 6728 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6729 err); 6730 if (bar != -1) { 6731 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6732 ctx->ifc_msix_mem); 6733 ctx->ifc_msix_mem = NULL; 6734 } 6735 } 6736 6737 msi: 6738 vectors = pci_msi_count(dev); 6739 scctx->isc_nrxqsets = 1; 6740 scctx->isc_ntxqsets = 1; 6741 scctx->isc_vectors = vectors; 6742 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6743 device_printf(dev,"Using an MSI interrupt\n"); 6744 scctx->isc_intr = IFLIB_INTR_MSI; 6745 } else { 6746 scctx->isc_vectors = 1; 6747 device_printf(dev,"Using a Legacy interrupt\n"); 6748 scctx->isc_intr = IFLIB_INTR_LEGACY; 6749 } 6750 6751 return (vectors); 6752 } 6753 6754 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6755 6756 static int 6757 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6758 { 6759 int rc; 6760 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6761 struct sbuf *sb; 6762 const char *ring_state = "UNKNOWN"; 6763 6764 /* XXX needed ? */ 6765 rc = sysctl_wire_old_buffer(req, 0); 6766 MPASS(rc == 0); 6767 if (rc != 0) 6768 return (rc); 6769 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6770 MPASS(sb != NULL); 6771 if (sb == NULL) 6772 return (ENOMEM); 6773 if (state[3] <= 3) 6774 ring_state = ring_states[state[3]]; 6775 6776 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6777 state[0], state[1], state[2], ring_state); 6778 rc = sbuf_finish(sb); 6779 sbuf_delete(sb); 6780 return(rc); 6781 } 6782 6783 enum iflib_ndesc_handler { 6784 IFLIB_NTXD_HANDLER, 6785 IFLIB_NRXD_HANDLER, 6786 }; 6787 6788 static int 6789 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6790 { 6791 if_ctx_t ctx = (void *)arg1; 6792 enum iflib_ndesc_handler type = arg2; 6793 char buf[256] = {0}; 6794 qidx_t *ndesc; 6795 char *p, *next; 6796 int nqs, rc, i; 6797 6798 nqs = 8; 6799 switch(type) { 6800 case IFLIB_NTXD_HANDLER: 6801 ndesc = ctx->ifc_sysctl_ntxds; 6802 if (ctx->ifc_sctx) 6803 nqs = ctx->ifc_sctx->isc_ntxqs; 6804 break; 6805 case IFLIB_NRXD_HANDLER: 6806 ndesc = ctx->ifc_sysctl_nrxds; 6807 if (ctx->ifc_sctx) 6808 nqs = ctx->ifc_sctx->isc_nrxqs; 6809 break; 6810 default: 6811 printf("%s: unhandled type\n", __func__); 6812 return (EINVAL); 6813 } 6814 if (nqs == 0) 6815 nqs = 8; 6816 6817 for (i=0; i<8; i++) { 6818 if (i >= nqs) 6819 break; 6820 if (i) 6821 strcat(buf, ","); 6822 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6823 } 6824 6825 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6826 if (rc || req->newptr == NULL) 6827 return rc; 6828 6829 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6830 i++, p = strsep(&next, " ,")) { 6831 ndesc[i] = strtoul(p, NULL, 10); 6832 } 6833 6834 return(rc); 6835 } 6836 6837 #define NAME_BUFLEN 32 6838 static void 6839 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6840 { 6841 device_t dev = iflib_get_dev(ctx); 6842 struct sysctl_oid_list *child, *oid_list; 6843 struct sysctl_ctx_list *ctx_list; 6844 struct sysctl_oid *node; 6845 6846 ctx_list = device_get_sysctl_ctx(dev); 6847 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6848 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6849 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6850 oid_list = SYSCTL_CHILDREN(node); 6851 6852 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6853 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6854 "driver version"); 6855 6856 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6857 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6858 "# of txqs to use, 0 => use default #"); 6859 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6860 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6861 "# of rxqs to use, 0 => use default #"); 6862 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6863 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6864 "permit #txq != #rxq"); 6865 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6866 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6867 "disable MSI-X (default 0)"); 6868 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6869 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6870 "set the RX budget"); 6871 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6872 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6873 "cause TX to abdicate instead of running to completion"); 6874 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6875 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6876 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6877 "offset to start using cores at"); 6878 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6879 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6880 "use separate cores for TX and RX"); 6881 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 6882 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6883 "try to make use of logical cores for TX and RX"); 6884 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "use_extra_msix_vectors", 6885 CTLFLAG_RDTUN, &ctx->ifc_sysctl_extra_msix_vectors, 0, 6886 "attempt to reserve the given number of extra MSI-X vectors during driver load for the creation of additional interfaces later"); 6887 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "allocated_msix_vectors", 6888 CTLFLAG_RDTUN, &ctx->ifc_softc_ctx.isc_vectors, 0, 6889 "total # of MSI-X vectors allocated by driver"); 6890 6891 /* XXX change for per-queue sizes */ 6892 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6893 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6894 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6895 "list of # of TX descriptors to use, 0 = use default #"); 6896 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6897 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6898 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6899 "list of # of RX descriptors to use, 0 = use default #"); 6900 } 6901 6902 static void 6903 iflib_add_device_sysctl_post(if_ctx_t ctx) 6904 { 6905 if_shared_ctx_t sctx = ctx->ifc_sctx; 6906 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6907 device_t dev = iflib_get_dev(ctx); 6908 struct sysctl_oid_list *child; 6909 struct sysctl_ctx_list *ctx_list; 6910 iflib_fl_t fl; 6911 iflib_txq_t txq; 6912 iflib_rxq_t rxq; 6913 int i, j; 6914 char namebuf[NAME_BUFLEN]; 6915 char *qfmt; 6916 struct sysctl_oid *queue_node, *fl_node, *node; 6917 struct sysctl_oid_list *queue_list, *fl_list; 6918 ctx_list = device_get_sysctl_ctx(dev); 6919 6920 node = ctx->ifc_sysctl_node; 6921 child = SYSCTL_CHILDREN(node); 6922 6923 if (scctx->isc_ntxqsets > 100) 6924 qfmt = "txq%03d"; 6925 else if (scctx->isc_ntxqsets > 10) 6926 qfmt = "txq%02d"; 6927 else 6928 qfmt = "txq%d"; 6929 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6930 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6931 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6932 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6933 queue_list = SYSCTL_CHILDREN(queue_node); 6934 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6935 CTLFLAG_RD, 6936 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to"); 6937 #if MEMORY_LOGGING 6938 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6939 CTLFLAG_RD, 6940 &txq->ift_dequeued, "total mbufs freed"); 6941 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6942 CTLFLAG_RD, 6943 &txq->ift_enqueued, "total mbufs enqueued"); 6944 #endif 6945 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6946 CTLFLAG_RD, 6947 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6948 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6949 CTLFLAG_RD, 6950 &txq->ift_pullups, "# of times m_pullup was called"); 6951 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6952 CTLFLAG_RD, 6953 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6954 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6955 CTLFLAG_RD, 6956 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6957 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6958 CTLFLAG_RD, 6959 &txq->ift_map_failed, "# of times DMA map failed"); 6960 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6961 CTLFLAG_RD, 6962 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6963 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6964 CTLFLAG_RD, 6965 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6966 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6967 CTLFLAG_RD, 6968 &txq->ift_pidx, 1, "Producer Index"); 6969 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6970 CTLFLAG_RD, 6971 &txq->ift_cidx, 1, "Consumer Index"); 6972 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6973 CTLFLAG_RD, 6974 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6975 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6976 CTLFLAG_RD, 6977 &txq->ift_in_use, 1, "descriptors in use"); 6978 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6979 CTLFLAG_RD, 6980 &txq->ift_processed, "descriptors procesed for clean"); 6981 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6982 CTLFLAG_RD, 6983 &txq->ift_cleaned, "total cleaned"); 6984 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6985 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6986 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6987 mp_ring_state_handler, "A", "soft ring state"); 6988 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6989 CTLFLAG_RD, &txq->ift_br->enqueues, 6990 "# of enqueues to the mp_ring for this queue"); 6991 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6992 CTLFLAG_RD, &txq->ift_br->drops, 6993 "# of drops in the mp_ring for this queue"); 6994 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6995 CTLFLAG_RD, &txq->ift_br->starts, 6996 "# of normal consumer starts in the mp_ring for this queue"); 6997 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6998 CTLFLAG_RD, &txq->ift_br->stalls, 6999 "# of consumer stalls in the mp_ring for this queue"); 7000 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 7001 CTLFLAG_RD, &txq->ift_br->restarts, 7002 "# of consumer restarts in the mp_ring for this queue"); 7003 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 7004 CTLFLAG_RD, &txq->ift_br->abdications, 7005 "# of consumer abdications in the mp_ring for this queue"); 7006 } 7007 7008 if (scctx->isc_nrxqsets > 100) 7009 qfmt = "rxq%03d"; 7010 else if (scctx->isc_nrxqsets > 10) 7011 qfmt = "rxq%02d"; 7012 else 7013 qfmt = "rxq%d"; 7014 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 7015 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7016 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7017 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7018 queue_list = SYSCTL_CHILDREN(queue_node); 7019 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7020 CTLFLAG_RD, 7021 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to"); 7022 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7023 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 7024 CTLFLAG_RD, 7025 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 7026 } 7027 7028 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7029 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7030 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 7031 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 7032 fl_list = SYSCTL_CHILDREN(fl_node); 7033 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7034 CTLFLAG_RD, 7035 &fl->ifl_pidx, 1, "Producer Index"); 7036 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7037 CTLFLAG_RD, 7038 &fl->ifl_cidx, 1, "Consumer Index"); 7039 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7040 CTLFLAG_RD, 7041 &fl->ifl_credits, 1, "credits available"); 7042 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7043 CTLFLAG_RD, 7044 &fl->ifl_buf_size, 1, "buffer size"); 7045 #if MEMORY_LOGGING 7046 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 7047 CTLFLAG_RD, 7048 &fl->ifl_m_enqueued, "mbufs allocated"); 7049 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 7050 CTLFLAG_RD, 7051 &fl->ifl_m_dequeued, "mbufs freed"); 7052 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 7053 CTLFLAG_RD, 7054 &fl->ifl_cl_enqueued, "clusters allocated"); 7055 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 7056 CTLFLAG_RD, 7057 &fl->ifl_cl_dequeued, "clusters freed"); 7058 #endif 7059 } 7060 } 7061 7062 } 7063 7064 void 7065 iflib_request_reset(if_ctx_t ctx) 7066 { 7067 7068 STATE_LOCK(ctx); 7069 ctx->ifc_flags |= IFC_DO_RESET; 7070 STATE_UNLOCK(ctx); 7071 } 7072 7073 #ifndef __NO_STRICT_ALIGNMENT 7074 static struct mbuf * 7075 iflib_fixup_rx(struct mbuf *m) 7076 { 7077 struct mbuf *n; 7078 7079 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7080 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7081 m->m_data += ETHER_HDR_LEN; 7082 n = m; 7083 } else { 7084 MGETHDR(n, M_NOWAIT, MT_DATA); 7085 if (n == NULL) { 7086 m_freem(m); 7087 return (NULL); 7088 } 7089 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7090 m->m_data += ETHER_HDR_LEN; 7091 m->m_len -= ETHER_HDR_LEN; 7092 n->m_len = ETHER_HDR_LEN; 7093 M_MOVE_PKTHDR(n, m); 7094 n->m_next = m; 7095 } 7096 return (n); 7097 } 7098 #endif 7099 7100 #ifdef DEBUGNET 7101 static void 7102 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7103 { 7104 if_ctx_t ctx; 7105 7106 ctx = if_getsoftc(ifp); 7107 CTX_LOCK(ctx); 7108 *nrxr = NRXQSETS(ctx); 7109 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7110 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7111 CTX_UNLOCK(ctx); 7112 } 7113 7114 static void 7115 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7116 { 7117 if_ctx_t ctx; 7118 if_softc_ctx_t scctx; 7119 iflib_fl_t fl; 7120 iflib_rxq_t rxq; 7121 int i, j; 7122 7123 ctx = if_getsoftc(ifp); 7124 scctx = &ctx->ifc_softc_ctx; 7125 7126 switch (event) { 7127 case DEBUGNET_START: 7128 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7129 rxq = &ctx->ifc_rxqs[i]; 7130 for (j = 0; j < rxq->ifr_nfl; j++) { 7131 fl = rxq->ifr_fl; 7132 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7133 } 7134 } 7135 iflib_no_tx_batch = 1; 7136 break; 7137 default: 7138 break; 7139 } 7140 } 7141 7142 static int 7143 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7144 { 7145 if_ctx_t ctx; 7146 iflib_txq_t txq; 7147 int error; 7148 7149 ctx = if_getsoftc(ifp); 7150 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7151 IFF_DRV_RUNNING) 7152 return (EBUSY); 7153 7154 txq = &ctx->ifc_txqs[0]; 7155 error = iflib_encap(txq, &m); 7156 if (error == 0) 7157 (void)iflib_txd_db_check(txq, true); 7158 return (error); 7159 } 7160 7161 static int 7162 iflib_debugnet_poll(if_t ifp, int count) 7163 { 7164 struct epoch_tracker et; 7165 if_ctx_t ctx; 7166 if_softc_ctx_t scctx; 7167 iflib_txq_t txq; 7168 int i; 7169 7170 ctx = if_getsoftc(ifp); 7171 scctx = &ctx->ifc_softc_ctx; 7172 7173 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7174 IFF_DRV_RUNNING) 7175 return (EBUSY); 7176 7177 txq = &ctx->ifc_txqs[0]; 7178 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7179 7180 NET_EPOCH_ENTER(et); 7181 for (i = 0; i < scctx->isc_nrxqsets; i++) 7182 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7183 NET_EPOCH_EXIT(et); 7184 return (0); 7185 } 7186 #endif /* DEBUGNET */ 7187