1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2019 Emmanuel Vadot <[email protected]> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/rman.h> 38 #include <sys/condvar.h> 39 #include <sys/kernel.h> 40 #include <sys/module.h> 41 #include <sys/gpio.h> 42 #include <machine/bus.h> 43 44 #include <dev/fdt/simplebus.h> 45 46 #include <dev/fdt/fdt_common.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 #include <dev/ofw/ofw_subr.h> 50 51 #include <dev/usb/usb.h> 52 #include <dev/usb/usbdi.h> 53 54 #include <dev/usb/usb_core.h> 55 #include <dev/usb/usb_busdma.h> 56 #include <dev/usb/usb_process.h> 57 58 #include <dev/usb/usb_controller.h> 59 #include <dev/usb/usb_bus.h> 60 #include <dev/usb/controller/xhci.h> 61 #include <dev/usb/controller/dwc3.h> 62 63 #include <dev/extres/clk/clk.h> 64 #include <dev/extres/phy/phy_usb.h> 65 66 #include "generic_xhci.h" 67 68 static struct ofw_compat_data compat_data[] = { 69 { "snps,dwc3", 1 }, 70 { NULL, 0 } 71 }; 72 73 struct snps_dwc3_softc { 74 struct xhci_softc sc; 75 device_t dev; 76 char dr_mode[16]; 77 struct resource * mem_res; 78 bus_space_tag_t bst; 79 bus_space_handle_t bsh; 80 phandle_t node; 81 phy_t usb2_phy; 82 phy_t usb3_phy; 83 }; 84 85 #define DWC3_WRITE(_sc, _off, _val) \ 86 bus_space_write_4(_sc->bst, _sc->bsh, _off, _val) 87 #define DWC3_READ(_sc, _off) \ 88 bus_space_read_4(_sc->bst, _sc->bsh, _off) 89 90 static int 91 snps_dwc3_attach_xhci(device_t dev) 92 { 93 struct snps_dwc3_softc *snps_sc = device_get_softc(dev); 94 struct xhci_softc *sc = &snps_sc->sc; 95 int err = 0, rid = 0; 96 97 sc->sc_io_res = snps_sc->mem_res; 98 sc->sc_io_tag = snps_sc->bst; 99 sc->sc_io_hdl = snps_sc->bsh; 100 sc->sc_io_size = rman_get_size(snps_sc->mem_res); 101 102 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 103 RF_SHAREABLE | RF_ACTIVE); 104 if (sc->sc_irq_res == NULL) { 105 device_printf(dev, "Failed to allocate IRQ\n"); 106 return (ENXIO); 107 } 108 109 sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); 110 if (sc->sc_bus.bdev == NULL) { 111 device_printf(dev, "Failed to add USB device\n"); 112 return (ENXIO); 113 } 114 115 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 116 117 sprintf(sc->sc_vendor, "Synopsys"); 118 device_set_desc(sc->sc_bus.bdev, "Synopsys"); 119 120 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 121 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 122 if (err != 0) { 123 device_printf(dev, "Failed to setup IRQ, %d\n", err); 124 sc->sc_intr_hdl = NULL; 125 return (err); 126 } 127 128 err = xhci_init(sc, dev, 1); 129 if (err != 0) { 130 device_printf(dev, "Failed to init XHCI, with error %d\n", err); 131 return (ENXIO); 132 } 133 134 err = xhci_start_controller(sc); 135 if (err != 0) { 136 device_printf(dev, "Failed to start XHCI controller, with error %d\n", err); 137 return (ENXIO); 138 } 139 140 device_printf(sc->sc_bus.bdev, "trying to attach\n"); 141 err = device_probe_and_attach(sc->sc_bus.bdev); 142 if (err != 0) { 143 device_printf(dev, "Failed to initialize USB, with error %d\n", err); 144 return (ENXIO); 145 } 146 147 return (0); 148 } 149 150 #if 0 151 static void 152 snsp_dwc3_dump_regs(struct snps_dwc3_softc *sc) 153 { 154 uint32_t reg; 155 156 reg = DWC3_READ(sc, DWC3_GCTL); 157 device_printf(sc->dev, "GCTL: %x\n", reg); 158 reg = DWC3_READ(sc, DWC3_GUCTL1); 159 device_printf(sc->dev, "GUCTL1: %x\n", reg); 160 reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); 161 device_printf(sc->dev, "GUSB2PHYCFG0: %x\n", reg); 162 reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); 163 device_printf(sc->dev, "GUSB3PIPECTL0: %x\n", reg); 164 reg = DWC3_READ(sc, DWC3_DCFG); 165 device_printf(sc->dev, "DCFG: %x\n", reg); 166 } 167 #endif 168 169 static void 170 snps_dwc3_reset(struct snps_dwc3_softc *sc) 171 { 172 uint32_t gctl, phy2, phy3; 173 174 if (sc->usb2_phy) 175 phy_enable(sc->usb2_phy); 176 if (sc->usb3_phy) 177 phy_enable(sc->usb3_phy); 178 179 gctl = DWC3_READ(sc, DWC3_GCTL); 180 gctl |= DWC3_GCTL_CORESOFTRESET; 181 DWC3_WRITE(sc, DWC3_GCTL, gctl); 182 183 phy2 = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); 184 phy2 |= DWC3_GUSB2PHYCFG0_PHYSOFTRST; 185 DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2); 186 187 phy3 = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); 188 phy3 |= DWC3_GUSB3PIPECTL0_PHYSOFTRST; 189 DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3); 190 191 DELAY(1000); 192 193 phy2 &= ~DWC3_GUSB2PHYCFG0_PHYSOFTRST; 194 DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2); 195 196 phy3 &= ~DWC3_GUSB3PIPECTL0_PHYSOFTRST; 197 DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3); 198 199 gctl &= ~DWC3_GCTL_CORESOFTRESET; 200 DWC3_WRITE(sc, DWC3_GCTL, gctl); 201 202 } 203 204 static void 205 snps_dwc3_configure_host(struct snps_dwc3_softc *sc) 206 { 207 uint32_t reg; 208 209 reg = DWC3_READ(sc, DWC3_GCTL); 210 reg &= ~DWC3_GCTL_PRTCAPDIR_MASK; 211 reg |= DWC3_GCTL_PRTCAPDIR_HOST; 212 DWC3_WRITE(sc, DWC3_GCTL, reg); 213 } 214 215 static void 216 snps_dwc3_configure_phy(struct snps_dwc3_softc *sc) 217 { 218 char *phy_type; 219 uint32_t reg; 220 int nphy_types; 221 222 phy_type = NULL; 223 nphy_types = OF_getprop_alloc(sc->node, "phy_type", (void **)&phy_type); 224 if (nphy_types <= 0) 225 return; 226 227 reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); 228 if (strncmp(phy_type, "utmi_wide", 9) == 0) { 229 reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf)); 230 reg |= DWC3_GUSB2PHYCFG0_PHYIF | 231 DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_16BITS); 232 } else { 233 reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf)); 234 reg |= DWC3_GUSB2PHYCFG0_PHYIF | 235 DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_8BITS); 236 } 237 DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg); 238 OF_prop_free(phy_type); 239 } 240 241 static void 242 snps_dwc3_do_quirks(struct snps_dwc3_softc *sc) 243 { 244 uint32_t reg; 245 246 reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); 247 if (OF_hasprop(sc->node, "snps,dis-u2-freeclk-exists-quirk")) 248 reg &= ~DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; 249 else 250 reg |= DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; 251 if (OF_hasprop(sc->node, "snps,dis_u2_susphy_quirk")) 252 reg &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20; 253 else 254 reg |= DWC3_GUSB2PHYCFG0_SUSPENDUSB20; 255 if (OF_hasprop(sc->node, "snps,dis_enblslpm_quirk")) 256 reg &= ~DWC3_GUSB2PHYCFG0_ENBLSLPM; 257 else 258 reg |= DWC3_GUSB2PHYCFG0_ENBLSLPM; 259 260 DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg); 261 262 reg = DWC3_READ(sc, DWC3_GUCTL1); 263 if (OF_hasprop(sc->node, "snps,dis-tx-ipgap-linecheck-quirk")) 264 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 265 DWC3_WRITE(sc, DWC3_GUCTL1, reg); 266 267 if (OF_hasprop(sc->node, "snps,dis-del-phy-power-chg-quirk")) { 268 reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); 269 reg |= DWC3_GUSB3PIPECTL0_DELAYP1TRANS; 270 DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, reg); 271 } 272 } 273 274 static int 275 snps_dwc3_probe(device_t dev) 276 { 277 struct snps_dwc3_softc *sc; 278 279 if (!ofw_bus_status_okay(dev)) 280 return (ENXIO); 281 282 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 283 return (ENXIO); 284 285 sc = device_get_softc(dev); 286 sc->node = ofw_bus_get_node(dev); 287 OF_getprop(sc->node, "dr_mode", sc->dr_mode, sizeof(sc->dr_mode)); 288 if (strcmp(sc->dr_mode, "host") != 0) { 289 device_printf(dev, "Only host mode is supported\n"); 290 return (ENXIO); 291 } 292 293 device_set_desc(dev, "Synopsys Designware DWC3"); 294 return (BUS_PROBE_DEFAULT); 295 } 296 297 static int 298 snps_dwc3_attach(device_t dev) 299 { 300 struct snps_dwc3_softc *sc; 301 int rid = 0; 302 303 sc = device_get_softc(dev); 304 sc->dev = dev; 305 306 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 307 RF_ACTIVE); 308 if (sc->mem_res == NULL) { 309 device_printf(dev, "Failed to map memory\n"); 310 return (ENXIO); 311 } 312 sc->bst = rman_get_bustag(sc->mem_res); 313 sc->bsh = rman_get_bushandle(sc->mem_res); 314 315 if (bootverbose) 316 device_printf(dev, "snps id: %x\n", DWC3_READ(sc, DWC3_GSNPSID)); 317 318 /* Get the phys */ 319 phy_get_by_ofw_name(dev, sc->node, "usb2-phy", &sc->usb2_phy); 320 phy_get_by_ofw_name(dev, sc->node, "usb3-phy", &sc->usb3_phy); 321 322 snps_dwc3_reset(sc); 323 snps_dwc3_configure_host(sc); 324 snps_dwc3_configure_phy(sc); 325 snps_dwc3_do_quirks(sc); 326 #if 0 327 snsp_dwc3_dump_regs(sc); 328 #endif 329 snps_dwc3_attach_xhci(dev); 330 331 return (0); 332 } 333 334 static device_method_t snps_dwc3_methods[] = { 335 /* Device interface */ 336 DEVMETHOD(device_probe, snps_dwc3_probe), 337 DEVMETHOD(device_attach, snps_dwc3_attach), 338 339 DEVMETHOD_END 340 }; 341 342 static driver_t snps_dwc3_driver = { 343 "xhci", 344 snps_dwc3_methods, 345 sizeof(struct snps_dwc3_softc) 346 }; 347 348 static devclass_t snps_dwc3_devclass; 349 DRIVER_MODULE(snps_dwc3, simplebus, snps_dwc3_driver, snps_dwc3_devclass, 0, 0); 350 MODULE_DEPEND(snps_dwc3, xhci, 1, 1, 1); 351