1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Emmanuel Vadot <[email protected]> 5 * Copyright (c) 2021-2022 Bjoern A. Zeeb <[email protected]> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include "opt_platform.h" 31 #include "opt_acpi.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/condvar.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #ifdef FDT 42 #include <sys/gpio.h> 43 #endif 44 45 #include <machine/bus.h> 46 47 #include <dev/usb/usb.h> 48 #include <dev/usb/usbdi.h> 49 50 #include <dev/usb/usb_core.h> 51 #include <dev/usb/usb_busdma.h> 52 #include <dev/usb/usb_process.h> 53 54 #include <dev/usb/usb_controller.h> 55 #include <dev/usb/usb_bus.h> 56 #include <dev/usb/controller/xhci.h> 57 #include <dev/usb/controller/dwc3.h> 58 59 #ifdef FDT 60 #include <dev/fdt/simplebus.h> 61 62 #include <dev/fdt/fdt_common.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_bus_subr.h> 65 #include <dev/ofw/ofw_subr.h> 66 67 #include <dev/extres/clk/clk.h> 68 #include <dev/extres/phy/phy_usb.h> 69 #endif 70 71 #ifdef DEV_ACPI 72 #include <contrib/dev/acpica/include/acpi.h> 73 #include <contrib/dev/acpica/include/accommon.h> 74 #include <dev/acpica/acpivar.h> 75 #endif 76 77 #include "generic_xhci.h" 78 79 struct snps_dwc3_softc { 80 struct xhci_softc sc; 81 device_t dev; 82 struct resource * mem_res; 83 bus_space_tag_t bst; 84 bus_space_handle_t bsh; 85 uint32_t snpsid; 86 uint32_t snpsversion; 87 uint32_t snpsrevision; 88 uint32_t snpsversion_type; 89 #ifdef FDT 90 clk_t clk_ref; 91 clk_t clk_suspend; 92 clk_t clk_bus; 93 #endif 94 }; 95 96 #define DWC3_WRITE(_sc, _off, _val) \ 97 bus_space_write_4(_sc->bst, _sc->bsh, _off, _val) 98 #define DWC3_READ(_sc, _off) \ 99 bus_space_read_4(_sc->bst, _sc->bsh, _off) 100 101 #define IS_DMA_32B 1 102 103 static void 104 xhci_interrupt_poll(void *_sc) 105 { 106 struct xhci_softc *sc = _sc; 107 108 USB_BUS_UNLOCK(&sc->sc_bus); 109 xhci_interrupt(sc); 110 USB_BUS_LOCK(&sc->sc_bus); 111 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 112 } 113 114 static int 115 snps_dwc3_attach_xhci(device_t dev) 116 { 117 struct snps_dwc3_softc *snps_sc = device_get_softc(dev); 118 struct xhci_softc *sc = &snps_sc->sc; 119 int err = 0, rid = 0; 120 121 sc->sc_io_res = snps_sc->mem_res; 122 sc->sc_io_tag = snps_sc->bst; 123 sc->sc_io_hdl = snps_sc->bsh; 124 sc->sc_io_size = rman_get_size(snps_sc->mem_res); 125 126 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 127 RF_SHAREABLE | RF_ACTIVE); 128 if (sc->sc_irq_res == NULL) { 129 device_printf(dev, "Failed to allocate IRQ\n"); 130 return (ENXIO); 131 } 132 133 sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); 134 if (sc->sc_bus.bdev == NULL) { 135 device_printf(dev, "Failed to add USB device\n"); 136 return (ENXIO); 137 } 138 139 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 140 141 sprintf(sc->sc_vendor, "Synopsys"); 142 device_set_desc(sc->sc_bus.bdev, "Synopsys"); 143 144 if (xhci_use_polling() == 0) { 145 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 146 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 147 if (err != 0) { 148 device_printf(dev, "Failed to setup IRQ, %d\n", err); 149 sc->sc_intr_hdl = NULL; 150 return (err); 151 } 152 } 153 154 err = xhci_init(sc, dev, IS_DMA_32B); 155 if (err != 0) { 156 device_printf(dev, "Failed to init XHCI, with error %d\n", err); 157 return (ENXIO); 158 } 159 160 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); 161 162 if (xhci_use_polling() != 0) { 163 device_printf(dev, "Interrupt polling at %dHz\n", hz); 164 USB_BUS_LOCK(&sc->sc_bus); 165 xhci_interrupt_poll(sc); 166 USB_BUS_UNLOCK(&sc->sc_bus); 167 } 168 169 err = xhci_start_controller(sc); 170 if (err != 0) { 171 device_printf(dev, "Failed to start XHCI controller, with error %d\n", err); 172 return (ENXIO); 173 } 174 175 device_printf(sc->sc_bus.bdev, "trying to attach\n"); 176 err = device_probe_and_attach(sc->sc_bus.bdev); 177 if (err != 0) { 178 device_printf(dev, "Failed to initialize USB, with error %d\n", err); 179 return (ENXIO); 180 } 181 182 return (0); 183 } 184 185 #ifdef DWC3_DEBUG 186 static void 187 snsp_dwc3_dump_regs(struct snps_dwc3_softc *sc, const char *msg) 188 { 189 struct xhci_softc *xsc; 190 uint32_t reg; 191 192 if (!bootverbose) 193 return; 194 195 device_printf(sc->dev, "%s: %s:\n", __func__, msg ? msg : ""); 196 197 reg = DWC3_READ(sc, DWC3_GCTL); 198 device_printf(sc->dev, "GCTL: %#012x\n", reg); 199 reg = DWC3_READ(sc, DWC3_GUCTL); 200 device_printf(sc->dev, "GUCTL: %#012x\n", reg); 201 reg = DWC3_READ(sc, DWC3_GUCTL1); 202 device_printf(sc->dev, "GUCTL1: %#012x\n", reg); 203 reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); 204 device_printf(sc->dev, "GUSB2PHYCFG0: %#012x\n", reg); 205 reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); 206 device_printf(sc->dev, "GUSB3PIPECTL0: %#012x\n", reg); 207 reg = DWC3_READ(sc, DWC3_DCFG); 208 device_printf(sc->dev, "DCFG: %#012x\n", reg); 209 210 xsc = &sc->sc; 211 device_printf(sc->dev, "xhci quirks: %#012x\n", xsc->sc_quirks); 212 } 213 214 static void 215 snps_dwc3_dump_ctrlparams(struct snps_dwc3_softc *sc) 216 { 217 const bus_size_t offs[] = { 218 DWC3_GHWPARAMS0, DWC3_GHWPARAMS1, DWC3_GHWPARAMS2, DWC3_GHWPARAMS3, 219 DWC3_GHWPARAMS4, DWC3_GHWPARAMS5, DWC3_GHWPARAMS6, DWC3_GHWPARAMS7, 220 DWC3_GHWPARAMS8, 221 }; 222 uint32_t reg; 223 int i; 224 225 for (i = 0; i < nitems(offs); i++) { 226 reg = DWC3_READ(sc, offs[i]); 227 if (bootverbose) 228 device_printf(sc->dev, "hwparams[%d]: %#012x\n", i, reg); 229 } 230 } 231 #endif 232 233 static void 234 snps_dwc3_reset(struct snps_dwc3_softc *sc) 235 { 236 uint32_t gctl, ghwp0, phy2, phy3; 237 238 ghwp0 = DWC3_READ(sc, DWC3_GHWPARAMS0); 239 240 gctl = DWC3_READ(sc, DWC3_GCTL); 241 gctl |= DWC3_GCTL_CORESOFTRESET; 242 DWC3_WRITE(sc, DWC3_GCTL, gctl); 243 244 phy2 = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); 245 phy2 |= DWC3_GUSB2PHYCFG0_PHYSOFTRST; 246 if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == 247 DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) 248 phy2 &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20; 249 DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2); 250 251 phy3 = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); 252 phy3 |= DWC3_GUSB3PIPECTL0_PHYSOFTRST; 253 if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == 254 DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) 255 phy3 &= ~DWC3_GUSB3PIPECTL0_SUSPENDUSB3; 256 DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3); 257 258 DELAY(1000); 259 260 phy2 &= ~DWC3_GUSB2PHYCFG0_PHYSOFTRST; 261 DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2); 262 263 phy3 &= ~DWC3_GUSB3PIPECTL0_PHYSOFTRST; 264 DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3); 265 266 gctl &= ~DWC3_GCTL_CORESOFTRESET; 267 DWC3_WRITE(sc, DWC3_GCTL, gctl); 268 269 } 270 271 static void 272 snps_dwc3_configure_host(struct snps_dwc3_softc *sc) 273 { 274 uint32_t reg; 275 276 reg = DWC3_READ(sc, DWC3_GCTL); 277 reg &= ~DWC3_GCTL_PRTCAPDIR_MASK; 278 reg |= DWC3_GCTL_PRTCAPDIR_HOST; 279 DWC3_WRITE(sc, DWC3_GCTL, reg); 280 281 /* 282 * Enable the Host IN Auto Retry feature, making the 283 * host respond with a non-terminating retry ACK. 284 * XXX If we ever support more than host mode this needs a dr_mode check. 285 */ 286 reg = DWC3_READ(sc, DWC3_GUCTL); 287 reg |= DWC3_GUCTL_HOST_AUTO_RETRY; 288 DWC3_WRITE(sc, DWC3_GUCTL, reg); 289 } 290 291 #ifdef FDT 292 static void 293 snps_dwc3_configure_phy(struct snps_dwc3_softc *sc, phandle_t node) 294 { 295 char *phy_type; 296 uint32_t reg; 297 int nphy_types; 298 299 phy_type = NULL; 300 nphy_types = OF_getprop_alloc(node, "phy_type", (void **)&phy_type); 301 if (nphy_types <= 0) 302 return; 303 304 reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); 305 if (strncmp(phy_type, "utmi_wide", 9) == 0) { 306 reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf)); 307 reg |= DWC3_GUSB2PHYCFG0_PHYIF | 308 DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_16BITS); 309 } else { 310 reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf)); 311 reg |= DWC3_GUSB2PHYCFG0_PHYIF | 312 DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_8BITS); 313 } 314 DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg); 315 OF_prop_free(phy_type); 316 } 317 #endif 318 319 static void 320 snps_dwc3_do_quirks(struct snps_dwc3_softc *sc) 321 { 322 struct xhci_softc *xsc; 323 uint32_t ghwp0, reg; 324 325 ghwp0 = DWC3_READ(sc, DWC3_GHWPARAMS0); 326 reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); 327 if (device_has_property(sc->dev, "snps,dis-u2-freeclk-exists-quirk")) 328 reg &= ~DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; 329 else 330 reg |= DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; 331 if (device_has_property(sc->dev, "snps,dis_u2_susphy_quirk")) 332 reg &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20; 333 else if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == 334 DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) 335 reg |= DWC3_GUSB2PHYCFG0_SUSPENDUSB20; 336 if (device_has_property(sc->dev, "snps,dis_enblslpm_quirk")) 337 reg &= ~DWC3_GUSB2PHYCFG0_ENBLSLPM; 338 else 339 reg |= DWC3_GUSB2PHYCFG0_ENBLSLPM; 340 DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg); 341 342 reg = DWC3_READ(sc, DWC3_GUCTL1); 343 if (device_has_property(sc->dev, "snps,dis-tx-ipgap-linecheck-quirk")) 344 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 345 DWC3_WRITE(sc, DWC3_GUCTL1, reg); 346 347 reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); 348 if (device_has_property(sc->dev, "snps,dis-del-phy-power-chg-quirk")) 349 reg &= ~DWC3_GUSB3PIPECTL0_DELAYP1TRANS; 350 if (device_has_property(sc->dev, "snps,dis_rxdet_inp3_quirk")) 351 reg |= DWC3_GUSB3PIPECTL0_DISRXDETINP3; 352 if (device_has_property(sc->dev, "snps,dis_u3_susphy_quirk")) 353 reg &= ~DWC3_GUSB3PIPECTL0_SUSPENDUSB3; 354 else if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == 355 DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) 356 reg |= DWC3_GUSB3PIPECTL0_SUSPENDUSB3; 357 DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, reg); 358 359 /* Port Disable does not work on <= 3.00a. Disable PORT_PED. */ 360 if ((sc->snpsid & 0xffff) <= 0x300a) { 361 xsc = &sc->sc; 362 xsc->sc_quirks |= XHCI_QUIRK_DISABLE_PORT_PED; 363 } 364 } 365 366 static int 367 snps_dwc3_probe_common(device_t dev) 368 { 369 char dr_mode[16] = { 0 }; 370 ssize_t s; 371 372 s = device_get_property(dev, "dr_mode", dr_mode, sizeof(dr_mode), 373 DEVICE_PROP_BUFFER); 374 if (s == -1) { 375 device_printf(dev, "Cannot determine dr_mode\n"); 376 return (ENXIO); 377 } 378 if (strcmp(dr_mode, "host") != 0) { 379 device_printf(dev, 380 "Found dr_mode '%s' but only 'host' supported. s=%zd\n", 381 dr_mode, s); 382 return (ENXIO); 383 } 384 385 device_set_desc(dev, "Synopsys Designware DWC3"); 386 return (BUS_PROBE_DEFAULT); 387 } 388 389 static int 390 snps_dwc3_common_attach(device_t dev, bool is_fdt) 391 { 392 struct snps_dwc3_softc *sc; 393 #ifdef FDT 394 phandle_t node; 395 phy_t usb2_phy, usb3_phy; 396 uint32_t reg; 397 #endif 398 int error, rid; 399 400 sc = device_get_softc(dev); 401 sc->dev = dev; 402 403 rid = 0; 404 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 405 RF_ACTIVE); 406 if (sc->mem_res == NULL) { 407 device_printf(dev, "Failed to map memory\n"); 408 return (ENXIO); 409 } 410 sc->bst = rman_get_bustag(sc->mem_res); 411 sc->bsh = rman_get_bushandle(sc->mem_res); 412 413 sc->snpsid = DWC3_READ(sc, DWC3_GSNPSID); 414 sc->snpsversion = DWC3_VERSION(sc->snpsid); 415 sc->snpsrevision = DWC3_REVISION(sc->snpsid); 416 if (sc->snpsversion == DWC3_1_IP_ID || 417 sc->snpsversion == DWC3_2_IP_ID) { 418 sc->snpsrevision = DWC3_READ(sc, DWC3_1_VER_NUMBER); 419 sc->snpsversion_type = DWC3_READ(sc, DWC3_1_VER_TYPE); 420 } 421 if (bootverbose) { 422 switch (sc->snpsversion) { 423 case DWC3_IP_ID: 424 device_printf(sc->dev, "SNPS Version: DWC3 (%x %x)\n", 425 sc->snpsversion, sc->snpsrevision); 426 break; 427 case DWC3_1_IP_ID: 428 device_printf(sc->dev, "SNPS Version: DWC3.1 (%x %x %x)\n", 429 sc->snpsversion, sc->snpsrevision, 430 sc->snpsversion_type); 431 break; 432 case DWC3_2_IP_ID: 433 device_printf(sc->dev, "SNPS Version: DWC3.2 (%x %x %x)\n", 434 sc->snpsversion, sc->snpsrevision, 435 sc->snpsversion_type); 436 break; 437 } 438 } 439 #ifdef DWC3_DEBUG 440 snps_dwc3_dump_ctrlparams(sc); 441 #endif 442 443 #ifdef FDT 444 if (!is_fdt) 445 goto skip_phys; 446 447 node = ofw_bus_get_node(dev); 448 449 /* Get the clocks if any */ 450 if (ofw_bus_is_compatible(dev, "rockchip,rk3328-dwc3") == 1 || 451 ofw_bus_is_compatible(dev, "rockchip,rk3568-dwc3") == 1) { 452 if (clk_get_by_ofw_name(dev, node, "ref_clk", &sc->clk_ref) != 0) 453 device_printf(dev, "Cannot get ref_clk\n"); 454 if (clk_get_by_ofw_name(dev, node, "suspend_clk", &sc->clk_suspend) != 0) 455 device_printf(dev, "Cannot get suspend_clk\n"); 456 if (clk_get_by_ofw_name(dev, node, "bus_clk", &sc->clk_bus) != 0) 457 device_printf(dev, "Cannot get bus_clk\n"); 458 } 459 460 if (sc->clk_ref != NULL) { 461 if (clk_enable(sc->clk_ref) != 0) 462 device_printf(dev, "Cannot enable ref_clk\n"); 463 } 464 if (sc->clk_suspend != NULL) { 465 if (clk_enable(sc->clk_suspend) != 0) 466 device_printf(dev, "Cannot enable suspend_clk\n"); 467 } 468 if (sc->clk_bus != NULL) { 469 if (clk_enable(sc->clk_bus) != 0) 470 device_printf(dev, "Cannot enable bus_clk\n"); 471 } 472 473 /* Get the phys */ 474 usb2_phy = usb3_phy = NULL; 475 error = phy_get_by_ofw_name(dev, node, "usb2-phy", &usb2_phy); 476 if (error == 0 && usb2_phy != NULL) 477 phy_enable(usb2_phy); 478 error = phy_get_by_ofw_name(dev, node, "usb3-phy", &usb3_phy); 479 if (error == 0 && usb3_phy != NULL) 480 phy_enable(usb3_phy); 481 if (sc->snpsversion == DWC3_IP_ID) { 482 if (sc->snpsrevision >= 0x290A) { 483 uint32_t hwparams3; 484 485 hwparams3 = DWC3_READ(sc, DWC3_GHWPARAMS3); 486 if (DWC3_HWPARAMS3_SSPHY(hwparams3) == DWC3_HWPARAMS3_SSPHY_DISABLE) { 487 reg = DWC3_READ(sc, DWC3_GUCTL1); 488 if (bootverbose) 489 device_printf(dev, "Forcing USB2 clock only\n"); 490 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 491 DWC3_WRITE(sc, DWC3_GUCTL1, reg); 492 } 493 } 494 } 495 snps_dwc3_configure_phy(sc, node); 496 skip_phys: 497 #endif 498 499 snps_dwc3_reset(sc); 500 snps_dwc3_configure_host(sc); 501 snps_dwc3_do_quirks(sc); 502 503 #ifdef DWC3_DEBUG 504 snsp_dwc3_dump_regs(sc, "Pre XHCI init"); 505 #endif 506 error = snps_dwc3_attach_xhci(dev); 507 #ifdef DWC3_DEBUG 508 snsp_dwc3_dump_regs(sc, "Post XHCI init"); 509 #endif 510 511 #ifdef FDT 512 if (error) { 513 if (sc->clk_ref != NULL) 514 clk_disable(sc->clk_ref); 515 if (sc->clk_suspend != NULL) 516 clk_disable(sc->clk_suspend); 517 if (sc->clk_bus != NULL) 518 clk_disable(sc->clk_bus); 519 } 520 #endif 521 return (error); 522 } 523 524 #ifdef FDT 525 static struct ofw_compat_data compat_data[] = { 526 { "snps,dwc3", 1 }, 527 { NULL, 0 } 528 }; 529 530 static int 531 snps_dwc3_fdt_probe(device_t dev) 532 { 533 534 if (!ofw_bus_status_okay(dev)) 535 return (ENXIO); 536 537 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 538 return (ENXIO); 539 540 return (snps_dwc3_probe_common(dev)); 541 } 542 543 static int 544 snps_dwc3_fdt_attach(device_t dev) 545 { 546 547 return (snps_dwc3_common_attach(dev, true)); 548 } 549 550 static device_method_t snps_dwc3_fdt_methods[] = { 551 /* Device interface */ 552 DEVMETHOD(device_probe, snps_dwc3_fdt_probe), 553 DEVMETHOD(device_attach, snps_dwc3_fdt_attach), 554 555 DEVMETHOD_END 556 }; 557 558 DEFINE_CLASS_1(snps_dwc3_fdt, snps_dwc3_fdt_driver, snps_dwc3_fdt_methods, 559 sizeof(struct snps_dwc3_softc), generic_xhci_driver); 560 561 DRIVER_MODULE(snps_dwc3_fdt, simplebus, snps_dwc3_fdt_driver, 0, 0); 562 MODULE_DEPEND(snps_dwc3_fdt, xhci, 1, 1, 1); 563 #endif 564 565 #ifdef DEV_ACPI 566 static char *dwc3_acpi_ids[] = { 567 "808622B7", /* This was an Intel PCI Vendor/Device ID used. */ 568 "PNP0D10", /* The generic XHCI PNP ID needing extra probe checks. */ 569 NULL 570 }; 571 572 static int 573 snps_dwc3_acpi_probe(device_t dev) 574 { 575 char *match; 576 int error; 577 578 if (acpi_disabled("snps_dwc3")) 579 return (ENXIO); 580 581 error = ACPI_ID_PROBE(device_get_parent(dev), dev, dwc3_acpi_ids, &match); 582 if (error > 0) 583 return (ENXIO); 584 585 /* 586 * If we found the Generic XHCI PNP ID we can only attach if we have 587 * some other means to identify the device as dwc3. 588 */ 589 if (strcmp(match, "PNP0D10") == 0) { 590 /* This is needed in SolidRun's HoneyComb. */ 591 if (device_has_property(dev, "snps,dis_rxdet_inp3_quirk")) 592 goto is_dwc3; 593 594 return (ENXIO); 595 } 596 597 is_dwc3: 598 return (snps_dwc3_probe_common(dev)); 599 } 600 601 static int 602 snps_dwc3_acpi_attach(device_t dev) 603 { 604 605 return (snps_dwc3_common_attach(dev, false)); 606 } 607 608 static device_method_t snps_dwc3_acpi_methods[] = { 609 /* Device interface */ 610 DEVMETHOD(device_probe, snps_dwc3_acpi_probe), 611 DEVMETHOD(device_attach, snps_dwc3_acpi_attach), 612 613 DEVMETHOD_END 614 }; 615 616 DEFINE_CLASS_1(snps_dwc3_acpi, snps_dwc3_acpi_driver, snps_dwc3_acpi_methods, 617 sizeof(struct snps_dwc3_softc), generic_xhci_driver); 618 619 DRIVER_MODULE(snps_dwc3_acpi, acpi, snps_dwc3_acpi_driver, 0, 0); 620 MODULE_DEPEND(snps_dwc3_acpi, usb, 1, 1, 1); 621 #endif 622