1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 Sam Leffler, Errno Consulting 5 * Copyright (c) 2003 Global Technology Associates, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * SafeNet SafeXcel-1141 hardware crypto accelerator 35 */ 36 #include "opt_safe.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/proc.h> 41 #include <sys/errno.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/mbuf.h> 45 #include <sys/module.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/sysctl.h> 49 #include <sys/endian.h> 50 #include <sys/uio.h> 51 52 #include <vm/vm.h> 53 #include <vm/pmap.h> 54 55 #include <machine/bus.h> 56 #include <machine/resource.h> 57 #include <sys/bus.h> 58 #include <sys/rman.h> 59 60 #include <opencrypto/cryptodev.h> 61 #include <opencrypto/xform_auth.h> 62 #include <sys/random.h> 63 #include <sys/kobj.h> 64 65 #include "cryptodev_if.h" 66 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcireg.h> 69 70 #ifdef SAFE_RNDTEST 71 #include <dev/rndtest/rndtest.h> 72 #endif 73 #include <dev/safe/safereg.h> 74 #include <dev/safe/safevar.h> 75 76 #ifndef bswap32 77 #define bswap32 NTOHL 78 #endif 79 80 /* 81 * Prototypes and count for the pci_device structure 82 */ 83 static int safe_probe(device_t); 84 static int safe_attach(device_t); 85 static int safe_detach(device_t); 86 static int safe_suspend(device_t); 87 static int safe_resume(device_t); 88 static int safe_shutdown(device_t); 89 90 static int safe_probesession(device_t, const struct crypto_session_params *); 91 static int safe_newsession(device_t, crypto_session_t, 92 const struct crypto_session_params *); 93 static int safe_process(device_t, struct cryptop *, int); 94 95 static device_method_t safe_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, safe_probe), 98 DEVMETHOD(device_attach, safe_attach), 99 DEVMETHOD(device_detach, safe_detach), 100 DEVMETHOD(device_suspend, safe_suspend), 101 DEVMETHOD(device_resume, safe_resume), 102 DEVMETHOD(device_shutdown, safe_shutdown), 103 104 /* crypto device methods */ 105 DEVMETHOD(cryptodev_probesession, safe_probesession), 106 DEVMETHOD(cryptodev_newsession, safe_newsession), 107 DEVMETHOD(cryptodev_process, safe_process), 108 109 DEVMETHOD_END 110 }; 111 static driver_t safe_driver = { 112 "safe", 113 safe_methods, 114 sizeof (struct safe_softc) 115 }; 116 static devclass_t safe_devclass; 117 118 DRIVER_MODULE(safe, pci, safe_driver, safe_devclass, 0, 0); 119 MODULE_DEPEND(safe, crypto, 1, 1, 1); 120 #ifdef SAFE_RNDTEST 121 MODULE_DEPEND(safe, rndtest, 1, 1, 1); 122 #endif 123 124 static void safe_intr(void *); 125 static void safe_callback(struct safe_softc *, struct safe_ringentry *); 126 static void safe_feed(struct safe_softc *, struct safe_ringentry *); 127 static void safe_mcopy(struct mbuf *, struct mbuf *, u_int); 128 #ifndef SAFE_NO_RNG 129 static void safe_rng_init(struct safe_softc *); 130 static void safe_rng(void *); 131 #endif /* SAFE_NO_RNG */ 132 static int safe_dma_malloc(struct safe_softc *, bus_size_t, 133 struct safe_dma_alloc *, int); 134 #define safe_dma_sync(_dma, _flags) \ 135 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 136 static void safe_dma_free(struct safe_softc *, struct safe_dma_alloc *); 137 static int safe_dmamap_aligned(const struct safe_operand *); 138 static int safe_dmamap_uniform(const struct safe_operand *); 139 140 static void safe_reset_board(struct safe_softc *); 141 static void safe_init_board(struct safe_softc *); 142 static void safe_init_pciregs(device_t dev); 143 static void safe_cleanchip(struct safe_softc *); 144 static void safe_totalreset(struct safe_softc *); 145 146 static int safe_free_entry(struct safe_softc *, struct safe_ringentry *); 147 148 static SYSCTL_NODE(_hw, OID_AUTO, safe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 149 "SafeNet driver parameters"); 150 151 #ifdef SAFE_DEBUG 152 static void safe_dump_dmastatus(struct safe_softc *, const char *); 153 static void safe_dump_ringstate(struct safe_softc *, const char *); 154 static void safe_dump_intrstate(struct safe_softc *, const char *); 155 static void safe_dump_request(struct safe_softc *, const char *, 156 struct safe_ringentry *); 157 158 static struct safe_softc *safec; /* for use by hw.safe.dump */ 159 160 static int safe_debug = 0; 161 SYSCTL_INT(_hw_safe, OID_AUTO, debug, CTLFLAG_RW, &safe_debug, 162 0, "control debugging msgs"); 163 #define DPRINTF(_x) if (safe_debug) printf _x 164 #else 165 #define DPRINTF(_x) 166 #endif 167 168 #define READ_REG(sc,r) \ 169 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 170 171 #define WRITE_REG(sc,reg,val) \ 172 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 173 174 struct safe_stats safestats; 175 SYSCTL_STRUCT(_hw_safe, OID_AUTO, stats, CTLFLAG_RD, &safestats, 176 safe_stats, "driver statistics"); 177 #ifndef SAFE_NO_RNG 178 static int safe_rnginterval = 1; /* poll once a second */ 179 SYSCTL_INT(_hw_safe, OID_AUTO, rnginterval, CTLFLAG_RW, &safe_rnginterval, 180 0, "RNG polling interval (secs)"); 181 static int safe_rngbufsize = 16; /* 64 bytes each poll */ 182 SYSCTL_INT(_hw_safe, OID_AUTO, rngbufsize, CTLFLAG_RW, &safe_rngbufsize, 183 0, "RNG polling buffer size (32-bit words)"); 184 static int safe_rngmaxalarm = 8; /* max alarms before reset */ 185 SYSCTL_INT(_hw_safe, OID_AUTO, rngmaxalarm, CTLFLAG_RW, &safe_rngmaxalarm, 186 0, "RNG max alarms before reset"); 187 #endif /* SAFE_NO_RNG */ 188 189 static int 190 safe_probe(device_t dev) 191 { 192 if (pci_get_vendor(dev) == PCI_VENDOR_SAFENET && 193 pci_get_device(dev) == PCI_PRODUCT_SAFEXCEL) 194 return (BUS_PROBE_DEFAULT); 195 return (ENXIO); 196 } 197 198 static const char* 199 safe_partname(struct safe_softc *sc) 200 { 201 /* XXX sprintf numbers when not decoded */ 202 switch (pci_get_vendor(sc->sc_dev)) { 203 case PCI_VENDOR_SAFENET: 204 switch (pci_get_device(sc->sc_dev)) { 205 case PCI_PRODUCT_SAFEXCEL: return "SafeNet SafeXcel-1141"; 206 } 207 return "SafeNet unknown-part"; 208 } 209 return "Unknown-vendor unknown-part"; 210 } 211 212 #ifndef SAFE_NO_RNG 213 static void 214 default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 215 { 216 /* MarkM: FIX!! Check that this does not swamp the harvester! */ 217 random_harvest_queue(buf, count, RANDOM_PURE_SAFE); 218 } 219 #endif /* SAFE_NO_RNG */ 220 221 static int 222 safe_attach(device_t dev) 223 { 224 struct safe_softc *sc = device_get_softc(dev); 225 u_int32_t raddr; 226 u_int32_t i; 227 int rid; 228 229 bzero(sc, sizeof (*sc)); 230 sc->sc_dev = dev; 231 232 /* XXX handle power management */ 233 234 pci_enable_busmaster(dev); 235 236 /* 237 * Setup memory-mapping of PCI registers. 238 */ 239 rid = BS_BAR; 240 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 241 RF_ACTIVE); 242 if (sc->sc_sr == NULL) { 243 device_printf(dev, "cannot map register space\n"); 244 goto bad; 245 } 246 sc->sc_st = rman_get_bustag(sc->sc_sr); 247 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 248 249 /* 250 * Arrange interrupt line. 251 */ 252 rid = 0; 253 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 254 RF_SHAREABLE|RF_ACTIVE); 255 if (sc->sc_irq == NULL) { 256 device_printf(dev, "could not map interrupt\n"); 257 goto bad1; 258 } 259 /* 260 * NB: Network code assumes we are blocked with splimp() 261 * so make sure the IRQ is mapped appropriately. 262 */ 263 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 264 NULL, safe_intr, sc, &sc->sc_ih)) { 265 device_printf(dev, "could not establish interrupt\n"); 266 goto bad2; 267 } 268 269 sc->sc_cid = crypto_get_driverid(dev, sizeof(struct safe_session), 270 CRYPTOCAP_F_HARDWARE); 271 if (sc->sc_cid < 0) { 272 device_printf(dev, "could not get crypto driver id\n"); 273 goto bad3; 274 } 275 276 sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & 277 (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); 278 279 /* 280 * Setup DMA descriptor area. 281 */ 282 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 283 1, /* alignment */ 284 SAFE_DMA_BOUNDARY, /* boundary */ 285 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 286 BUS_SPACE_MAXADDR, /* highaddr */ 287 NULL, NULL, /* filter, filterarg */ 288 SAFE_MAX_DMA, /* maxsize */ 289 SAFE_MAX_PART, /* nsegments */ 290 SAFE_MAX_SSIZE, /* maxsegsize */ 291 BUS_DMA_ALLOCNOW, /* flags */ 292 NULL, NULL, /* locking */ 293 &sc->sc_srcdmat)) { 294 device_printf(dev, "cannot allocate DMA tag\n"); 295 goto bad4; 296 } 297 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 298 1, /* alignment */ 299 SAFE_MAX_DSIZE, /* boundary */ 300 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 301 BUS_SPACE_MAXADDR, /* highaddr */ 302 NULL, NULL, /* filter, filterarg */ 303 SAFE_MAX_DMA, /* maxsize */ 304 SAFE_MAX_PART, /* nsegments */ 305 SAFE_MAX_DSIZE, /* maxsegsize */ 306 BUS_DMA_ALLOCNOW, /* flags */ 307 NULL, NULL, /* locking */ 308 &sc->sc_dstdmat)) { 309 device_printf(dev, "cannot allocate DMA tag\n"); 310 goto bad4; 311 } 312 313 /* 314 * Allocate packet engine descriptors. 315 */ 316 if (safe_dma_malloc(sc, 317 SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), 318 &sc->sc_ringalloc, 0)) { 319 device_printf(dev, "cannot allocate PE descriptor ring\n"); 320 bus_dma_tag_destroy(sc->sc_srcdmat); 321 goto bad4; 322 } 323 /* 324 * Hookup the static portion of all our data structures. 325 */ 326 sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; 327 sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; 328 sc->sc_front = sc->sc_ring; 329 sc->sc_back = sc->sc_ring; 330 raddr = sc->sc_ringalloc.dma_paddr; 331 bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); 332 for (i = 0; i < SAFE_MAX_NQUEUE; i++) { 333 struct safe_ringentry *re = &sc->sc_ring[i]; 334 335 re->re_desc.d_sa = raddr + 336 offsetof(struct safe_ringentry, re_sa); 337 re->re_sa.sa_staterec = raddr + 338 offsetof(struct safe_ringentry, re_sastate); 339 340 raddr += sizeof (struct safe_ringentry); 341 } 342 mtx_init(&sc->sc_ringmtx, device_get_nameunit(dev), 343 "packet engine ring", MTX_DEF); 344 345 /* 346 * Allocate scatter and gather particle descriptors. 347 */ 348 if (safe_dma_malloc(sc, SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), 349 &sc->sc_spalloc, 0)) { 350 device_printf(dev, "cannot allocate source particle " 351 "descriptor ring\n"); 352 mtx_destroy(&sc->sc_ringmtx); 353 safe_dma_free(sc, &sc->sc_ringalloc); 354 bus_dma_tag_destroy(sc->sc_srcdmat); 355 goto bad4; 356 } 357 sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; 358 sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; 359 sc->sc_spfree = sc->sc_spring; 360 bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); 361 362 if (safe_dma_malloc(sc, SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), 363 &sc->sc_dpalloc, 0)) { 364 device_printf(dev, "cannot allocate destination particle " 365 "descriptor ring\n"); 366 mtx_destroy(&sc->sc_ringmtx); 367 safe_dma_free(sc, &sc->sc_spalloc); 368 safe_dma_free(sc, &sc->sc_ringalloc); 369 bus_dma_tag_destroy(sc->sc_dstdmat); 370 goto bad4; 371 } 372 sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; 373 sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; 374 sc->sc_dpfree = sc->sc_dpring; 375 bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); 376 377 device_printf(sc->sc_dev, "%s", safe_partname(sc)); 378 379 sc->sc_devinfo = READ_REG(sc, SAFE_DEVINFO); 380 if (sc->sc_devinfo & SAFE_DEVINFO_RNG) { 381 sc->sc_flags |= SAFE_FLAGS_RNG; 382 printf(" rng"); 383 } 384 if (sc->sc_devinfo & SAFE_DEVINFO_PKEY) { 385 #if 0 386 printf(" key"); 387 sc->sc_flags |= SAFE_FLAGS_KEY; 388 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); 389 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); 390 #endif 391 } 392 if (sc->sc_devinfo & SAFE_DEVINFO_DES) { 393 printf(" des/3des"); 394 } 395 if (sc->sc_devinfo & SAFE_DEVINFO_AES) { 396 printf(" aes"); 397 } 398 if (sc->sc_devinfo & SAFE_DEVINFO_MD5) { 399 printf(" md5"); 400 } 401 if (sc->sc_devinfo & SAFE_DEVINFO_SHA1) { 402 printf(" sha1"); 403 } 404 /* XXX other supported algorithms */ 405 printf("\n"); 406 407 safe_reset_board(sc); /* reset h/w */ 408 safe_init_pciregs(dev); /* init pci settings */ 409 safe_init_board(sc); /* init h/w */ 410 411 #ifndef SAFE_NO_RNG 412 if (sc->sc_flags & SAFE_FLAGS_RNG) { 413 #ifdef SAFE_RNDTEST 414 sc->sc_rndtest = rndtest_attach(dev); 415 if (sc->sc_rndtest) 416 sc->sc_harvest = rndtest_harvest; 417 else 418 sc->sc_harvest = default_harvest; 419 #else 420 sc->sc_harvest = default_harvest; 421 #endif 422 safe_rng_init(sc); 423 424 callout_init(&sc->sc_rngto, 1); 425 callout_reset(&sc->sc_rngto, hz*safe_rnginterval, safe_rng, sc); 426 } 427 #endif /* SAFE_NO_RNG */ 428 #ifdef SAFE_DEBUG 429 safec = sc; /* for use by hw.safe.dump */ 430 #endif 431 return (0); 432 bad4: 433 crypto_unregister_all(sc->sc_cid); 434 bad3: 435 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 436 bad2: 437 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 438 bad1: 439 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 440 bad: 441 return (ENXIO); 442 } 443 444 /* 445 * Detach a device that successfully probed. 446 */ 447 static int 448 safe_detach(device_t dev) 449 { 450 struct safe_softc *sc = device_get_softc(dev); 451 452 /* XXX wait/abort active ops */ 453 454 WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ 455 456 callout_stop(&sc->sc_rngto); 457 458 crypto_unregister_all(sc->sc_cid); 459 460 #ifdef SAFE_RNDTEST 461 if (sc->sc_rndtest) 462 rndtest_detach(sc->sc_rndtest); 463 #endif 464 465 safe_cleanchip(sc); 466 safe_dma_free(sc, &sc->sc_dpalloc); 467 safe_dma_free(sc, &sc->sc_spalloc); 468 mtx_destroy(&sc->sc_ringmtx); 469 safe_dma_free(sc, &sc->sc_ringalloc); 470 471 bus_generic_detach(dev); 472 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 473 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 474 475 bus_dma_tag_destroy(sc->sc_srcdmat); 476 bus_dma_tag_destroy(sc->sc_dstdmat); 477 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 478 479 return (0); 480 } 481 482 /* 483 * Stop all chip i/o so that the kernel's probe routines don't 484 * get confused by errant DMAs when rebooting. 485 */ 486 static int 487 safe_shutdown(device_t dev) 488 { 489 #ifdef notyet 490 safe_stop(device_get_softc(dev)); 491 #endif 492 return (0); 493 } 494 495 /* 496 * Device suspend routine. 497 */ 498 static int 499 safe_suspend(device_t dev) 500 { 501 struct safe_softc *sc = device_get_softc(dev); 502 503 #ifdef notyet 504 /* XXX stop the device and save PCI settings */ 505 #endif 506 sc->sc_suspended = 1; 507 508 return (0); 509 } 510 511 static int 512 safe_resume(device_t dev) 513 { 514 struct safe_softc *sc = device_get_softc(dev); 515 516 #ifdef notyet 517 /* XXX retore PCI settings and start the device */ 518 #endif 519 sc->sc_suspended = 0; 520 return (0); 521 } 522 523 /* 524 * SafeXcel Interrupt routine 525 */ 526 static void 527 safe_intr(void *arg) 528 { 529 struct safe_softc *sc = arg; 530 volatile u_int32_t stat; 531 532 stat = READ_REG(sc, SAFE_HM_STAT); 533 if (stat == 0) /* shared irq, not for us */ 534 return; 535 536 WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ 537 538 if ((stat & SAFE_INT_PE_DDONE)) { 539 /* 540 * Descriptor(s) done; scan the ring and 541 * process completed operations. 542 */ 543 mtx_lock(&sc->sc_ringmtx); 544 while (sc->sc_back != sc->sc_front) { 545 struct safe_ringentry *re = sc->sc_back; 546 #ifdef SAFE_DEBUG 547 if (safe_debug) { 548 safe_dump_ringstate(sc, __func__); 549 safe_dump_request(sc, __func__, re); 550 } 551 #endif 552 /* 553 * safe_process marks ring entries that were allocated 554 * but not used with a csr of zero. This insures the 555 * ring front pointer never needs to be set backwards 556 * in the event that an entry is allocated but not used 557 * because of a setup error. 558 */ 559 if (re->re_desc.d_csr != 0) { 560 if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) 561 break; 562 if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) 563 break; 564 sc->sc_nqchip--; 565 safe_callback(sc, re); 566 } 567 if (++(sc->sc_back) == sc->sc_ringtop) 568 sc->sc_back = sc->sc_ring; 569 } 570 mtx_unlock(&sc->sc_ringmtx); 571 } 572 573 /* 574 * Check to see if we got any DMA Error 575 */ 576 if (stat & SAFE_INT_PE_ERROR) { 577 DPRINTF(("dmaerr dmastat %08x\n", 578 READ_REG(sc, SAFE_PE_DMASTAT))); 579 safestats.st_dmaerr++; 580 safe_totalreset(sc); 581 #if 0 582 safe_feed(sc); 583 #endif 584 } 585 586 if (sc->sc_needwakeup) { /* XXX check high watermark */ 587 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 588 DPRINTF(("%s: wakeup crypto %x\n", __func__, 589 sc->sc_needwakeup)); 590 sc->sc_needwakeup &= ~wakeup; 591 crypto_unblock(sc->sc_cid, wakeup); 592 } 593 } 594 595 /* 596 * safe_feed() - post a request to chip 597 */ 598 static void 599 safe_feed(struct safe_softc *sc, struct safe_ringentry *re) 600 { 601 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_PREWRITE); 602 if (re->re_dst_map != NULL) 603 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 604 BUS_DMASYNC_PREREAD); 605 /* XXX have no smaller granularity */ 606 safe_dma_sync(&sc->sc_ringalloc, 607 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 608 safe_dma_sync(&sc->sc_spalloc, BUS_DMASYNC_PREWRITE); 609 safe_dma_sync(&sc->sc_dpalloc, BUS_DMASYNC_PREWRITE); 610 611 #ifdef SAFE_DEBUG 612 if (safe_debug) { 613 safe_dump_ringstate(sc, __func__); 614 safe_dump_request(sc, __func__, re); 615 } 616 #endif 617 sc->sc_nqchip++; 618 if (sc->sc_nqchip > safestats.st_maxqchip) 619 safestats.st_maxqchip = sc->sc_nqchip; 620 /* poke h/w to check descriptor ring, any value can be written */ 621 WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); 622 } 623 624 #define N(a) (sizeof(a) / sizeof (a[0])) 625 static void 626 safe_setup_enckey(struct safe_session *ses, const void *key) 627 { 628 int i; 629 630 bcopy(key, ses->ses_key, ses->ses_klen); 631 632 /* PE is little-endian, insure proper byte order */ 633 for (i = 0; i < N(ses->ses_key); i++) 634 ses->ses_key[i] = htole32(ses->ses_key[i]); 635 } 636 637 static void 638 safe_setup_mackey(struct safe_session *ses, int algo, const uint8_t *key, 639 int klen) 640 { 641 MD5_CTX md5ctx; 642 SHA1_CTX sha1ctx; 643 int i; 644 645 if (algo == CRYPTO_MD5_HMAC) { 646 hmac_init_ipad(&auth_hash_hmac_md5, key, klen, &md5ctx); 647 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state)); 648 649 hmac_init_opad(&auth_hash_hmac_md5, key, klen, &md5ctx); 650 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state)); 651 652 explicit_bzero(&md5ctx, sizeof(md5ctx)); 653 } else { 654 hmac_init_ipad(&auth_hash_hmac_sha1, key, klen, &sha1ctx); 655 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); 656 657 hmac_init_opad(&auth_hash_hmac_sha1, key, klen, &sha1ctx); 658 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); 659 660 explicit_bzero(&sha1ctx, sizeof(sha1ctx)); 661 } 662 663 /* PE is little-endian, insure proper byte order */ 664 for (i = 0; i < N(ses->ses_hminner); i++) { 665 ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); 666 ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); 667 } 668 } 669 #undef N 670 671 static bool 672 safe_auth_supported(struct safe_softc *sc, 673 const struct crypto_session_params *csp) 674 { 675 676 switch (csp->csp_auth_alg) { 677 case CRYPTO_MD5_HMAC: 678 if ((sc->sc_devinfo & SAFE_DEVINFO_MD5) == 0) 679 return (false); 680 break; 681 case CRYPTO_SHA1_HMAC: 682 if ((sc->sc_devinfo & SAFE_DEVINFO_SHA1) == 0) 683 return (false); 684 break; 685 default: 686 return (false); 687 } 688 return (true); 689 } 690 691 static bool 692 safe_cipher_supported(struct safe_softc *sc, 693 const struct crypto_session_params *csp) 694 { 695 696 switch (csp->csp_cipher_alg) { 697 case CRYPTO_AES_CBC: 698 if ((sc->sc_devinfo & SAFE_DEVINFO_AES) == 0) 699 return (false); 700 if (csp->csp_ivlen != 16) 701 return (false); 702 if (csp->csp_cipher_klen != 16 && 703 csp->csp_cipher_klen != 24 && 704 csp->csp_cipher_klen != 32) 705 return (false); 706 break; 707 } 708 return (true); 709 } 710 711 static int 712 safe_probesession(device_t dev, const struct crypto_session_params *csp) 713 { 714 struct safe_softc *sc = device_get_softc(dev); 715 716 if (csp->csp_flags != 0) 717 return (EINVAL); 718 switch (csp->csp_mode) { 719 case CSP_MODE_DIGEST: 720 if (!safe_auth_supported(sc, csp)) 721 return (EINVAL); 722 break; 723 case CSP_MODE_CIPHER: 724 if (!safe_cipher_supported(sc, csp)) 725 return (EINVAL); 726 break; 727 case CSP_MODE_ETA: 728 if (!safe_auth_supported(sc, csp) || 729 !safe_cipher_supported(sc, csp)) 730 return (EINVAL); 731 break; 732 default: 733 return (EINVAL); 734 } 735 736 return (CRYPTODEV_PROBE_HARDWARE); 737 } 738 739 /* 740 * Allocate a new 'session'. 741 */ 742 static int 743 safe_newsession(device_t dev, crypto_session_t cses, 744 const struct crypto_session_params *csp) 745 { 746 struct safe_session *ses; 747 748 ses = crypto_get_driver_session(cses); 749 if (csp->csp_cipher_alg != 0) { 750 ses->ses_klen = csp->csp_cipher_klen; 751 if (csp->csp_cipher_key != NULL) 752 safe_setup_enckey(ses, csp->csp_cipher_key); 753 } 754 755 if (csp->csp_auth_alg != 0) { 756 ses->ses_mlen = csp->csp_auth_mlen; 757 if (ses->ses_mlen == 0) { 758 if (csp->csp_auth_alg == CRYPTO_MD5_HMAC) 759 ses->ses_mlen = MD5_HASH_LEN; 760 else 761 ses->ses_mlen = SHA1_HASH_LEN; 762 } 763 764 if (csp->csp_auth_key != NULL) { 765 safe_setup_mackey(ses, csp->csp_auth_alg, 766 csp->csp_auth_key, csp->csp_auth_klen); 767 } 768 } 769 770 return (0); 771 } 772 773 static bus_size_t 774 safe_crp_length(struct cryptop *crp) 775 { 776 777 switch (crp->crp_buf_type) { 778 case CRYPTO_BUF_MBUF: 779 return (crp->crp_mbuf->m_pkthdr.len); 780 case CRYPTO_BUF_UIO: 781 return (crp->crp_uio->uio_resid); 782 case CRYPTO_BUF_CONTIG: 783 return (crp->crp_ilen); 784 default: 785 panic("bad crp buffer type"); 786 } 787 } 788 789 static void 790 safe_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, int error) 791 { 792 struct safe_operand *op = arg; 793 794 DPRINTF(("%s: nsegs %d error %d\n", __func__, 795 nsegs, error)); 796 if (error != 0) 797 return; 798 op->nsegs = nsegs; 799 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 800 } 801 802 static int 803 safe_process(device_t dev, struct cryptop *crp, int hint) 804 { 805 struct safe_softc *sc = device_get_softc(dev); 806 const struct crypto_session_params *csp; 807 int err = 0, i, nicealign, uniform; 808 int bypass, oplen; 809 int16_t coffset; 810 struct safe_session *ses; 811 struct safe_ringentry *re; 812 struct safe_sarec *sa; 813 struct safe_pdesc *pd; 814 u_int32_t cmd0, cmd1, staterec; 815 816 mtx_lock(&sc->sc_ringmtx); 817 if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { 818 safestats.st_ringfull++; 819 sc->sc_needwakeup |= CRYPTO_SYMQ; 820 mtx_unlock(&sc->sc_ringmtx); 821 return (ERESTART); 822 } 823 re = sc->sc_front; 824 825 staterec = re->re_sa.sa_staterec; /* save */ 826 /* NB: zero everything but the PE descriptor */ 827 bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); 828 re->re_sa.sa_staterec = staterec; /* restore */ 829 830 re->re_crp = crp; 831 832 sa = &re->re_sa; 833 ses = crypto_get_driver_session(crp->crp_session); 834 csp = crypto_get_params(crp->crp_session); 835 836 cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ 837 cmd1 = 0; 838 switch (csp->csp_mode) { 839 case CSP_MODE_DIGEST: 840 cmd0 |= SAFE_SA_CMD0_OP_HASH; 841 break; 842 case CSP_MODE_CIPHER: 843 cmd0 |= SAFE_SA_CMD0_OP_CRYPT; 844 break; 845 case CSP_MODE_ETA: 846 cmd0 |= SAFE_SA_CMD0_OP_BOTH; 847 break; 848 } 849 850 if (csp->csp_cipher_alg != 0) { 851 if (crp->crp_cipher_key != NULL) 852 safe_setup_enckey(ses, crp->crp_cipher_key); 853 854 switch (csp->csp_cipher_alg) { 855 case CRYPTO_AES_CBC: 856 cmd0 |= SAFE_SA_CMD0_AES; 857 cmd1 |= SAFE_SA_CMD1_CBC; 858 if (ses->ses_klen * 8 == 128) 859 cmd1 |= SAFE_SA_CMD1_AES128; 860 else if (ses->ses_klen * 8 == 192) 861 cmd1 |= SAFE_SA_CMD1_AES192; 862 else 863 cmd1 |= SAFE_SA_CMD1_AES256; 864 } 865 866 /* 867 * Setup encrypt/decrypt state. When using basic ops 868 * we can't use an inline IV because hash/crypt offset 869 * must be from the end of the IV to the start of the 870 * crypt data and this leaves out the preceding header 871 * from the hash calculation. Instead we place the IV 872 * in the state record and set the hash/crypt offset to 873 * copy both the header+IV. 874 */ 875 crypto_read_iv(crp, re->re_sastate.sa_saved_iv); 876 cmd0 |= SAFE_SA_CMD0_IVLD_STATE; 877 878 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) { 879 cmd0 |= SAFE_SA_CMD0_OUTBOUND; 880 881 /* 882 * XXX: I suspect we don't need this since we 883 * don't save the returned IV. 884 */ 885 cmd0 |= SAFE_SA_CMD0_SAVEIV; 886 } else { 887 cmd0 |= SAFE_SA_CMD0_INBOUND; 888 } 889 /* 890 * For basic encryption use the zero pad algorithm. 891 * This pads results to an 8-byte boundary and 892 * suppresses padding verification for inbound (i.e. 893 * decrypt) operations. 894 * 895 * NB: Not sure if the 8-byte pad boundary is a problem. 896 */ 897 cmd0 |= SAFE_SA_CMD0_PAD_ZERO; 898 899 /* XXX assert key bufs have the same size */ 900 bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); 901 } 902 903 if (csp->csp_auth_alg != 0) { 904 if (crp->crp_auth_key != NULL) { 905 safe_setup_mackey(ses, csp->csp_auth_alg, 906 crp->crp_auth_key, csp->csp_auth_klen); 907 } 908 909 switch (csp->csp_auth_alg) { 910 case CRYPTO_MD5_HMAC: 911 cmd0 |= SAFE_SA_CMD0_MD5; 912 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 913 break; 914 case CRYPTO_SHA1_HMAC: 915 cmd0 |= SAFE_SA_CMD0_SHA1; 916 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 917 break; 918 } 919 920 /* 921 * Digest data is loaded from the SA and the hash 922 * result is saved to the state block where we 923 * retrieve it for return to the caller. 924 */ 925 /* XXX assert digest bufs have the same size */ 926 bcopy(ses->ses_hminner, sa->sa_indigest, 927 sizeof(sa->sa_indigest)); 928 bcopy(ses->ses_hmouter, sa->sa_outdigest, 929 sizeof(sa->sa_outdigest)); 930 931 cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; 932 re->re_flags |= SAFE_QFLAGS_COPYOUTICV; 933 } 934 935 if (csp->csp_mode == CSP_MODE_ETA) { 936 /* 937 * The driver only supports ETA requests where there 938 * is no gap between the AAD and payload. 939 */ 940 if (crp->crp_aad_length != 0 && 941 crp->crp_aad_start + crp->crp_aad_length != 942 crp->crp_payload_start) { 943 safestats.st_lenmismatch++; 944 err = EINVAL; 945 goto errout; 946 } 947 if (crp->crp_aad_length != 0) 948 bypass = crp->crp_aad_start; 949 else 950 bypass = crp->crp_payload_start; 951 coffset = crp->crp_aad_length; 952 oplen = crp->crp_payload_start + crp->crp_payload_length; 953 #ifdef SAFE_DEBUG 954 if (safe_debug) { 955 printf("AAD: skip %d, len %d, digest %d\n", 956 crp->crp_aad_start, crp->crp_aad_length, 957 crp->crp_digest_start); 958 printf("payload: skip %d, len %d, IV %d\n", 959 crp->crp_payload_start, crp->crp_payload_length, 960 crp->crp_iv_start); 961 printf("bypass %d coffset %d oplen %d\n", 962 bypass, coffset, oplen); 963 } 964 #endif 965 if (coffset & 3) { /* offset must be 32-bit aligned */ 966 DPRINTF(("%s: coffset %u misaligned\n", 967 __func__, coffset)); 968 safestats.st_coffmisaligned++; 969 err = EINVAL; 970 goto errout; 971 } 972 coffset >>= 2; 973 if (coffset > 255) { /* offset must be <256 dwords */ 974 DPRINTF(("%s: coffset %u too big\n", 975 __func__, coffset)); 976 safestats.st_cofftoobig++; 977 err = EINVAL; 978 goto errout; 979 } 980 /* 981 * Tell the hardware to copy the header to the output. 982 * The header is defined as the data from the end of 983 * the bypass to the start of data to be encrypted. 984 * Typically this is the inline IV. Note that you need 985 * to do this even if src+dst are the same; it appears 986 * that w/o this bit the crypted data is written 987 * immediately after the bypass data. 988 */ 989 cmd1 |= SAFE_SA_CMD1_HDRCOPY; 990 /* 991 * Disable IP header mutable bit handling. This is 992 * needed to get correct HMAC calculations. 993 */ 994 cmd1 |= SAFE_SA_CMD1_MUTABLE; 995 } else { 996 bypass = crp->crp_payload_start; 997 oplen = bypass + crp->crp_payload_length; 998 coffset = 0; 999 } 1000 /* XXX verify multiple of 4 when using s/g */ 1001 if (bypass > 96) { /* bypass offset must be <= 96 bytes */ 1002 DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); 1003 safestats.st_bypasstoobig++; 1004 err = EINVAL; 1005 goto errout; 1006 } 1007 1008 if (bus_dmamap_create(sc->sc_srcdmat, BUS_DMA_NOWAIT, &re->re_src_map)) { 1009 safestats.st_nomap++; 1010 err = ENOMEM; 1011 goto errout; 1012 } 1013 if (bus_dmamap_load_crp(sc->sc_srcdmat, re->re_src_map, crp, safe_op_cb, 1014 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1015 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1016 re->re_src_map = NULL; 1017 safestats.st_noload++; 1018 err = ENOMEM; 1019 goto errout; 1020 } 1021 re->re_src_mapsize = safe_crp_length(crp); 1022 nicealign = safe_dmamap_aligned(&re->re_src); 1023 uniform = safe_dmamap_uniform(&re->re_src); 1024 1025 DPRINTF(("src nicealign %u uniform %u nsegs %u\n", 1026 nicealign, uniform, re->re_src.nsegs)); 1027 if (re->re_src.nsegs > 1) { 1028 re->re_desc.d_src = sc->sc_spalloc.dma_paddr + 1029 ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); 1030 for (i = 0; i < re->re_src_nsegs; i++) { 1031 /* NB: no need to check if there's space */ 1032 pd = sc->sc_spfree; 1033 if (++(sc->sc_spfree) == sc->sc_springtop) 1034 sc->sc_spfree = sc->sc_spring; 1035 1036 KASSERT((pd->pd_flags&3) == 0 || 1037 (pd->pd_flags&3) == SAFE_PD_DONE, 1038 ("bogus source particle descriptor; flags %x", 1039 pd->pd_flags)); 1040 pd->pd_addr = re->re_src_segs[i].ds_addr; 1041 pd->pd_size = re->re_src_segs[i].ds_len; 1042 pd->pd_flags = SAFE_PD_READY; 1043 } 1044 cmd0 |= SAFE_SA_CMD0_IGATHER; 1045 } else { 1046 /* 1047 * No need for gather, reference the operand directly. 1048 */ 1049 re->re_desc.d_src = re->re_src_segs[0].ds_addr; 1050 } 1051 1052 if (csp->csp_mode == CSP_MODE_DIGEST) { 1053 /* 1054 * Hash op; no destination needed. 1055 */ 1056 } else { 1057 if (nicealign && uniform == 1) { 1058 /* 1059 * Source layout is suitable for direct 1060 * sharing of the DMA map and segment list. 1061 */ 1062 re->re_dst = re->re_src; 1063 } else if (nicealign && uniform == 2) { 1064 /* 1065 * The source is properly aligned but requires a 1066 * different particle list to handle DMA of the 1067 * result. Create a new map and do the load to 1068 * create the segment list. The particle 1069 * descriptor setup code below will handle the 1070 * rest. 1071 */ 1072 if (bus_dmamap_create(sc->sc_dstdmat, BUS_DMA_NOWAIT, 1073 &re->re_dst_map)) { 1074 safestats.st_nomap++; 1075 err = ENOMEM; 1076 goto errout; 1077 } 1078 if (bus_dmamap_load_crp(sc->sc_dstdmat, re->re_dst_map, 1079 crp, safe_op_cb, &re->re_dst, BUS_DMA_NOWAIT) != 1080 0) { 1081 bus_dmamap_destroy(sc->sc_dstdmat, 1082 re->re_dst_map); 1083 re->re_dst_map = NULL; 1084 safestats.st_noload++; 1085 err = ENOMEM; 1086 goto errout; 1087 } 1088 } else if (crp->crp_buf_type == CRYPTO_BUF_MBUF) { 1089 int totlen, len; 1090 struct mbuf *m, *top, **mp; 1091 1092 /* 1093 * DMA constraints require that we allocate a 1094 * new mbuf chain for the destination. We 1095 * allocate an entire new set of mbufs of 1096 * optimal/required size and then tell the 1097 * hardware to copy any bits that are not 1098 * created as a byproduct of the operation. 1099 */ 1100 if (!nicealign) 1101 safestats.st_unaligned++; 1102 if (!uniform) 1103 safestats.st_notuniform++; 1104 totlen = re->re_src_mapsize; 1105 if (crp->crp_mbuf->m_flags & M_PKTHDR) { 1106 len = MHLEN; 1107 MGETHDR(m, M_NOWAIT, MT_DATA); 1108 if (m && !m_dup_pkthdr(m, crp->crp_mbuf, 1109 M_NOWAIT)) { 1110 m_free(m); 1111 m = NULL; 1112 } 1113 } else { 1114 len = MLEN; 1115 MGET(m, M_NOWAIT, MT_DATA); 1116 } 1117 if (m == NULL) { 1118 safestats.st_nombuf++; 1119 err = sc->sc_nqchip ? ERESTART : ENOMEM; 1120 goto errout; 1121 } 1122 if (totlen >= MINCLSIZE) { 1123 if (!(MCLGET(m, M_NOWAIT))) { 1124 m_free(m); 1125 safestats.st_nomcl++; 1126 err = sc->sc_nqchip ? 1127 ERESTART : ENOMEM; 1128 goto errout; 1129 } 1130 len = MCLBYTES; 1131 } 1132 m->m_len = len; 1133 top = NULL; 1134 mp = ⊤ 1135 1136 while (totlen > 0) { 1137 if (top) { 1138 MGET(m, M_NOWAIT, MT_DATA); 1139 if (m == NULL) { 1140 m_freem(top); 1141 safestats.st_nombuf++; 1142 err = sc->sc_nqchip ? 1143 ERESTART : ENOMEM; 1144 goto errout; 1145 } 1146 len = MLEN; 1147 } 1148 if (top && totlen >= MINCLSIZE) { 1149 if (!(MCLGET(m, M_NOWAIT))) { 1150 *mp = m; 1151 m_freem(top); 1152 safestats.st_nomcl++; 1153 err = sc->sc_nqchip ? 1154 ERESTART : ENOMEM; 1155 goto errout; 1156 } 1157 len = MCLBYTES; 1158 } 1159 m->m_len = len = min(totlen, len); 1160 totlen -= len; 1161 *mp = m; 1162 mp = &m->m_next; 1163 } 1164 re->re_dst_m = top; 1165 if (bus_dmamap_create(sc->sc_dstdmat, 1166 BUS_DMA_NOWAIT, &re->re_dst_map) != 0) { 1167 safestats.st_nomap++; 1168 err = ENOMEM; 1169 goto errout; 1170 } 1171 if (bus_dmamap_load_mbuf_sg(sc->sc_dstdmat, 1172 re->re_dst_map, top, re->re_dst_segs, 1173 &re->re_dst_nsegs, 0) != 0) { 1174 bus_dmamap_destroy(sc->sc_dstdmat, 1175 re->re_dst_map); 1176 re->re_dst_map = NULL; 1177 safestats.st_noload++; 1178 err = ENOMEM; 1179 goto errout; 1180 } 1181 re->re_dst_mapsize = re->re_src_mapsize; 1182 if (re->re_src.mapsize > oplen) { 1183 /* 1184 * There's data following what the 1185 * hardware will copy for us. If this 1186 * isn't just the ICV (that's going to 1187 * be written on completion), copy it 1188 * to the new mbufs 1189 */ 1190 if (!(csp->csp_mode == CSP_MODE_ETA && 1191 (re->re_src.mapsize-oplen) == ses->ses_mlen && 1192 crp->crp_digest_start == oplen)) 1193 safe_mcopy(crp->crp_mbuf, re->re_dst_m, 1194 oplen); 1195 else 1196 safestats.st_noicvcopy++; 1197 } 1198 } else { 1199 if (!nicealign) { 1200 safestats.st_iovmisaligned++; 1201 err = EINVAL; 1202 goto errout; 1203 } else { 1204 /* 1205 * There's no way to handle the DMA 1206 * requirements with this uio. We 1207 * could create a separate DMA area for 1208 * the result and then copy it back, 1209 * but for now we just bail and return 1210 * an error. Note that uio requests 1211 * > SAFE_MAX_DSIZE are handled because 1212 * the DMA map and segment list for the 1213 * destination wil result in a 1214 * destination particle list that does 1215 * the necessary scatter DMA. 1216 */ 1217 safestats.st_iovnotuniform++; 1218 err = EINVAL; 1219 goto errout; 1220 } 1221 } 1222 1223 if (re->re_dst.nsegs > 1) { 1224 re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + 1225 ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); 1226 for (i = 0; i < re->re_dst_nsegs; i++) { 1227 pd = sc->sc_dpfree; 1228 KASSERT((pd->pd_flags&3) == 0 || 1229 (pd->pd_flags&3) == SAFE_PD_DONE, 1230 ("bogus dest particle descriptor; flags %x", 1231 pd->pd_flags)); 1232 if (++(sc->sc_dpfree) == sc->sc_dpringtop) 1233 sc->sc_dpfree = sc->sc_dpring; 1234 pd->pd_addr = re->re_dst_segs[i].ds_addr; 1235 pd->pd_flags = SAFE_PD_READY; 1236 } 1237 cmd0 |= SAFE_SA_CMD0_OSCATTER; 1238 } else { 1239 /* 1240 * No need for scatter, reference the operand directly. 1241 */ 1242 re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; 1243 } 1244 } 1245 1246 /* 1247 * All done with setup; fillin the SA command words 1248 * and the packet engine descriptor. The operation 1249 * is now ready for submission to the hardware. 1250 */ 1251 sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; 1252 sa->sa_cmd1 = cmd1 1253 | (coffset << SAFE_SA_CMD1_OFFSET_S) 1254 | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ 1255 | SAFE_SA_CMD1_SRPCI 1256 ; 1257 /* 1258 * NB: the order of writes is important here. In case the 1259 * chip is scanning the ring because of an outstanding request 1260 * it might nab this one too. In that case we need to make 1261 * sure the setup is complete before we write the length 1262 * field of the descriptor as it signals the descriptor is 1263 * ready for processing. 1264 */ 1265 re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; 1266 if (csp->csp_auth_alg != 0) 1267 re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; 1268 re->re_desc.d_len = oplen 1269 | SAFE_PE_LEN_READY 1270 | (bypass << SAFE_PE_LEN_BYPASS_S) 1271 ; 1272 1273 safestats.st_ipackets++; 1274 safestats.st_ibytes += oplen; 1275 1276 if (++(sc->sc_front) == sc->sc_ringtop) 1277 sc->sc_front = sc->sc_ring; 1278 1279 /* XXX honor batching */ 1280 safe_feed(sc, re); 1281 mtx_unlock(&sc->sc_ringmtx); 1282 return (0); 1283 1284 errout: 1285 if (re->re_dst_m != NULL) 1286 m_freem(re->re_dst_m); 1287 1288 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1289 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1290 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1291 } 1292 if (re->re_src_map != NULL) { 1293 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1294 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1295 } 1296 mtx_unlock(&sc->sc_ringmtx); 1297 if (err != ERESTART) { 1298 crp->crp_etype = err; 1299 crypto_done(crp); 1300 } else { 1301 sc->sc_needwakeup |= CRYPTO_SYMQ; 1302 } 1303 return (err); 1304 } 1305 1306 static void 1307 safe_callback(struct safe_softc *sc, struct safe_ringentry *re) 1308 { 1309 const struct crypto_session_params *csp; 1310 struct cryptop *crp = (struct cryptop *)re->re_crp; 1311 struct safe_session *ses; 1312 uint8_t hash[HASH_MAX_LEN]; 1313 1314 ses = crypto_get_driver_session(crp->crp_session); 1315 csp = crypto_get_params(crp->crp_session); 1316 1317 safestats.st_opackets++; 1318 safestats.st_obytes += re->re_dst.mapsize; 1319 1320 safe_dma_sync(&sc->sc_ringalloc, 1321 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1322 if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { 1323 device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", 1324 re->re_desc.d_csr, 1325 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); 1326 safestats.st_peoperr++; 1327 crp->crp_etype = EIO; /* something more meaningful? */ 1328 } 1329 1330 /* XXX: Should crp_mbuf be updated to re->re_dst_m if it is non-NULL? */ 1331 1332 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1333 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 1334 BUS_DMASYNC_POSTREAD); 1335 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1336 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1337 } 1338 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_POSTWRITE); 1339 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1340 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1341 1342 if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { 1343 if (csp->csp_auth_alg == CRYPTO_SHA1_HMAC) { 1344 /* 1345 * SHA-1 ICV's are byte-swapped; fix 'em up 1346 * before copying them to their destination. 1347 */ 1348 re->re_sastate.sa_saved_indigest[0] = 1349 bswap32(re->re_sastate.sa_saved_indigest[0]); 1350 re->re_sastate.sa_saved_indigest[1] = 1351 bswap32(re->re_sastate.sa_saved_indigest[1]); 1352 re->re_sastate.sa_saved_indigest[2] = 1353 bswap32(re->re_sastate.sa_saved_indigest[2]); 1354 } 1355 1356 if (crp->crp_op & CRYPTO_OP_VERIFY_DIGEST) { 1357 crypto_copydata(crp, crp->crp_digest_start, 1358 ses->ses_mlen, hash); 1359 if (timingsafe_bcmp(re->re_sastate.sa_saved_indigest, 1360 hash, ses->ses_mlen) != 0) 1361 crp->crp_etype = EBADMSG; 1362 } else 1363 crypto_copyback(crp, crp->crp_digest_start, 1364 ses->ses_mlen, re->re_sastate.sa_saved_indigest); 1365 } 1366 crypto_done(crp); 1367 } 1368 1369 /* 1370 * Copy all data past offset from srcm to dstm. 1371 */ 1372 static void 1373 safe_mcopy(struct mbuf *srcm, struct mbuf *dstm, u_int offset) 1374 { 1375 u_int j, dlen, slen; 1376 caddr_t dptr, sptr; 1377 1378 /* 1379 * Advance src and dst to offset. 1380 */ 1381 j = offset; 1382 while (j >= srcm->m_len) { 1383 j -= srcm->m_len; 1384 srcm = srcm->m_next; 1385 if (srcm == NULL) 1386 return; 1387 } 1388 sptr = mtod(srcm, caddr_t) + j; 1389 slen = srcm->m_len - j; 1390 1391 j = offset; 1392 while (j >= dstm->m_len) { 1393 j -= dstm->m_len; 1394 dstm = dstm->m_next; 1395 if (dstm == NULL) 1396 return; 1397 } 1398 dptr = mtod(dstm, caddr_t) + j; 1399 dlen = dstm->m_len - j; 1400 1401 /* 1402 * Copy everything that remains. 1403 */ 1404 for (;;) { 1405 j = min(slen, dlen); 1406 bcopy(sptr, dptr, j); 1407 if (slen == j) { 1408 srcm = srcm->m_next; 1409 if (srcm == NULL) 1410 return; 1411 sptr = srcm->m_data; 1412 slen = srcm->m_len; 1413 } else 1414 sptr += j, slen -= j; 1415 if (dlen == j) { 1416 dstm = dstm->m_next; 1417 if (dstm == NULL) 1418 return; 1419 dptr = dstm->m_data; 1420 dlen = dstm->m_len; 1421 } else 1422 dptr += j, dlen -= j; 1423 } 1424 } 1425 1426 #ifndef SAFE_NO_RNG 1427 #define SAFE_RNG_MAXWAIT 1000 1428 1429 static void 1430 safe_rng_init(struct safe_softc *sc) 1431 { 1432 u_int32_t w, v; 1433 int i; 1434 1435 WRITE_REG(sc, SAFE_RNG_CTRL, 0); 1436 /* use default value according to the manual */ 1437 WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ 1438 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1439 1440 /* 1441 * There is a bug in rev 1.0 of the 1140 that when the RNG 1442 * is brought out of reset the ready status flag does not 1443 * work until the RNG has finished its internal initialization. 1444 * 1445 * So in order to determine the device is through its 1446 * initialization we must read the data register, using the 1447 * status reg in the read in case it is initialized. Then read 1448 * the data register until it changes from the first read. 1449 * Once it changes read the data register until it changes 1450 * again. At this time the RNG is considered initialized. 1451 * This could take between 750ms - 1000ms in time. 1452 */ 1453 i = 0; 1454 w = READ_REG(sc, SAFE_RNG_OUT); 1455 do { 1456 v = READ_REG(sc, SAFE_RNG_OUT); 1457 if (v != w) { 1458 w = v; 1459 break; 1460 } 1461 DELAY(10); 1462 } while (++i < SAFE_RNG_MAXWAIT); 1463 1464 /* Wait Until data changes again */ 1465 i = 0; 1466 do { 1467 v = READ_REG(sc, SAFE_RNG_OUT); 1468 if (v != w) 1469 break; 1470 DELAY(10); 1471 } while (++i < SAFE_RNG_MAXWAIT); 1472 } 1473 1474 static __inline void 1475 safe_rng_disable_short_cycle(struct safe_softc *sc) 1476 { 1477 WRITE_REG(sc, SAFE_RNG_CTRL, 1478 READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); 1479 } 1480 1481 static __inline void 1482 safe_rng_enable_short_cycle(struct safe_softc *sc) 1483 { 1484 WRITE_REG(sc, SAFE_RNG_CTRL, 1485 READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); 1486 } 1487 1488 static __inline u_int32_t 1489 safe_rng_read(struct safe_softc *sc) 1490 { 1491 int i; 1492 1493 i = 0; 1494 while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) 1495 ; 1496 return READ_REG(sc, SAFE_RNG_OUT); 1497 } 1498 1499 static void 1500 safe_rng(void *arg) 1501 { 1502 struct safe_softc *sc = arg; 1503 u_int32_t buf[SAFE_RNG_MAXBUFSIZ]; /* NB: maybe move to softc */ 1504 u_int maxwords; 1505 int i; 1506 1507 safestats.st_rng++; 1508 /* 1509 * Fetch the next block of data. 1510 */ 1511 maxwords = safe_rngbufsize; 1512 if (maxwords > SAFE_RNG_MAXBUFSIZ) 1513 maxwords = SAFE_RNG_MAXBUFSIZ; 1514 retry: 1515 for (i = 0; i < maxwords; i++) 1516 buf[i] = safe_rng_read(sc); 1517 /* 1518 * Check the comparator alarm count and reset the h/w if 1519 * it exceeds our threshold. This guards against the 1520 * hardware oscillators resonating with external signals. 1521 */ 1522 if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { 1523 u_int32_t freq_inc, w; 1524 1525 DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, 1526 READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); 1527 safestats.st_rngalarm++; 1528 safe_rng_enable_short_cycle(sc); 1529 freq_inc = 18; 1530 for (i = 0; i < 64; i++) { 1531 w = READ_REG(sc, SAFE_RNG_CNFG); 1532 freq_inc = ((w + freq_inc) & 0x3fL); 1533 w = ((w & ~0x3fL) | freq_inc); 1534 WRITE_REG(sc, SAFE_RNG_CNFG, w); 1535 1536 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1537 1538 (void) safe_rng_read(sc); 1539 DELAY(25); 1540 1541 if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { 1542 safe_rng_disable_short_cycle(sc); 1543 goto retry; 1544 } 1545 freq_inc = 1; 1546 } 1547 safe_rng_disable_short_cycle(sc); 1548 } else 1549 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1550 1551 (*sc->sc_harvest)(sc->sc_rndtest, buf, maxwords*sizeof (u_int32_t)); 1552 callout_reset(&sc->sc_rngto, 1553 hz * (safe_rnginterval ? safe_rnginterval : 1), safe_rng, sc); 1554 } 1555 #endif /* SAFE_NO_RNG */ 1556 1557 static void 1558 safe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1559 { 1560 bus_addr_t *paddr = (bus_addr_t*) arg; 1561 *paddr = segs->ds_addr; 1562 } 1563 1564 static int 1565 safe_dma_malloc( 1566 struct safe_softc *sc, 1567 bus_size_t size, 1568 struct safe_dma_alloc *dma, 1569 int mapflags 1570 ) 1571 { 1572 int r; 1573 1574 r = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1575 sizeof(u_int32_t), 0, /* alignment, bounds */ 1576 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1577 BUS_SPACE_MAXADDR, /* highaddr */ 1578 NULL, NULL, /* filter, filterarg */ 1579 size, /* maxsize */ 1580 1, /* nsegments */ 1581 size, /* maxsegsize */ 1582 BUS_DMA_ALLOCNOW, /* flags */ 1583 NULL, NULL, /* locking */ 1584 &dma->dma_tag); 1585 if (r != 0) { 1586 device_printf(sc->sc_dev, "safe_dma_malloc: " 1587 "bus_dma_tag_create failed; error %u\n", r); 1588 goto fail_0; 1589 } 1590 1591 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1592 BUS_DMA_NOWAIT, &dma->dma_map); 1593 if (r != 0) { 1594 device_printf(sc->sc_dev, "safe_dma_malloc: " 1595 "bus_dmammem_alloc failed; size %ju, error %u\n", 1596 (uintmax_t)size, r); 1597 goto fail_1; 1598 } 1599 1600 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1601 size, 1602 safe_dmamap_cb, 1603 &dma->dma_paddr, 1604 mapflags | BUS_DMA_NOWAIT); 1605 if (r != 0) { 1606 device_printf(sc->sc_dev, "safe_dma_malloc: " 1607 "bus_dmamap_load failed; error %u\n", r); 1608 goto fail_2; 1609 } 1610 1611 dma->dma_size = size; 1612 return (0); 1613 1614 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1615 fail_2: 1616 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1617 fail_1: 1618 bus_dma_tag_destroy(dma->dma_tag); 1619 fail_0: 1620 dma->dma_tag = NULL; 1621 return (r); 1622 } 1623 1624 static void 1625 safe_dma_free(struct safe_softc *sc, struct safe_dma_alloc *dma) 1626 { 1627 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1628 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1629 bus_dma_tag_destroy(dma->dma_tag); 1630 } 1631 1632 /* 1633 * Resets the board. Values in the regesters are left as is 1634 * from the reset (i.e. initial values are assigned elsewhere). 1635 */ 1636 static void 1637 safe_reset_board(struct safe_softc *sc) 1638 { 1639 u_int32_t v; 1640 /* 1641 * Reset the device. The manual says no delay 1642 * is needed between marking and clearing reset. 1643 */ 1644 v = READ_REG(sc, SAFE_PE_DMACFG) &~ 1645 (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | 1646 SAFE_PE_DMACFG_SGRESET); 1647 WRITE_REG(sc, SAFE_PE_DMACFG, v 1648 | SAFE_PE_DMACFG_PERESET 1649 | SAFE_PE_DMACFG_PDRRESET 1650 | SAFE_PE_DMACFG_SGRESET); 1651 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1652 } 1653 1654 /* 1655 * Initialize registers we need to touch only once. 1656 */ 1657 static void 1658 safe_init_board(struct safe_softc *sc) 1659 { 1660 u_int32_t v, dwords; 1661 1662 v = READ_REG(sc, SAFE_PE_DMACFG); 1663 v &=~ SAFE_PE_DMACFG_PEMODE; 1664 v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ 1665 | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ 1666 | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ 1667 | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ 1668 | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ 1669 | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ 1670 ; 1671 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1672 #if 0 1673 /* XXX select byte swap based on host byte order */ 1674 WRITE_REG(sc, SAFE_ENDIAN, 0x1b); 1675 #endif 1676 if (sc->sc_chiprev == SAFE_REV(1,0)) { 1677 /* 1678 * Avoid large PCI DMA transfers. Rev 1.0 has a bug where 1679 * "target mode transfers" done while the chip is DMA'ing 1680 * >1020 bytes cause the hardware to lockup. To avoid this 1681 * we reduce the max PCI transfer size and use small source 1682 * particle descriptors (<= 256 bytes). 1683 */ 1684 WRITE_REG(sc, SAFE_DMA_CFG, 256); 1685 device_printf(sc->sc_dev, 1686 "Reduce max DMA size to %u words for rev %u.%u WAR\n", 1687 (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff, 1688 SAFE_REV_MAJ(sc->sc_chiprev), 1689 SAFE_REV_MIN(sc->sc_chiprev)); 1690 } 1691 1692 /* NB: operands+results are overlaid */ 1693 WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); 1694 WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); 1695 /* 1696 * Configure ring entry size and number of items in the ring. 1697 */ 1698 KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, 1699 ("PE ring entry not 32-bit aligned!")); 1700 dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); 1701 WRITE_REG(sc, SAFE_PE_RINGCFG, 1702 (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); 1703 WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ 1704 1705 WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); 1706 WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); 1707 WRITE_REG(sc, SAFE_PE_PARTSIZE, 1708 (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); 1709 /* 1710 * NB: destination particles are fixed size. We use 1711 * an mbuf cluster and require all results go to 1712 * clusters or smaller. 1713 */ 1714 WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE); 1715 1716 /* it's now safe to enable PE mode, do it */ 1717 WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); 1718 1719 /* 1720 * Configure hardware to use level-triggered interrupts and 1721 * to interrupt after each descriptor is processed. 1722 */ 1723 WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); 1724 WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); 1725 WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); 1726 } 1727 1728 /* 1729 * Init PCI registers 1730 */ 1731 static void 1732 safe_init_pciregs(device_t dev) 1733 { 1734 } 1735 1736 /* 1737 * Clean up after a chip crash. 1738 * It is assumed that the caller in splimp() 1739 */ 1740 static void 1741 safe_cleanchip(struct safe_softc *sc) 1742 { 1743 1744 if (sc->sc_nqchip != 0) { 1745 struct safe_ringentry *re = sc->sc_back; 1746 1747 while (re != sc->sc_front) { 1748 if (re->re_desc.d_csr != 0) 1749 safe_free_entry(sc, re); 1750 if (++re == sc->sc_ringtop) 1751 re = sc->sc_ring; 1752 } 1753 sc->sc_back = re; 1754 sc->sc_nqchip = 0; 1755 } 1756 } 1757 1758 /* 1759 * free a safe_q 1760 * It is assumed that the caller is within splimp(). 1761 */ 1762 static int 1763 safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) 1764 { 1765 struct cryptop *crp; 1766 1767 /* 1768 * Free header MCR 1769 */ 1770 if (re->re_dst_m != NULL) 1771 m_freem(re->re_dst_m); 1772 1773 crp = (struct cryptop *)re->re_crp; 1774 1775 re->re_desc.d_csr = 0; 1776 1777 crp->crp_etype = EFAULT; 1778 crypto_done(crp); 1779 return(0); 1780 } 1781 1782 /* 1783 * Routine to reset the chip and clean up. 1784 * It is assumed that the caller is in splimp() 1785 */ 1786 static void 1787 safe_totalreset(struct safe_softc *sc) 1788 { 1789 safe_reset_board(sc); 1790 safe_init_board(sc); 1791 safe_cleanchip(sc); 1792 } 1793 1794 /* 1795 * Is the operand suitable aligned for direct DMA. Each 1796 * segment must be aligned on a 32-bit boundary and all 1797 * but the last segment must be a multiple of 4 bytes. 1798 */ 1799 static int 1800 safe_dmamap_aligned(const struct safe_operand *op) 1801 { 1802 int i; 1803 1804 for (i = 0; i < op->nsegs; i++) { 1805 if (op->segs[i].ds_addr & 3) 1806 return (0); 1807 if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) 1808 return (0); 1809 } 1810 return (1); 1811 } 1812 1813 /* 1814 * Is the operand suitable for direct DMA as the destination 1815 * of an operation. The hardware requires that each ``particle'' 1816 * but the last in an operation result have the same size. We 1817 * fix that size at SAFE_MAX_DSIZE bytes. This routine returns 1818 * 0 if some segment is not a multiple of of this size, 1 if all 1819 * segments are exactly this size, or 2 if segments are at worst 1820 * a multple of this size. 1821 */ 1822 static int 1823 safe_dmamap_uniform(const struct safe_operand *op) 1824 { 1825 int result = 1; 1826 1827 if (op->nsegs > 0) { 1828 int i; 1829 1830 for (i = 0; i < op->nsegs-1; i++) { 1831 if (op->segs[i].ds_len % SAFE_MAX_DSIZE) 1832 return (0); 1833 if (op->segs[i].ds_len != SAFE_MAX_DSIZE) 1834 result = 2; 1835 } 1836 } 1837 return (result); 1838 } 1839 1840 #ifdef SAFE_DEBUG 1841 static void 1842 safe_dump_dmastatus(struct safe_softc *sc, const char *tag) 1843 { 1844 printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" 1845 , tag 1846 , READ_REG(sc, SAFE_DMA_ENDIAN) 1847 , READ_REG(sc, SAFE_DMA_SRCADDR) 1848 , READ_REG(sc, SAFE_DMA_DSTADDR) 1849 , READ_REG(sc, SAFE_DMA_STAT) 1850 ); 1851 } 1852 1853 static void 1854 safe_dump_intrstate(struct safe_softc *sc, const char *tag) 1855 { 1856 printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" 1857 , tag 1858 , READ_REG(sc, SAFE_HI_CFG) 1859 , READ_REG(sc, SAFE_HI_MASK) 1860 , READ_REG(sc, SAFE_HI_DESC_CNT) 1861 , READ_REG(sc, SAFE_HU_STAT) 1862 , READ_REG(sc, SAFE_HM_STAT) 1863 ); 1864 } 1865 1866 static void 1867 safe_dump_ringstate(struct safe_softc *sc, const char *tag) 1868 { 1869 u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); 1870 1871 /* NB: assume caller has lock on ring */ 1872 printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", 1873 tag, 1874 estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), 1875 (unsigned long)(sc->sc_back - sc->sc_ring), 1876 (unsigned long)(sc->sc_front - sc->sc_ring)); 1877 } 1878 1879 static void 1880 safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) 1881 { 1882 int ix, nsegs; 1883 1884 ix = re - sc->sc_ring; 1885 printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" 1886 , tag 1887 , re, ix 1888 , re->re_desc.d_csr 1889 , re->re_desc.d_src 1890 , re->re_desc.d_dst 1891 , re->re_desc.d_sa 1892 , re->re_desc.d_len 1893 ); 1894 if (re->re_src.nsegs > 1) { 1895 ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / 1896 sizeof(struct safe_pdesc); 1897 for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { 1898 printf(" spd[%u] %p: %p size %u flags %x" 1899 , ix, &sc->sc_spring[ix] 1900 , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr 1901 , sc->sc_spring[ix].pd_size 1902 , sc->sc_spring[ix].pd_flags 1903 ); 1904 if (sc->sc_spring[ix].pd_size == 0) 1905 printf(" (zero!)"); 1906 printf("\n"); 1907 if (++ix == SAFE_TOTAL_SPART) 1908 ix = 0; 1909 } 1910 } 1911 if (re->re_dst.nsegs > 1) { 1912 ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / 1913 sizeof(struct safe_pdesc); 1914 for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { 1915 printf(" dpd[%u] %p: %p flags %x\n" 1916 , ix, &sc->sc_dpring[ix] 1917 , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr 1918 , sc->sc_dpring[ix].pd_flags 1919 ); 1920 if (++ix == SAFE_TOTAL_DPART) 1921 ix = 0; 1922 } 1923 } 1924 printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", 1925 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); 1926 printf("sa: key %x %x %x %x %x %x %x %x\n" 1927 , re->re_sa.sa_key[0] 1928 , re->re_sa.sa_key[1] 1929 , re->re_sa.sa_key[2] 1930 , re->re_sa.sa_key[3] 1931 , re->re_sa.sa_key[4] 1932 , re->re_sa.sa_key[5] 1933 , re->re_sa.sa_key[6] 1934 , re->re_sa.sa_key[7] 1935 ); 1936 printf("sa: indigest %x %x %x %x %x\n" 1937 , re->re_sa.sa_indigest[0] 1938 , re->re_sa.sa_indigest[1] 1939 , re->re_sa.sa_indigest[2] 1940 , re->re_sa.sa_indigest[3] 1941 , re->re_sa.sa_indigest[4] 1942 ); 1943 printf("sa: outdigest %x %x %x %x %x\n" 1944 , re->re_sa.sa_outdigest[0] 1945 , re->re_sa.sa_outdigest[1] 1946 , re->re_sa.sa_outdigest[2] 1947 , re->re_sa.sa_outdigest[3] 1948 , re->re_sa.sa_outdigest[4] 1949 ); 1950 printf("sr: iv %x %x %x %x\n" 1951 , re->re_sastate.sa_saved_iv[0] 1952 , re->re_sastate.sa_saved_iv[1] 1953 , re->re_sastate.sa_saved_iv[2] 1954 , re->re_sastate.sa_saved_iv[3] 1955 ); 1956 printf("sr: hashbc %u indigest %x %x %x %x %x\n" 1957 , re->re_sastate.sa_saved_hashbc 1958 , re->re_sastate.sa_saved_indigest[0] 1959 , re->re_sastate.sa_saved_indigest[1] 1960 , re->re_sastate.sa_saved_indigest[2] 1961 , re->re_sastate.sa_saved_indigest[3] 1962 , re->re_sastate.sa_saved_indigest[4] 1963 ); 1964 } 1965 1966 static void 1967 safe_dump_ring(struct safe_softc *sc, const char *tag) 1968 { 1969 mtx_lock(&sc->sc_ringmtx); 1970 printf("\nSafeNet Ring State:\n"); 1971 safe_dump_intrstate(sc, tag); 1972 safe_dump_dmastatus(sc, tag); 1973 safe_dump_ringstate(sc, tag); 1974 if (sc->sc_nqchip) { 1975 struct safe_ringentry *re = sc->sc_back; 1976 do { 1977 safe_dump_request(sc, tag, re); 1978 if (++re == sc->sc_ringtop) 1979 re = sc->sc_ring; 1980 } while (re != sc->sc_front); 1981 } 1982 mtx_unlock(&sc->sc_ringmtx); 1983 } 1984 1985 static int 1986 sysctl_hw_safe_dump(SYSCTL_HANDLER_ARGS) 1987 { 1988 char dmode[64]; 1989 int error; 1990 1991 strncpy(dmode, "", sizeof(dmode) - 1); 1992 dmode[sizeof(dmode) - 1] = '\0'; 1993 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 1994 1995 if (error == 0 && req->newptr != NULL) { 1996 struct safe_softc *sc = safec; 1997 1998 if (!sc) 1999 return EINVAL; 2000 if (strncmp(dmode, "dma", 3) == 0) 2001 safe_dump_dmastatus(sc, "safe0"); 2002 else if (strncmp(dmode, "int", 3) == 0) 2003 safe_dump_intrstate(sc, "safe0"); 2004 else if (strncmp(dmode, "ring", 4) == 0) 2005 safe_dump_ring(sc, "safe0"); 2006 else 2007 return EINVAL; 2008 } 2009 return error; 2010 } 2011 SYSCTL_PROC(_hw_safe, OID_AUTO, dump, 2012 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 0, 0, 2013 sysctl_hw_safe_dump, "A", 2014 "Dump driver state"); 2015 #endif /* SAFE_DEBUG */ 2016