1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010 Alexander Motin <[email protected]> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/malloc.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <vm/uma.h> 40 #include <machine/stdarg.h> 41 #include <machine/resource.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <sys/sbuf.h> 45 #include <arm/mv/mvreg.h> 46 #include <arm/mv/mvvar.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 #include "mvs.h" 50 51 /* local prototypes */ 52 static int mvs_setup_interrupt(device_t dev); 53 static void mvs_intr(void *data); 54 static int mvs_suspend(device_t dev); 55 static int mvs_resume(device_t dev); 56 static int mvs_ctlr_setup(device_t dev); 57 58 static struct { 59 uint32_t id; 60 uint8_t rev; 61 const char *name; 62 int ports; 63 int quirks; 64 } mvs_ids[] = { 65 {MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 66 {MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 67 {MV_DEV_88F6282, 0x00, "Marvell 88F6282", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 68 {MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 69 {MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 70 {MV_DEV_MV78260, 0x00, "Marvell MV78260", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 71 {MV_DEV_MV78460, 0x00, "Marvell MV78460", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 72 {0, 0x00, NULL, 0, 0} 73 }; 74 75 static int 76 mvs_probe(device_t dev) 77 { 78 int i; 79 uint32_t devid, revid; 80 81 if (!ofw_bus_status_okay(dev)) 82 return (ENXIO); 83 84 if (!ofw_bus_is_compatible(dev, "mrvl,sata")) 85 return (ENXIO); 86 87 soc_id(&devid, &revid); 88 for (i = 0; mvs_ids[i].id != 0; i++) { 89 if (mvs_ids[i].id == devid && 90 mvs_ids[i].rev <= revid) { 91 device_set_descf(dev, "%s SATA controller", 92 mvs_ids[i].name); 93 return (BUS_PROBE_DEFAULT); 94 } 95 } 96 return (ENXIO); 97 } 98 99 static int 100 mvs_attach(device_t dev) 101 { 102 struct mvs_controller *ctlr = device_get_softc(dev); 103 device_t child; 104 int error, unit, i; 105 uint32_t devid, revid; 106 107 soc_id(&devid, &revid); 108 ctlr->dev = dev; 109 i = 0; 110 while (mvs_ids[i].id != 0 && 111 (mvs_ids[i].id != devid || 112 mvs_ids[i].rev > revid)) 113 i++; 114 ctlr->channels = mvs_ids[i].ports; 115 ctlr->quirks = mvs_ids[i].quirks; 116 ctlr->ccc = 0; 117 resource_int_value(device_get_name(dev), 118 device_get_unit(dev), "ccc", &ctlr->ccc); 119 ctlr->cccc = 8; 120 resource_int_value(device_get_name(dev), 121 device_get_unit(dev), "cccc", &ctlr->cccc); 122 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 123 ctlr->ccc = 0; 124 ctlr->cccc = 0; 125 } 126 if (ctlr->ccc > 100000) 127 ctlr->ccc = 100000; 128 device_printf(dev, 129 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 130 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 131 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 132 ctlr->channels, 133 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 134 ((ctlr->quirks & MVS_Q_GENI) ? 135 "not supported" : "supported"), 136 ((ctlr->quirks & MVS_Q_GENIIE) ? 137 " with FBS" : "")); 138 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 139 /* We should have a memory BAR(0). */ 140 ctlr->r_rid = 0; 141 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 142 &ctlr->r_rid, RF_ACTIVE))) 143 return ENXIO; 144 if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0) 145 ctlr->quirks |= MVS_Q_SOC65; 146 /* Setup our own memory management for channels. */ 147 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 148 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 149 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 150 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 151 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 152 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 153 return (error); 154 } 155 if ((error = rman_manage_region(&ctlr->sc_iomem, 156 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 157 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 158 rman_fini(&ctlr->sc_iomem); 159 return (error); 160 } 161 mvs_ctlr_setup(dev); 162 /* Setup interrupts. */ 163 if (mvs_setup_interrupt(dev)) { 164 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 165 rman_fini(&ctlr->sc_iomem); 166 return ENXIO; 167 } 168 /* Attach all channels on this controller */ 169 for (unit = 0; unit < ctlr->channels; unit++) { 170 child = device_add_child(dev, "mvsch", -1); 171 if (child == NULL) 172 device_printf(dev, "failed to add channel device\n"); 173 else 174 device_set_ivars(child, (void *)(intptr_t)unit); 175 } 176 bus_generic_attach(dev); 177 return 0; 178 } 179 180 static int 181 mvs_detach(device_t dev) 182 { 183 struct mvs_controller *ctlr = device_get_softc(dev); 184 185 /* Detach & delete all children */ 186 device_delete_children(dev); 187 188 /* Free interrupt. */ 189 if (ctlr->irq.r_irq) { 190 bus_teardown_intr(dev, ctlr->irq.r_irq, 191 ctlr->irq.handle); 192 bus_release_resource(dev, SYS_RES_IRQ, 193 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 194 } 195 /* Free memory. */ 196 rman_fini(&ctlr->sc_iomem); 197 if (ctlr->r_mem) 198 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 199 mtx_destroy(&ctlr->mtx); 200 return (0); 201 } 202 203 static int 204 mvs_ctlr_setup(device_t dev) 205 { 206 struct mvs_controller *ctlr = device_get_softc(dev); 207 int ccc = ctlr->ccc, cccc = ctlr->cccc; 208 209 /* Mask chip interrupts */ 210 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 211 /* Clear HC interrupts */ 212 ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000); 213 /* Clear chip interrupts */ 214 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0); 215 /* Configure per-HC CCC */ 216 if (ccc && bootverbose) { 217 device_printf(dev, 218 "CCC with %dus/%dcmd enabled\n", 219 ctlr->ccc, ctlr->cccc); 220 } 221 ccc *= 150; 222 ATA_OUTL(ctlr->r_mem, HC_ICT, cccc); 223 ATA_OUTL(ctlr->r_mem, HC_ITT, ccc); 224 /* Enable chip interrupts */ 225 ctlr->gmim = ((ccc ? IC_HC0_COAL_DONE : 226 (IC_DONE_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))) | 227 (IC_ERR_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))); 228 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 229 return (0); 230 } 231 232 static void 233 mvs_edma(device_t dev, device_t child, int mode) 234 { 235 struct mvs_controller *ctlr = device_get_softc(dev); 236 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 237 int bit = IC_DONE_IRQ << (unit * 2); 238 239 if (ctlr->ccc == 0) 240 return; 241 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 242 mtx_lock(&ctlr->mtx); 243 if (mode == MVS_EDMA_OFF) 244 ctlr->pmim |= bit; 245 else 246 ctlr->pmim &= ~bit; 247 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 248 mtx_unlock(&ctlr->mtx); 249 } 250 251 static int 252 mvs_suspend(device_t dev) 253 { 254 struct mvs_controller *ctlr = device_get_softc(dev); 255 256 bus_generic_suspend(dev); 257 /* Mask chip interrupts */ 258 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 259 return 0; 260 } 261 262 static int 263 mvs_resume(device_t dev) 264 { 265 266 mvs_ctlr_setup(dev); 267 return (bus_generic_resume(dev)); 268 } 269 270 static int 271 mvs_setup_interrupt(device_t dev) 272 { 273 struct mvs_controller *ctlr = device_get_softc(dev); 274 275 /* Allocate all IRQs. */ 276 ctlr->irq.r_irq_rid = 0; 277 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 278 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 279 device_printf(dev, "unable to map interrupt\n"); 280 return (ENXIO); 281 } 282 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 283 mvs_intr, ctlr, &ctlr->irq.handle))) { 284 device_printf(dev, "unable to setup interrupt\n"); 285 bus_release_resource(dev, SYS_RES_IRQ, 286 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 287 ctlr->irq.r_irq = NULL; 288 return (ENXIO); 289 } 290 return (0); 291 } 292 293 /* 294 * Common case interrupt handler. 295 */ 296 static void 297 mvs_intr(void *data) 298 { 299 struct mvs_controller *ctlr = data; 300 struct mvs_intr_arg arg; 301 void (*function)(void *); 302 int p, chan_num; 303 u_int32_t ic, aic; 304 305 ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); 306 if ((ic & IC_HC0) == 0) 307 return; 308 309 /* Acknowledge interrupts of this HC. */ 310 aic = 0; 311 312 /* Processing interrupts from each initialized channel */ 313 for (chan_num = 0; chan_num < ctlr->channels; chan_num++) { 314 if (ic & (IC_DONE_IRQ << (chan_num * 2))) 315 aic |= HC_IC_DONE(chan_num) | HC_IC_DEV(chan_num); 316 } 317 318 if (ic & IC_HC0_COAL_DONE) 319 aic |= HC_IC_COAL; 320 ATA_OUTL(ctlr->r_mem, HC_IC, ~aic); 321 322 /* Call per-port interrupt handler. */ 323 for (p = 0; p < ctlr->channels; p++) { 324 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 325 if ((arg.cause != 0) && 326 (function = ctlr->interrupt[p].function)) { 327 arg.arg = ctlr->interrupt[p].argument; 328 function(&arg); 329 } 330 ic >>= 2; 331 } 332 } 333 334 static struct resource * 335 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 336 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 337 { 338 struct mvs_controller *ctlr = device_get_softc(dev); 339 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 340 struct resource *res = NULL; 341 int offset = PORT_BASE(unit & 0x03); 342 rman_res_t st; 343 344 switch (type) { 345 case SYS_RES_MEMORY: 346 st = rman_get_start(ctlr->r_mem); 347 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 348 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 349 if (res) { 350 bus_space_handle_t bsh; 351 bus_space_tag_t bst; 352 bsh = rman_get_bushandle(ctlr->r_mem); 353 bst = rman_get_bustag(ctlr->r_mem); 354 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 355 rman_set_bushandle(res, bsh); 356 rman_set_bustag(res, bst); 357 } 358 break; 359 case SYS_RES_IRQ: 360 if (*rid == ATA_IRQ_RID) 361 res = ctlr->irq.r_irq; 362 break; 363 } 364 return (res); 365 } 366 367 static int 368 mvs_release_resource(device_t dev, device_t child, int type, int rid, 369 struct resource *r) 370 { 371 372 switch (type) { 373 case SYS_RES_MEMORY: 374 rman_release_resource(r); 375 return (0); 376 case SYS_RES_IRQ: 377 if (rid != ATA_IRQ_RID) 378 return ENOENT; 379 return (0); 380 } 381 return (EINVAL); 382 } 383 384 static int 385 mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 386 int flags, driver_filter_t *filter, driver_intr_t *function, 387 void *argument, void **cookiep) 388 { 389 struct mvs_controller *ctlr = device_get_softc(dev); 390 int unit = (intptr_t)device_get_ivars(child); 391 392 if (filter != NULL) { 393 printf("mvs.c: we cannot use a filter here\n"); 394 return (EINVAL); 395 } 396 ctlr->interrupt[unit].function = function; 397 ctlr->interrupt[unit].argument = argument; 398 return (0); 399 } 400 401 static int 402 mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 403 void *cookie) 404 { 405 struct mvs_controller *ctlr = device_get_softc(dev); 406 int unit = (intptr_t)device_get_ivars(child); 407 408 ctlr->interrupt[unit].function = NULL; 409 ctlr->interrupt[unit].argument = NULL; 410 return (0); 411 } 412 413 static int 414 mvs_print_child(device_t dev, device_t child) 415 { 416 int retval; 417 418 retval = bus_print_child_header(dev, child); 419 retval += printf(" at channel %d", 420 (int)(intptr_t)device_get_ivars(child)); 421 retval += bus_print_child_footer(dev, child); 422 423 return (retval); 424 } 425 426 static int 427 mvs_child_location(device_t dev, device_t child, struct sbuf *sb) 428 { 429 430 sbuf_printf(sb, "channel=%d", (int)(intptr_t)device_get_ivars(child)); 431 return (0); 432 } 433 434 static bus_dma_tag_t 435 mvs_get_dma_tag(device_t bus, device_t child) 436 { 437 438 return (bus_get_dma_tag(bus)); 439 } 440 441 static device_method_t mvs_methods[] = { 442 DEVMETHOD(device_probe, mvs_probe), 443 DEVMETHOD(device_attach, mvs_attach), 444 DEVMETHOD(device_detach, mvs_detach), 445 DEVMETHOD(device_suspend, mvs_suspend), 446 DEVMETHOD(device_resume, mvs_resume), 447 DEVMETHOD(bus_print_child, mvs_print_child), 448 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 449 DEVMETHOD(bus_release_resource, mvs_release_resource), 450 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 451 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 452 DEVMETHOD(bus_child_location, mvs_child_location), 453 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag), 454 DEVMETHOD(mvs_edma, mvs_edma), 455 { 0, 0 } 456 }; 457 static driver_t mvs_driver = { 458 "mvs", 459 mvs_methods, 460 sizeof(struct mvs_controller) 461 }; 462 DRIVER_MODULE(mvs, simplebus, mvs_driver, 0, 0); 463 MODULE_VERSION(mvs, 1); 464 MODULE_DEPEND(mvs, cam, 1, 1, 1); 465