1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <[email protected]> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/endian.h> 43 #include <sys/kernel.h> 44 #include <sys/bus.h> 45 #include <sys/malloc.h> 46 #include <sys/mbuf.h> 47 #include <sys/proc.h> 48 #include <sys/rman.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 54 #include <net/ethernet.h> 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_dl.h> 58 #include <net/if_types.h> 59 #include <net/bpf.h> 60 #include <net/if_arp.h> 61 #include <net/if_media.h> 62 #include <net/if_vlan_var.h> 63 64 #include <machine/bus.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <dev/et/if_etreg.h> 73 #include <dev/et/if_etvar.h> 74 75 #include "miibus_if.h" 76 77 MODULE_DEPEND(et, pci, 1, 1, 1); 78 MODULE_DEPEND(et, ether, 1, 1, 1); 79 MODULE_DEPEND(et, miibus, 1, 1, 1); 80 81 /* Tunables. */ 82 static int msi_disable = 0; 83 TUNABLE_INT("hw.et.msi_disable", &msi_disable); 84 85 #define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 87 static int et_probe(device_t); 88 static int et_attach(device_t); 89 static int et_detach(device_t); 90 static int et_shutdown(device_t); 91 static int et_suspend(device_t); 92 static int et_resume(device_t); 93 94 static int et_miibus_readreg(device_t, int, int); 95 static int et_miibus_writereg(device_t, int, int, int); 96 static void et_miibus_statchg(device_t); 97 98 static void et_init_locked(struct et_softc *); 99 static void et_init(void *); 100 static int et_ioctl(if_t, u_long, caddr_t); 101 static void et_start_locked(if_t); 102 static void et_start(if_t); 103 static int et_watchdog(struct et_softc *); 104 static int et_ifmedia_upd_locked(if_t); 105 static int et_ifmedia_upd(if_t); 106 static void et_ifmedia_sts(if_t, struct ifmediareq *); 107 static uint64_t et_get_counter(if_t, ift_counter); 108 109 static void et_add_sysctls(struct et_softc *); 110 static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 111 static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 112 113 static void et_intr(void *); 114 static void et_rxeof(struct et_softc *); 115 static void et_txeof(struct et_softc *); 116 117 static int et_dma_alloc(struct et_softc *); 118 static void et_dma_free(struct et_softc *); 119 static void et_dma_map_addr(void *, bus_dma_segment_t *, int, int); 120 static int et_dma_ring_alloc(struct et_softc *, bus_size_t, bus_size_t, 121 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, 122 const char *); 123 static void et_dma_ring_free(struct et_softc *, bus_dma_tag_t *, uint8_t **, 124 bus_dmamap_t, bus_addr_t *); 125 static void et_init_tx_ring(struct et_softc *); 126 static int et_init_rx_ring(struct et_softc *); 127 static void et_free_tx_ring(struct et_softc *); 128 static void et_free_rx_ring(struct et_softc *); 129 static int et_encap(struct et_softc *, struct mbuf **); 130 static int et_newbuf_cluster(struct et_rxbuf_data *, int); 131 static int et_newbuf_hdr(struct et_rxbuf_data *, int); 132 static void et_rxbuf_discard(struct et_rxbuf_data *, int); 133 134 static void et_stop(struct et_softc *); 135 static int et_chip_init(struct et_softc *); 136 static void et_chip_attach(struct et_softc *); 137 static void et_init_mac(struct et_softc *); 138 static void et_init_rxmac(struct et_softc *); 139 static void et_init_txmac(struct et_softc *); 140 static int et_init_rxdma(struct et_softc *); 141 static int et_init_txdma(struct et_softc *); 142 static int et_start_rxdma(struct et_softc *); 143 static int et_start_txdma(struct et_softc *); 144 static int et_stop_rxdma(struct et_softc *); 145 static int et_stop_txdma(struct et_softc *); 146 static void et_reset(struct et_softc *); 147 static int et_bus_config(struct et_softc *); 148 static void et_get_eaddr(device_t, uint8_t[]); 149 static void et_setmulti(struct et_softc *); 150 static void et_tick(void *); 151 static void et_stats_update(struct et_softc *); 152 153 static const struct et_dev { 154 uint16_t vid; 155 uint16_t did; 156 const char *desc; 157 } et_devices[] = { 158 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 159 "Agere ET1310 Gigabit Ethernet" }, 160 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 161 "Agere ET1310 Fast Ethernet" }, 162 { 0, 0, NULL } 163 }; 164 165 static device_method_t et_methods[] = { 166 DEVMETHOD(device_probe, et_probe), 167 DEVMETHOD(device_attach, et_attach), 168 DEVMETHOD(device_detach, et_detach), 169 DEVMETHOD(device_shutdown, et_shutdown), 170 DEVMETHOD(device_suspend, et_suspend), 171 DEVMETHOD(device_resume, et_resume), 172 173 DEVMETHOD(miibus_readreg, et_miibus_readreg), 174 DEVMETHOD(miibus_writereg, et_miibus_writereg), 175 DEVMETHOD(miibus_statchg, et_miibus_statchg), 176 177 DEVMETHOD_END 178 }; 179 180 static driver_t et_driver = { 181 "et", 182 et_methods, 183 sizeof(struct et_softc) 184 }; 185 186 DRIVER_MODULE(et, pci, et_driver, 0, 0); 187 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, et, et_devices, 188 nitems(et_devices) - 1); 189 DRIVER_MODULE(miibus, et, miibus_driver, 0, 0); 190 191 static int et_rx_intr_npkts = 32; 192 static int et_rx_intr_delay = 20; /* x10 usec */ 193 static int et_tx_intr_nsegs = 126; 194 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 195 196 TUNABLE_INT("hw.et.timer", &et_timer); 197 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 198 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 199 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 200 201 static int 202 et_probe(device_t dev) 203 { 204 const struct et_dev *d; 205 uint16_t did, vid; 206 207 vid = pci_get_vendor(dev); 208 did = pci_get_device(dev); 209 210 for (d = et_devices; d->desc != NULL; ++d) { 211 if (vid == d->vid && did == d->did) { 212 device_set_desc(dev, d->desc); 213 return (BUS_PROBE_DEFAULT); 214 } 215 } 216 return (ENXIO); 217 } 218 219 static int 220 et_attach(device_t dev) 221 { 222 struct et_softc *sc; 223 if_t ifp; 224 uint8_t eaddr[ETHER_ADDR_LEN]; 225 uint32_t pmcfg; 226 int cap, error, msic; 227 228 sc = device_get_softc(dev); 229 sc->dev = dev; 230 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 231 MTX_DEF); 232 callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 233 234 ifp = sc->ifp = if_alloc(IFT_ETHER); 235 236 /* 237 * Initialize tunables 238 */ 239 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 240 sc->sc_rx_intr_delay = et_rx_intr_delay; 241 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 242 sc->sc_timer = et_timer; 243 244 /* Enable bus mastering */ 245 pci_enable_busmaster(dev); 246 247 /* 248 * Allocate IO memory 249 */ 250 sc->sc_mem_rid = PCIR_BAR(0); 251 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 252 &sc->sc_mem_rid, RF_ACTIVE); 253 if (sc->sc_mem_res == NULL) { 254 device_printf(dev, "can't allocate IO memory\n"); 255 return (ENXIO); 256 } 257 258 msic = 0; 259 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 260 sc->sc_expcap = cap; 261 sc->sc_flags |= ET_FLAG_PCIE; 262 msic = pci_msi_count(dev); 263 if (bootverbose) 264 device_printf(dev, "MSI count: %d\n", msic); 265 } 266 if (msic > 0 && msi_disable == 0) { 267 msic = 1; 268 if (pci_alloc_msi(dev, &msic) == 0) { 269 if (msic == 1) { 270 device_printf(dev, "Using %d MSI message\n", 271 msic); 272 sc->sc_flags |= ET_FLAG_MSI; 273 } else 274 pci_release_msi(dev); 275 } 276 } 277 278 /* 279 * Allocate IRQ 280 */ 281 if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 282 sc->sc_irq_rid = 0; 283 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 284 &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 285 } else { 286 sc->sc_irq_rid = 1; 287 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 288 &sc->sc_irq_rid, RF_ACTIVE); 289 } 290 if (sc->sc_irq_res == NULL) { 291 device_printf(dev, "can't allocate irq\n"); 292 error = ENXIO; 293 goto fail; 294 } 295 296 if (pci_get_device(dev) == PCI_PRODUCT_LUCENT_ET1310_FAST) 297 sc->sc_flags |= ET_FLAG_FASTETHER; 298 299 error = et_bus_config(sc); 300 if (error) 301 goto fail; 302 303 et_get_eaddr(dev, eaddr); 304 305 /* Take PHY out of COMA and enable clocks. */ 306 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 307 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 308 pmcfg |= EM_PM_GIGEPHY_ENB; 309 CSR_WRITE_4(sc, ET_PM, pmcfg); 310 311 et_reset(sc); 312 313 error = et_dma_alloc(sc); 314 if (error) 315 goto fail; 316 317 if_setsoftc(ifp, sc); 318 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 319 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 320 if_setinitfn(ifp, et_init); 321 if_setioctlfn(ifp, et_ioctl); 322 if_setstartfn(ifp, et_start); 323 if_setgetcounterfn(ifp, et_get_counter); 324 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_VLAN_MTU); 325 if_setcapenable(ifp, if_getcapabilities(ifp)); 326 if_setsendqlen(ifp, ET_TX_NDESC - 1); 327 if_setsendqready(ifp); 328 329 et_chip_attach(sc); 330 331 error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd, 332 et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 333 MIIF_DOPAUSE); 334 if (error) { 335 device_printf(dev, "attaching PHYs failed\n"); 336 goto fail; 337 } 338 339 ether_ifattach(ifp, eaddr); 340 341 /* Tell the upper layer(s) we support long frames. */ 342 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 343 344 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 345 NULL, et_intr, sc, &sc->sc_irq_handle); 346 if (error) { 347 ether_ifdetach(ifp); 348 device_printf(dev, "can't setup intr\n"); 349 goto fail; 350 } 351 352 et_add_sysctls(sc); 353 354 return (0); 355 fail: 356 et_detach(dev); 357 return (error); 358 } 359 360 static int 361 et_detach(device_t dev) 362 { 363 struct et_softc *sc; 364 365 sc = device_get_softc(dev); 366 if (device_is_attached(dev)) { 367 ether_ifdetach(sc->ifp); 368 ET_LOCK(sc); 369 et_stop(sc); 370 ET_UNLOCK(sc); 371 callout_drain(&sc->sc_tick); 372 } 373 374 if (sc->sc_miibus != NULL) 375 device_delete_child(dev, sc->sc_miibus); 376 bus_generic_detach(dev); 377 378 if (sc->sc_irq_handle != NULL) 379 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 380 if (sc->sc_irq_res != NULL) 381 bus_release_resource(dev, SYS_RES_IRQ, 382 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 383 if ((sc->sc_flags & ET_FLAG_MSI) != 0) 384 pci_release_msi(dev); 385 if (sc->sc_mem_res != NULL) 386 bus_release_resource(dev, SYS_RES_MEMORY, 387 rman_get_rid(sc->sc_mem_res), sc->sc_mem_res); 388 389 if (sc->ifp != NULL) 390 if_free(sc->ifp); 391 392 et_dma_free(sc); 393 394 mtx_destroy(&sc->sc_mtx); 395 396 return (0); 397 } 398 399 static int 400 et_shutdown(device_t dev) 401 { 402 struct et_softc *sc; 403 404 sc = device_get_softc(dev); 405 ET_LOCK(sc); 406 et_stop(sc); 407 ET_UNLOCK(sc); 408 return (0); 409 } 410 411 static int 412 et_miibus_readreg(device_t dev, int phy, int reg) 413 { 414 struct et_softc *sc; 415 uint32_t val; 416 int i, ret; 417 418 sc = device_get_softc(dev); 419 /* Stop any pending operations */ 420 CSR_WRITE_4(sc, ET_MII_CMD, 0); 421 422 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 423 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 424 CSR_WRITE_4(sc, ET_MII_ADDR, val); 425 426 /* Start reading */ 427 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 428 429 #define NRETRY 50 430 431 for (i = 0; i < NRETRY; ++i) { 432 val = CSR_READ_4(sc, ET_MII_IND); 433 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 434 break; 435 DELAY(50); 436 } 437 if (i == NRETRY) { 438 if_printf(sc->ifp, 439 "read phy %d, reg %d timed out\n", phy, reg); 440 ret = 0; 441 goto back; 442 } 443 444 #undef NRETRY 445 446 val = CSR_READ_4(sc, ET_MII_STAT); 447 ret = val & ET_MII_STAT_VALUE_MASK; 448 449 back: 450 /* Make sure that the current operation is stopped */ 451 CSR_WRITE_4(sc, ET_MII_CMD, 0); 452 return (ret); 453 } 454 455 static int 456 et_miibus_writereg(device_t dev, int phy, int reg, int val0) 457 { 458 struct et_softc *sc; 459 uint32_t val; 460 int i; 461 462 sc = device_get_softc(dev); 463 /* Stop any pending operations */ 464 CSR_WRITE_4(sc, ET_MII_CMD, 0); 465 466 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 467 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 468 CSR_WRITE_4(sc, ET_MII_ADDR, val); 469 470 /* Start writing */ 471 CSR_WRITE_4(sc, ET_MII_CTRL, 472 (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 473 474 #define NRETRY 100 475 476 for (i = 0; i < NRETRY; ++i) { 477 val = CSR_READ_4(sc, ET_MII_IND); 478 if ((val & ET_MII_IND_BUSY) == 0) 479 break; 480 DELAY(50); 481 } 482 if (i == NRETRY) { 483 if_printf(sc->ifp, 484 "write phy %d, reg %d timed out\n", phy, reg); 485 et_miibus_readreg(dev, phy, reg); 486 } 487 488 #undef NRETRY 489 490 /* Make sure that the current operation is stopped */ 491 CSR_WRITE_4(sc, ET_MII_CMD, 0); 492 return (0); 493 } 494 495 static void 496 et_miibus_statchg(device_t dev) 497 { 498 struct et_softc *sc; 499 struct mii_data *mii; 500 if_t ifp; 501 uint32_t cfg1, cfg2, ctrl; 502 int i; 503 504 sc = device_get_softc(dev); 505 506 mii = device_get_softc(sc->sc_miibus); 507 ifp = sc->ifp; 508 if (mii == NULL || ifp == NULL || 509 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 510 return; 511 512 sc->sc_flags &= ~ET_FLAG_LINK; 513 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 514 (IFM_ACTIVE | IFM_AVALID)) { 515 switch (IFM_SUBTYPE(mii->mii_media_active)) { 516 case IFM_10_T: 517 case IFM_100_TX: 518 sc->sc_flags |= ET_FLAG_LINK; 519 break; 520 case IFM_1000_T: 521 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 522 sc->sc_flags |= ET_FLAG_LINK; 523 break; 524 } 525 } 526 527 /* XXX Stop TX/RX MAC? */ 528 if ((sc->sc_flags & ET_FLAG_LINK) == 0) 529 return; 530 531 /* Program MACs with resolved speed/duplex/flow-control. */ 532 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 533 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 534 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 535 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 536 ET_MAC_CFG1_LOOPBACK); 537 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 538 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 539 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 540 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 541 ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 542 ET_MAC_CFG2_PREAMBLE_LEN_MASK); 543 544 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 545 cfg2 |= ET_MAC_CFG2_MODE_GMII; 546 else { 547 cfg2 |= ET_MAC_CFG2_MODE_MII; 548 ctrl |= ET_MAC_CTRL_MODE_MII; 549 } 550 551 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { 552 cfg2 |= ET_MAC_CFG2_FDX; 553 /* 554 * Controller lacks automatic TX pause frame 555 * generation so it should be handled by driver. 556 * Even though driver can send pause frame with 557 * arbitrary pause time, controller does not 558 * provide a way that tells how many free RX 559 * buffers are available in controller. This 560 * limitation makes it hard to generate XON frame 561 * in time on driver side so don't enable TX flow 562 * control. 563 */ 564 #ifdef notyet 565 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) 566 cfg1 |= ET_MAC_CFG1_TXFLOW; 567 #endif 568 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) 569 cfg1 |= ET_MAC_CFG1_RXFLOW; 570 } else 571 ctrl |= ET_MAC_CTRL_GHDX; 572 573 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 574 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 575 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 576 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); 577 578 #define NRETRY 50 579 580 for (i = 0; i < NRETRY; ++i) { 581 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 582 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 583 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 584 break; 585 DELAY(100); 586 } 587 if (i == NRETRY) 588 if_printf(ifp, "can't enable RX/TX\n"); 589 sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 590 591 #undef NRETRY 592 } 593 594 static int 595 et_ifmedia_upd_locked(if_t ifp) 596 { 597 struct et_softc *sc; 598 struct mii_data *mii; 599 struct mii_softc *miisc; 600 601 sc = if_getsoftc(ifp); 602 mii = device_get_softc(sc->sc_miibus); 603 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 604 PHY_RESET(miisc); 605 return (mii_mediachg(mii)); 606 } 607 608 static int 609 et_ifmedia_upd(if_t ifp) 610 { 611 struct et_softc *sc; 612 int res; 613 614 sc = if_getsoftc(ifp); 615 ET_LOCK(sc); 616 res = et_ifmedia_upd_locked(ifp); 617 ET_UNLOCK(sc); 618 619 return (res); 620 } 621 622 static void 623 et_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 624 { 625 struct et_softc *sc; 626 struct mii_data *mii; 627 628 sc = if_getsoftc(ifp); 629 ET_LOCK(sc); 630 if ((if_getflags(ifp) & IFF_UP) == 0) { 631 ET_UNLOCK(sc); 632 return; 633 } 634 635 mii = device_get_softc(sc->sc_miibus); 636 mii_pollstat(mii); 637 ifmr->ifm_active = mii->mii_media_active; 638 ifmr->ifm_status = mii->mii_media_status; 639 ET_UNLOCK(sc); 640 } 641 642 static void 643 et_stop(struct et_softc *sc) 644 { 645 if_t ifp; 646 647 ET_LOCK_ASSERT(sc); 648 649 ifp = sc->ifp; 650 callout_stop(&sc->sc_tick); 651 /* Disable interrupts. */ 652 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 653 654 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( 655 ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN)); 656 DELAY(100); 657 658 et_stop_rxdma(sc); 659 et_stop_txdma(sc); 660 et_stats_update(sc); 661 662 et_free_tx_ring(sc); 663 et_free_rx_ring(sc); 664 665 sc->sc_tx = 0; 666 sc->sc_tx_intr = 0; 667 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 668 669 sc->watchdog_timer = 0; 670 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 671 } 672 673 static int 674 et_bus_config(struct et_softc *sc) 675 { 676 uint32_t val, max_plsz; 677 uint16_t ack_latency, replay_timer; 678 679 /* 680 * Test whether EEPROM is valid 681 * NOTE: Read twice to get the correct value 682 */ 683 pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 684 val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 685 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 686 device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 687 return (ENXIO); 688 } 689 690 /* TODO: LED */ 691 692 if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 693 return (0); 694 695 /* 696 * Configure ACK latency and replay timer according to 697 * max playload size 698 */ 699 val = pci_read_config(sc->dev, 700 sc->sc_expcap + PCIER_DEVICE_CAP, 4); 701 max_plsz = val & PCIEM_CAP_MAX_PAYLOAD; 702 703 switch (max_plsz) { 704 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 705 ack_latency = ET_PCIV_ACK_LATENCY_128; 706 replay_timer = ET_PCIV_REPLAY_TIMER_128; 707 break; 708 709 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 710 ack_latency = ET_PCIV_ACK_LATENCY_256; 711 replay_timer = ET_PCIV_REPLAY_TIMER_256; 712 break; 713 714 default: 715 ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 716 replay_timer = pci_read_config(sc->dev, 717 ET_PCIR_REPLAY_TIMER, 2); 718 device_printf(sc->dev, "ack latency %u, replay timer %u\n", 719 ack_latency, replay_timer); 720 break; 721 } 722 if (ack_latency != 0) { 723 pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 724 pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 725 2); 726 } 727 728 /* 729 * Set L0s and L1 latency timer to 2us 730 */ 731 val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 732 val &= ~(PCIEM_LINK_CAP_L0S_EXIT | PCIEM_LINK_CAP_L1_EXIT); 733 /* L0s exit latency : 2us */ 734 val |= 0x00005000; 735 /* L1 exit latency : 2us */ 736 val |= 0x00028000; 737 pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 738 739 /* 740 * Set max read request size to 2048 bytes 741 */ 742 pci_set_max_read_req(sc->dev, 2048); 743 744 return (0); 745 } 746 747 static void 748 et_get_eaddr(device_t dev, uint8_t eaddr[]) 749 { 750 uint32_t val; 751 int i; 752 753 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 754 for (i = 0; i < 4; ++i) 755 eaddr[i] = (val >> (8 * i)) & 0xff; 756 757 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 758 for (; i < ETHER_ADDR_LEN; ++i) 759 eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 760 } 761 762 static void 763 et_reset(struct et_softc *sc) 764 { 765 766 CSR_WRITE_4(sc, ET_MAC_CFG1, 767 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 768 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 769 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 770 771 CSR_WRITE_4(sc, ET_SWRST, 772 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 773 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 774 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 775 776 CSR_WRITE_4(sc, ET_MAC_CFG1, 777 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 778 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 779 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 780 /* Disable interrupts. */ 781 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 782 } 783 784 struct et_dmamap_arg { 785 bus_addr_t et_busaddr; 786 }; 787 788 static void 789 et_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 790 { 791 struct et_dmamap_arg *ctx; 792 793 if (error) 794 return; 795 796 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 797 798 ctx = arg; 799 ctx->et_busaddr = segs->ds_addr; 800 } 801 802 static int 803 et_dma_ring_alloc(struct et_softc *sc, bus_size_t alignment, bus_size_t maxsize, 804 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 805 const char *msg) 806 { 807 struct et_dmamap_arg ctx; 808 int error; 809 810 error = bus_dma_tag_create(sc->sc_dtag, alignment, 0, BUS_SPACE_MAXADDR, 811 BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, maxsize, 0, NULL, NULL, 812 tag); 813 if (error != 0) { 814 device_printf(sc->dev, "could not create %s dma tag\n", msg); 815 return (error); 816 } 817 /* Allocate DMA'able memory for ring. */ 818 error = bus_dmamem_alloc(*tag, (void **)ring, 819 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 820 if (error != 0) { 821 device_printf(sc->dev, 822 "could not allocate DMA'able memory for %s\n", msg); 823 return (error); 824 } 825 /* Load the address of the ring. */ 826 ctx.et_busaddr = 0; 827 error = bus_dmamap_load(*tag, *map, *ring, maxsize, et_dma_map_addr, 828 &ctx, BUS_DMA_NOWAIT); 829 if (error != 0) { 830 device_printf(sc->dev, 831 "could not load DMA'able memory for %s\n", msg); 832 return (error); 833 } 834 *paddr = ctx.et_busaddr; 835 return (0); 836 } 837 838 static void 839 et_dma_ring_free(struct et_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 840 bus_dmamap_t map, bus_addr_t *paddr) 841 { 842 843 if (*paddr != 0) { 844 bus_dmamap_unload(*tag, map); 845 *paddr = 0; 846 } 847 if (*ring != NULL) { 848 bus_dmamem_free(*tag, *ring, map); 849 *ring = NULL; 850 } 851 if (*tag) { 852 bus_dma_tag_destroy(*tag); 853 *tag = NULL; 854 } 855 } 856 857 static int 858 et_dma_alloc(struct et_softc *sc) 859 { 860 struct et_txdesc_ring *tx_ring; 861 struct et_rxdesc_ring *rx_ring; 862 struct et_rxstat_ring *rxst_ring; 863 struct et_rxstatus_data *rxsd; 864 struct et_rxbuf_data *rbd; 865 struct et_txbuf_data *tbd; 866 struct et_txstatus_data *txsd; 867 int i, error; 868 869 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 870 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 871 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 872 &sc->sc_dtag); 873 if (error != 0) { 874 device_printf(sc->dev, "could not allocate parent dma tag\n"); 875 return (error); 876 } 877 878 /* TX ring. */ 879 tx_ring = &sc->sc_tx_ring; 880 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_TX_RING_SIZE, 881 &tx_ring->tr_dtag, (uint8_t **)&tx_ring->tr_desc, &tx_ring->tr_dmap, 882 &tx_ring->tr_paddr, "TX ring"); 883 if (error) 884 return (error); 885 886 /* TX status block. */ 887 txsd = &sc->sc_tx_status; 888 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, sizeof(uint32_t), 889 &txsd->txsd_dtag, (uint8_t **)&txsd->txsd_status, &txsd->txsd_dmap, 890 &txsd->txsd_paddr, "TX status block"); 891 if (error) 892 return (error); 893 894 /* RX ring 0, used as to recive small sized frames. */ 895 rx_ring = &sc->sc_rx_ring[0]; 896 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 897 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 898 &rx_ring->rr_paddr, "RX ring 0"); 899 rx_ring->rr_posreg = ET_RX_RING0_POS; 900 if (error) 901 return (error); 902 903 /* RX ring 1, used as to store normal sized frames. */ 904 rx_ring = &sc->sc_rx_ring[1]; 905 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 906 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 907 &rx_ring->rr_paddr, "RX ring 1"); 908 rx_ring->rr_posreg = ET_RX_RING1_POS; 909 if (error) 910 return (error); 911 912 /* RX stat ring. */ 913 rxst_ring = &sc->sc_rxstat_ring; 914 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RXSTAT_RING_SIZE, 915 &rxst_ring->rsr_dtag, (uint8_t **)&rxst_ring->rsr_stat, 916 &rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr, "RX stat ring"); 917 if (error) 918 return (error); 919 920 /* RX status block. */ 921 rxsd = &sc->sc_rx_status; 922 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, 923 sizeof(struct et_rxstatus), &rxsd->rxsd_dtag, 924 (uint8_t **)&rxsd->rxsd_status, &rxsd->rxsd_dmap, 925 &rxsd->rxsd_paddr, "RX status block"); 926 if (error) 927 return (error); 928 929 /* Create parent DMA tag for mbufs. */ 930 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 931 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 932 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 933 &sc->sc_mbuf_dtag); 934 if (error != 0) { 935 device_printf(sc->dev, 936 "could not allocate parent dma tag for mbuf\n"); 937 return (error); 938 } 939 940 /* Create DMA tag for mini RX mbufs to use RX ring 0. */ 941 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 942 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 943 MHLEN, 0, NULL, NULL, &sc->sc_rx_mini_tag); 944 if (error) { 945 device_printf(sc->dev, "could not create mini RX dma tag\n"); 946 return (error); 947 } 948 949 /* Create DMA tag for standard RX mbufs to use RX ring 1. */ 950 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 951 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 952 MCLBYTES, 0, NULL, NULL, &sc->sc_rx_tag); 953 if (error) { 954 device_printf(sc->dev, "could not create RX dma tag\n"); 955 return (error); 956 } 957 958 /* Create DMA tag for TX mbufs. */ 959 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 960 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 961 MCLBYTES * ET_NSEG_MAX, ET_NSEG_MAX, MCLBYTES, 0, NULL, NULL, 962 &sc->sc_tx_tag); 963 if (error) { 964 device_printf(sc->dev, "could not create TX dma tag\n"); 965 return (error); 966 } 967 968 /* Initialize RX ring 0. */ 969 rbd = &sc->sc_rx_data[0]; 970 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING0_128; 971 rbd->rbd_newbuf = et_newbuf_hdr; 972 rbd->rbd_discard = et_rxbuf_discard; 973 rbd->rbd_softc = sc; 974 rbd->rbd_ring = &sc->sc_rx_ring[0]; 975 /* Create DMA maps for mini RX buffers, ring 0. */ 976 for (i = 0; i < ET_RX_NDESC; i++) { 977 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 978 &rbd->rbd_buf[i].rb_dmap); 979 if (error) { 980 device_printf(sc->dev, 981 "could not create DMA map for mini RX mbufs\n"); 982 return (error); 983 } 984 } 985 986 /* Create a spare DMA map for mini RX buffers, ring 0. */ 987 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 988 &sc->sc_rx_mini_sparemap); 989 if (error) { 990 device_printf(sc->dev, 991 "could not create spare DMA map for mini RX mbuf\n"); 992 return (error); 993 } 994 995 /* Initialize RX ring 1. */ 996 rbd = &sc->sc_rx_data[1]; 997 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING1_2048; 998 rbd->rbd_newbuf = et_newbuf_cluster; 999 rbd->rbd_discard = et_rxbuf_discard; 1000 rbd->rbd_softc = sc; 1001 rbd->rbd_ring = &sc->sc_rx_ring[1]; 1002 /* Create DMA maps for standard RX buffers, ring 1. */ 1003 for (i = 0; i < ET_RX_NDESC; i++) { 1004 error = bus_dmamap_create(sc->sc_rx_tag, 0, 1005 &rbd->rbd_buf[i].rb_dmap); 1006 if (error) { 1007 device_printf(sc->dev, 1008 "could not create DMA map for mini RX mbufs\n"); 1009 return (error); 1010 } 1011 } 1012 1013 /* Create a spare DMA map for standard RX buffers, ring 1. */ 1014 error = bus_dmamap_create(sc->sc_rx_tag, 0, &sc->sc_rx_sparemap); 1015 if (error) { 1016 device_printf(sc->dev, 1017 "could not create spare DMA map for RX mbuf\n"); 1018 return (error); 1019 } 1020 1021 /* Create DMA maps for TX buffers. */ 1022 tbd = &sc->sc_tx_data; 1023 for (i = 0; i < ET_TX_NDESC; i++) { 1024 error = bus_dmamap_create(sc->sc_tx_tag, 0, 1025 &tbd->tbd_buf[i].tb_dmap); 1026 if (error) { 1027 device_printf(sc->dev, 1028 "could not create DMA map for TX mbufs\n"); 1029 return (error); 1030 } 1031 } 1032 1033 return (0); 1034 } 1035 1036 static void 1037 et_dma_free(struct et_softc *sc) 1038 { 1039 struct et_txdesc_ring *tx_ring; 1040 struct et_rxdesc_ring *rx_ring; 1041 struct et_txstatus_data *txsd; 1042 struct et_rxstat_ring *rxst_ring; 1043 struct et_rxbuf_data *rbd; 1044 struct et_txbuf_data *tbd; 1045 int i; 1046 1047 /* Destroy DMA maps for mini RX buffers, ring 0. */ 1048 rbd = &sc->sc_rx_data[0]; 1049 for (i = 0; i < ET_RX_NDESC; i++) { 1050 if (rbd->rbd_buf[i].rb_dmap) { 1051 bus_dmamap_destroy(sc->sc_rx_mini_tag, 1052 rbd->rbd_buf[i].rb_dmap); 1053 rbd->rbd_buf[i].rb_dmap = NULL; 1054 } 1055 } 1056 if (sc->sc_rx_mini_sparemap) { 1057 bus_dmamap_destroy(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap); 1058 sc->sc_rx_mini_sparemap = NULL; 1059 } 1060 if (sc->sc_rx_mini_tag) { 1061 bus_dma_tag_destroy(sc->sc_rx_mini_tag); 1062 sc->sc_rx_mini_tag = NULL; 1063 } 1064 1065 /* Destroy DMA maps for standard RX buffers, ring 1. */ 1066 rbd = &sc->sc_rx_data[1]; 1067 for (i = 0; i < ET_RX_NDESC; i++) { 1068 if (rbd->rbd_buf[i].rb_dmap) { 1069 bus_dmamap_destroy(sc->sc_rx_tag, 1070 rbd->rbd_buf[i].rb_dmap); 1071 rbd->rbd_buf[i].rb_dmap = NULL; 1072 } 1073 } 1074 if (sc->sc_rx_sparemap) { 1075 bus_dmamap_destroy(sc->sc_rx_tag, sc->sc_rx_sparemap); 1076 sc->sc_rx_sparemap = NULL; 1077 } 1078 if (sc->sc_rx_tag) { 1079 bus_dma_tag_destroy(sc->sc_rx_tag); 1080 sc->sc_rx_tag = NULL; 1081 } 1082 1083 /* Destroy DMA maps for TX buffers. */ 1084 tbd = &sc->sc_tx_data; 1085 for (i = 0; i < ET_TX_NDESC; i++) { 1086 if (tbd->tbd_buf[i].tb_dmap) { 1087 bus_dmamap_destroy(sc->sc_tx_tag, 1088 tbd->tbd_buf[i].tb_dmap); 1089 tbd->tbd_buf[i].tb_dmap = NULL; 1090 } 1091 } 1092 if (sc->sc_tx_tag) { 1093 bus_dma_tag_destroy(sc->sc_tx_tag); 1094 sc->sc_tx_tag = NULL; 1095 } 1096 1097 /* Destroy mini RX ring, ring 0. */ 1098 rx_ring = &sc->sc_rx_ring[0]; 1099 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1100 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1101 /* Destroy standard RX ring, ring 1. */ 1102 rx_ring = &sc->sc_rx_ring[1]; 1103 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1104 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1105 /* Destroy RX stat ring. */ 1106 rxst_ring = &sc->sc_rxstat_ring; 1107 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1108 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1109 /* Destroy RX status block. */ 1110 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1111 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1112 /* Destroy TX ring. */ 1113 tx_ring = &sc->sc_tx_ring; 1114 et_dma_ring_free(sc, &tx_ring->tr_dtag, (void *)&tx_ring->tr_desc, 1115 tx_ring->tr_dmap, &tx_ring->tr_paddr); 1116 /* Destroy TX status block. */ 1117 txsd = &sc->sc_tx_status; 1118 et_dma_ring_free(sc, &txsd->txsd_dtag, (void *)&txsd->txsd_status, 1119 txsd->txsd_dmap, &txsd->txsd_paddr); 1120 1121 /* Destroy the parent tag. */ 1122 if (sc->sc_dtag) { 1123 bus_dma_tag_destroy(sc->sc_dtag); 1124 sc->sc_dtag = NULL; 1125 } 1126 } 1127 1128 static void 1129 et_chip_attach(struct et_softc *sc) 1130 { 1131 uint32_t val; 1132 1133 /* 1134 * Perform minimal initialization 1135 */ 1136 1137 /* Disable loopback */ 1138 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1139 1140 /* Reset MAC */ 1141 CSR_WRITE_4(sc, ET_MAC_CFG1, 1142 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1143 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1144 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1145 1146 /* 1147 * Setup half duplex mode 1148 */ 1149 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1150 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1151 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1152 ET_MAC_HDX_EXC_DEFER; 1153 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1154 1155 /* Clear MAC control */ 1156 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1157 1158 /* Reset MII */ 1159 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1160 1161 /* Bring MAC out of reset state */ 1162 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1163 1164 /* Enable memory controllers */ 1165 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1166 } 1167 1168 static void 1169 et_intr(void *xsc) 1170 { 1171 struct et_softc *sc; 1172 if_t ifp; 1173 uint32_t status; 1174 1175 sc = xsc; 1176 ET_LOCK(sc); 1177 ifp = sc->ifp; 1178 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1179 goto done; 1180 1181 status = CSR_READ_4(sc, ET_INTR_STATUS); 1182 if ((status & ET_INTRS) == 0) 1183 goto done; 1184 1185 /* Disable further interrupts. */ 1186 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 1187 1188 if (status & (ET_INTR_RXDMA_ERROR | ET_INTR_TXDMA_ERROR)) { 1189 device_printf(sc->dev, "DMA error(0x%08x) -- resetting\n", 1190 status); 1191 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1192 et_init_locked(sc); 1193 ET_UNLOCK(sc); 1194 return; 1195 } 1196 if (status & ET_INTR_RXDMA) 1197 et_rxeof(sc); 1198 if (status & (ET_INTR_TXDMA | ET_INTR_TIMER)) 1199 et_txeof(sc); 1200 if (status & ET_INTR_TIMER) 1201 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1202 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1203 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1204 if (!if_sendq_empty(ifp)) 1205 et_start_locked(ifp); 1206 } 1207 done: 1208 ET_UNLOCK(sc); 1209 } 1210 1211 static void 1212 et_init_locked(struct et_softc *sc) 1213 { 1214 if_t ifp; 1215 int error; 1216 1217 ET_LOCK_ASSERT(sc); 1218 1219 ifp = sc->ifp; 1220 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1221 return; 1222 1223 et_stop(sc); 1224 et_reset(sc); 1225 1226 et_init_tx_ring(sc); 1227 error = et_init_rx_ring(sc); 1228 if (error) 1229 return; 1230 1231 error = et_chip_init(sc); 1232 if (error) 1233 goto fail; 1234 1235 /* 1236 * Start TX/RX DMA engine 1237 */ 1238 error = et_start_rxdma(sc); 1239 if (error) 1240 return; 1241 1242 error = et_start_txdma(sc); 1243 if (error) 1244 return; 1245 1246 /* Enable interrupts. */ 1247 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1248 1249 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1250 1251 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1252 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1253 1254 sc->sc_flags &= ~ET_FLAG_LINK; 1255 et_ifmedia_upd_locked(ifp); 1256 1257 callout_reset(&sc->sc_tick, hz, et_tick, sc); 1258 1259 fail: 1260 if (error) 1261 et_stop(sc); 1262 } 1263 1264 static void 1265 et_init(void *xsc) 1266 { 1267 struct et_softc *sc = xsc; 1268 1269 ET_LOCK(sc); 1270 et_init_locked(sc); 1271 ET_UNLOCK(sc); 1272 } 1273 1274 static int 1275 et_ioctl(if_t ifp, u_long cmd, caddr_t data) 1276 { 1277 struct et_softc *sc; 1278 struct mii_data *mii; 1279 struct ifreq *ifr; 1280 int error, mask, max_framelen; 1281 1282 sc = if_getsoftc(ifp); 1283 ifr = (struct ifreq *)data; 1284 error = 0; 1285 1286 /* XXX LOCKSUSED */ 1287 switch (cmd) { 1288 case SIOCSIFFLAGS: 1289 ET_LOCK(sc); 1290 if (if_getflags(ifp) & IFF_UP) { 1291 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1292 if ((if_getflags(ifp) ^ sc->sc_if_flags) & 1293 (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 1294 et_setmulti(sc); 1295 } else { 1296 et_init_locked(sc); 1297 } 1298 } else { 1299 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1300 et_stop(sc); 1301 } 1302 sc->sc_if_flags = if_getflags(ifp); 1303 ET_UNLOCK(sc); 1304 break; 1305 1306 case SIOCSIFMEDIA: 1307 case SIOCGIFMEDIA: 1308 mii = device_get_softc(sc->sc_miibus); 1309 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1310 break; 1311 1312 case SIOCADDMULTI: 1313 case SIOCDELMULTI: 1314 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1315 ET_LOCK(sc); 1316 et_setmulti(sc); 1317 ET_UNLOCK(sc); 1318 } 1319 break; 1320 1321 case SIOCSIFMTU: 1322 ET_LOCK(sc); 1323 #if 0 1324 if (sc->sc_flags & ET_FLAG_JUMBO) 1325 max_framelen = ET_JUMBO_FRAMELEN; 1326 else 1327 #endif 1328 max_framelen = MCLBYTES - 1; 1329 1330 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1331 error = EOPNOTSUPP; 1332 ET_UNLOCK(sc); 1333 break; 1334 } 1335 1336 if (if_getmtu(ifp) != ifr->ifr_mtu) { 1337 if_setmtu(ifp, ifr->ifr_mtu); 1338 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1339 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1340 et_init_locked(sc); 1341 } 1342 } 1343 ET_UNLOCK(sc); 1344 break; 1345 1346 case SIOCSIFCAP: 1347 ET_LOCK(sc); 1348 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1349 if ((mask & IFCAP_TXCSUM) != 0 && 1350 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 1351 if_togglecapenable(ifp, IFCAP_TXCSUM); 1352 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 1353 if_sethwassistbits(ifp, ET_CSUM_FEATURES, 0); 1354 else 1355 if_sethwassistbits(ifp, 0, ET_CSUM_FEATURES); 1356 } 1357 ET_UNLOCK(sc); 1358 break; 1359 1360 default: 1361 error = ether_ioctl(ifp, cmd, data); 1362 break; 1363 } 1364 return (error); 1365 } 1366 1367 static void 1368 et_start_locked(if_t ifp) 1369 { 1370 struct et_softc *sc; 1371 struct mbuf *m_head = NULL; 1372 struct et_txdesc_ring *tx_ring; 1373 struct et_txbuf_data *tbd; 1374 uint32_t tx_ready_pos; 1375 int enq; 1376 1377 sc = if_getsoftc(ifp); 1378 ET_LOCK_ASSERT(sc); 1379 1380 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1381 IFF_DRV_RUNNING || 1382 (sc->sc_flags & (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) != 1383 (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) 1384 return; 1385 1386 /* 1387 * Driver does not request TX completion interrupt for every 1388 * queued frames to prevent generating excessive interrupts. 1389 * This means driver may wait for TX completion interrupt even 1390 * though some frames were successfully transmitted. Reclaiming 1391 * transmitted frames will ensure driver see all available 1392 * descriptors. 1393 */ 1394 tbd = &sc->sc_tx_data; 1395 if (tbd->tbd_used > (ET_TX_NDESC * 2) / 3) 1396 et_txeof(sc); 1397 1398 for (enq = 0; !if_sendq_empty(ifp); ) { 1399 if (tbd->tbd_used + ET_NSEG_SPARE >= ET_TX_NDESC) { 1400 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1401 break; 1402 } 1403 1404 m_head = if_dequeue(ifp); 1405 if (m_head == NULL) 1406 break; 1407 1408 if (et_encap(sc, &m_head)) { 1409 if (m_head == NULL) { 1410 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1411 break; 1412 } 1413 if_sendq_prepend(ifp, m_head); 1414 if (tbd->tbd_used > 0) 1415 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1416 break; 1417 } 1418 enq++; 1419 ETHER_BPF_MTAP(ifp, m_head); 1420 } 1421 1422 if (enq > 0) { 1423 tx_ring = &sc->sc_tx_ring; 1424 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1425 BUS_DMASYNC_PREWRITE); 1426 tx_ready_pos = tx_ring->tr_ready_index & 1427 ET_TX_READY_POS_INDEX_MASK; 1428 if (tx_ring->tr_ready_wrap) 1429 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1430 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1431 sc->watchdog_timer = 5; 1432 } 1433 } 1434 1435 static void 1436 et_start(if_t ifp) 1437 { 1438 struct et_softc *sc; 1439 1440 sc = if_getsoftc(ifp); 1441 ET_LOCK(sc); 1442 et_start_locked(ifp); 1443 ET_UNLOCK(sc); 1444 } 1445 1446 static int 1447 et_watchdog(struct et_softc *sc) 1448 { 1449 uint32_t status; 1450 1451 ET_LOCK_ASSERT(sc); 1452 1453 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1454 return (0); 1455 1456 bus_dmamap_sync(sc->sc_tx_status.txsd_dtag, sc->sc_tx_status.txsd_dmap, 1457 BUS_DMASYNC_POSTREAD); 1458 status = le32toh(*(sc->sc_tx_status.txsd_status)); 1459 if_printf(sc->ifp, "watchdog timed out (0x%08x) -- resetting\n", 1460 status); 1461 1462 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1); 1463 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING); 1464 et_init_locked(sc); 1465 return (EJUSTRETURN); 1466 } 1467 1468 static int 1469 et_stop_rxdma(struct et_softc *sc) 1470 { 1471 1472 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1473 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1474 1475 DELAY(5); 1476 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1477 if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1478 return (ETIMEDOUT); 1479 } 1480 return (0); 1481 } 1482 1483 static int 1484 et_stop_txdma(struct et_softc *sc) 1485 { 1486 1487 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1488 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1489 return (0); 1490 } 1491 1492 static void 1493 et_free_tx_ring(struct et_softc *sc) 1494 { 1495 struct et_txbuf_data *tbd; 1496 struct et_txbuf *tb; 1497 int i; 1498 1499 tbd = &sc->sc_tx_data; 1500 for (i = 0; i < ET_TX_NDESC; ++i) { 1501 tb = &tbd->tbd_buf[i]; 1502 if (tb->tb_mbuf != NULL) { 1503 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 1504 BUS_DMASYNC_POSTWRITE); 1505 bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 1506 m_freem(tb->tb_mbuf); 1507 tb->tb_mbuf = NULL; 1508 } 1509 } 1510 } 1511 1512 static void 1513 et_free_rx_ring(struct et_softc *sc) 1514 { 1515 struct et_rxbuf_data *rbd; 1516 struct et_rxdesc_ring *rx_ring; 1517 struct et_rxbuf *rb; 1518 int i; 1519 1520 /* Ring 0 */ 1521 rx_ring = &sc->sc_rx_ring[0]; 1522 rbd = &sc->sc_rx_data[0]; 1523 for (i = 0; i < ET_RX_NDESC; ++i) { 1524 rb = &rbd->rbd_buf[i]; 1525 if (rb->rb_mbuf != NULL) { 1526 bus_dmamap_sync(sc->sc_rx_mini_tag, rx_ring->rr_dmap, 1527 BUS_DMASYNC_POSTREAD); 1528 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 1529 m_freem(rb->rb_mbuf); 1530 rb->rb_mbuf = NULL; 1531 } 1532 } 1533 1534 /* Ring 1 */ 1535 rx_ring = &sc->sc_rx_ring[1]; 1536 rbd = &sc->sc_rx_data[1]; 1537 for (i = 0; i < ET_RX_NDESC; ++i) { 1538 rb = &rbd->rbd_buf[i]; 1539 if (rb->rb_mbuf != NULL) { 1540 bus_dmamap_sync(sc->sc_rx_tag, rx_ring->rr_dmap, 1541 BUS_DMASYNC_POSTREAD); 1542 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 1543 m_freem(rb->rb_mbuf); 1544 rb->rb_mbuf = NULL; 1545 } 1546 } 1547 } 1548 1549 static u_int 1550 et_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1551 { 1552 uint32_t h, *hp, *hash = arg; 1553 1554 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 1555 h = (h & 0x3f800000) >> 23; 1556 1557 hp = &hash[0]; 1558 if (h >= 32 && h < 64) { 1559 h -= 32; 1560 hp = &hash[1]; 1561 } else if (h >= 64 && h < 96) { 1562 h -= 64; 1563 hp = &hash[2]; 1564 } else if (h >= 96) { 1565 h -= 96; 1566 hp = &hash[3]; 1567 } 1568 *hp |= (1 << h); 1569 1570 return (1); 1571 } 1572 1573 static void 1574 et_setmulti(struct et_softc *sc) 1575 { 1576 if_t ifp; 1577 uint32_t hash[4] = { 0, 0, 0, 0 }; 1578 uint32_t rxmac_ctrl, pktfilt; 1579 int i, count; 1580 1581 ET_LOCK_ASSERT(sc); 1582 ifp = sc->ifp; 1583 1584 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1585 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1586 1587 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1588 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) { 1589 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1590 goto back; 1591 } 1592 1593 count = if_foreach_llmaddr(ifp, et_hash_maddr, &hash); 1594 1595 for (i = 0; i < 4; ++i) 1596 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1597 1598 if (count > 0) 1599 pktfilt |= ET_PKTFILT_MCAST; 1600 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1601 back: 1602 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1603 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1604 } 1605 1606 static int 1607 et_chip_init(struct et_softc *sc) 1608 { 1609 if_t ifp; 1610 uint32_t rxq_end; 1611 int error, frame_len, rxmem_size; 1612 1613 ifp = sc->ifp; 1614 /* 1615 * Split 16Kbytes internal memory between TX and RX 1616 * according to frame length. 1617 */ 1618 frame_len = ET_FRAMELEN(if_getmtu(ifp)); 1619 if (frame_len < 2048) { 1620 rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1621 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1622 rxmem_size = ET_MEM_SIZE / 2; 1623 } else { 1624 rxmem_size = ET_MEM_SIZE - 1625 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1626 } 1627 rxq_end = ET_QUEUE_ADDR(rxmem_size); 1628 1629 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1630 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1631 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1632 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1633 1634 /* No loopback */ 1635 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1636 1637 /* Clear MSI configure */ 1638 if ((sc->sc_flags & ET_FLAG_MSI) == 0) 1639 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1640 1641 /* Disable timer */ 1642 CSR_WRITE_4(sc, ET_TIMER, 0); 1643 1644 /* Initialize MAC */ 1645 et_init_mac(sc); 1646 1647 /* Enable memory controllers */ 1648 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1649 1650 /* Initialize RX MAC */ 1651 et_init_rxmac(sc); 1652 1653 /* Initialize TX MAC */ 1654 et_init_txmac(sc); 1655 1656 /* Initialize RX DMA engine */ 1657 error = et_init_rxdma(sc); 1658 if (error) 1659 return (error); 1660 1661 /* Initialize TX DMA engine */ 1662 error = et_init_txdma(sc); 1663 if (error) 1664 return (error); 1665 1666 return (0); 1667 } 1668 1669 static void 1670 et_init_tx_ring(struct et_softc *sc) 1671 { 1672 struct et_txdesc_ring *tx_ring; 1673 struct et_txbuf_data *tbd; 1674 struct et_txstatus_data *txsd; 1675 1676 tx_ring = &sc->sc_tx_ring; 1677 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1678 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1679 BUS_DMASYNC_PREWRITE); 1680 1681 tbd = &sc->sc_tx_data; 1682 tbd->tbd_start_index = 0; 1683 tbd->tbd_start_wrap = 0; 1684 tbd->tbd_used = 0; 1685 1686 txsd = &sc->sc_tx_status; 1687 bzero(txsd->txsd_status, sizeof(uint32_t)); 1688 bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 1689 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1690 } 1691 1692 static int 1693 et_init_rx_ring(struct et_softc *sc) 1694 { 1695 struct et_rxstatus_data *rxsd; 1696 struct et_rxstat_ring *rxst_ring; 1697 struct et_rxbuf_data *rbd; 1698 int i, error, n; 1699 1700 for (n = 0; n < ET_RX_NRING; ++n) { 1701 rbd = &sc->sc_rx_data[n]; 1702 for (i = 0; i < ET_RX_NDESC; ++i) { 1703 error = rbd->rbd_newbuf(rbd, i); 1704 if (error) { 1705 if_printf(sc->ifp, "%d ring %d buf, " 1706 "newbuf failed: %d\n", n, i, error); 1707 return (error); 1708 } 1709 } 1710 } 1711 1712 rxsd = &sc->sc_rx_status; 1713 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1714 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1715 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1716 1717 rxst_ring = &sc->sc_rxstat_ring; 1718 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1719 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1720 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1721 1722 return (0); 1723 } 1724 1725 static int 1726 et_init_rxdma(struct et_softc *sc) 1727 { 1728 struct et_rxstatus_data *rxsd; 1729 struct et_rxstat_ring *rxst_ring; 1730 struct et_rxdesc_ring *rx_ring; 1731 int error; 1732 1733 error = et_stop_rxdma(sc); 1734 if (error) { 1735 if_printf(sc->ifp, "can't init RX DMA engine\n"); 1736 return (error); 1737 } 1738 1739 /* 1740 * Install RX status 1741 */ 1742 rxsd = &sc->sc_rx_status; 1743 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1744 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1745 1746 /* 1747 * Install RX stat ring 1748 */ 1749 rxst_ring = &sc->sc_rxstat_ring; 1750 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1751 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1752 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1753 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1754 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1755 1756 /* Match ET_RXSTAT_POS */ 1757 rxst_ring->rsr_index = 0; 1758 rxst_ring->rsr_wrap = 0; 1759 1760 /* 1761 * Install the 2nd RX descriptor ring 1762 */ 1763 rx_ring = &sc->sc_rx_ring[1]; 1764 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1765 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1766 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1767 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1768 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1769 1770 /* Match ET_RX_RING1_POS */ 1771 rx_ring->rr_index = 0; 1772 rx_ring->rr_wrap = 1; 1773 1774 /* 1775 * Install the 1st RX descriptor ring 1776 */ 1777 rx_ring = &sc->sc_rx_ring[0]; 1778 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1779 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1780 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1781 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1782 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1783 1784 /* Match ET_RX_RING0_POS */ 1785 rx_ring->rr_index = 0; 1786 rx_ring->rr_wrap = 1; 1787 1788 /* 1789 * RX intr moderation 1790 */ 1791 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1792 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1793 1794 return (0); 1795 } 1796 1797 static int 1798 et_init_txdma(struct et_softc *sc) 1799 { 1800 struct et_txdesc_ring *tx_ring; 1801 struct et_txstatus_data *txsd; 1802 int error; 1803 1804 error = et_stop_txdma(sc); 1805 if (error) { 1806 if_printf(sc->ifp, "can't init TX DMA engine\n"); 1807 return (error); 1808 } 1809 1810 /* 1811 * Install TX descriptor ring 1812 */ 1813 tx_ring = &sc->sc_tx_ring; 1814 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1815 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1816 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1817 1818 /* 1819 * Install TX status 1820 */ 1821 txsd = &sc->sc_tx_status; 1822 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1823 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1824 1825 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1826 1827 /* Match ET_TX_READY_POS */ 1828 tx_ring->tr_ready_index = 0; 1829 tx_ring->tr_ready_wrap = 0; 1830 1831 return (0); 1832 } 1833 1834 static void 1835 et_init_mac(struct et_softc *sc) 1836 { 1837 if_t ifp; 1838 const uint8_t *eaddr; 1839 uint32_t val; 1840 1841 /* Reset MAC */ 1842 CSR_WRITE_4(sc, ET_MAC_CFG1, 1843 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1844 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1845 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1846 1847 /* 1848 * Setup inter packet gap 1849 */ 1850 val = (56 << ET_IPG_NONB2B_1_SHIFT) | 1851 (88 << ET_IPG_NONB2B_2_SHIFT) | 1852 (80 << ET_IPG_MINIFG_SHIFT) | 1853 (96 << ET_IPG_B2B_SHIFT); 1854 CSR_WRITE_4(sc, ET_IPG, val); 1855 1856 /* 1857 * Setup half duplex mode 1858 */ 1859 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1860 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1861 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1862 ET_MAC_HDX_EXC_DEFER; 1863 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1864 1865 /* Clear MAC control */ 1866 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1867 1868 /* Reset MII */ 1869 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1870 1871 /* 1872 * Set MAC address 1873 */ 1874 ifp = sc->ifp; 1875 eaddr = if_getlladdr(ifp); 1876 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1877 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1878 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1879 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1880 1881 /* Set max frame length */ 1882 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(if_getmtu(ifp))); 1883 1884 /* Bring MAC out of reset state */ 1885 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1886 } 1887 1888 static void 1889 et_init_rxmac(struct et_softc *sc) 1890 { 1891 if_t ifp; 1892 const uint8_t *eaddr; 1893 uint32_t val; 1894 int i; 1895 1896 /* Disable RX MAC and WOL */ 1897 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1898 1899 /* 1900 * Clear all WOL related registers 1901 */ 1902 for (i = 0; i < 3; ++i) 1903 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1904 for (i = 0; i < 20; ++i) 1905 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1906 1907 /* 1908 * Set WOL source address. XXX is this necessary? 1909 */ 1910 ifp = sc->ifp; 1911 eaddr = if_getlladdr(ifp); 1912 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1913 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1914 val = (eaddr[0] << 8) | eaddr[1]; 1915 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1916 1917 /* Clear packet filters */ 1918 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1919 1920 /* No ucast filtering */ 1921 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1922 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1923 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1924 1925 if (ET_FRAMELEN(if_getmtu(ifp)) > ET_RXMAC_CUT_THRU_FRMLEN) { 1926 /* 1927 * In order to transmit jumbo packets greater than 1928 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1929 * RX MAC and RX DMA needs to be reduced in size to 1930 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1931 * order to implement this, we must use "cut through" 1932 * mode in the RX MAC, which chops packets down into 1933 * segments. In this case we selected 256 bytes, 1934 * since this is the size of the PCI-Express TLP's 1935 * that the ET1310 uses. 1936 */ 1937 val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 1938 ET_RXMAC_MC_SEGSZ_ENABLE; 1939 } else { 1940 val = 0; 1941 } 1942 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1943 1944 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1945 1946 /* Initialize RX MAC management register */ 1947 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1948 1949 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1950 1951 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1952 ET_RXMAC_MGT_PASS_ECRC | 1953 ET_RXMAC_MGT_PASS_ELEN | 1954 ET_RXMAC_MGT_PASS_ETRUNC | 1955 ET_RXMAC_MGT_CHECK_PKT); 1956 1957 /* 1958 * Configure runt filtering (may not work on certain chip generation) 1959 */ 1960 val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 1961 ET_PKTFILT_MINLEN_MASK; 1962 val |= ET_PKTFILT_FRAG; 1963 CSR_WRITE_4(sc, ET_PKTFILT, val); 1964 1965 /* Enable RX MAC but leave WOL disabled */ 1966 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1967 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1968 1969 /* 1970 * Setup multicast hash and allmulti/promisc mode 1971 */ 1972 et_setmulti(sc); 1973 } 1974 1975 static void 1976 et_init_txmac(struct et_softc *sc) 1977 { 1978 1979 /* Disable TX MAC and FC(?) */ 1980 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1981 1982 /* 1983 * Initialize pause time. 1984 * This register should be set before XON/XOFF frame is 1985 * sent by driver. 1986 */ 1987 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0 << ET_TXMAC_FLOWCTRL_CFPT_SHIFT); 1988 1989 /* Enable TX MAC but leave FC(?) disabled */ 1990 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1991 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1992 } 1993 1994 static int 1995 et_start_rxdma(struct et_softc *sc) 1996 { 1997 uint32_t val; 1998 1999 val = (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 2000 ET_RXDMA_CTRL_RING0_ENABLE; 2001 val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 2002 ET_RXDMA_CTRL_RING1_ENABLE; 2003 2004 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 2005 2006 DELAY(5); 2007 2008 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 2009 if_printf(sc->ifp, "can't start RX DMA engine\n"); 2010 return (ETIMEDOUT); 2011 } 2012 return (0); 2013 } 2014 2015 static int 2016 et_start_txdma(struct et_softc *sc) 2017 { 2018 2019 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 2020 return (0); 2021 } 2022 2023 static void 2024 et_rxeof(struct et_softc *sc) 2025 { 2026 struct et_rxstatus_data *rxsd; 2027 struct et_rxstat_ring *rxst_ring; 2028 struct et_rxbuf_data *rbd; 2029 struct et_rxdesc_ring *rx_ring; 2030 struct et_rxstat *st; 2031 if_t ifp; 2032 struct mbuf *m; 2033 uint32_t rxstat_pos, rxring_pos; 2034 uint32_t rxst_info1, rxst_info2, rxs_stat_ring; 2035 int buflen, buf_idx, npost[2], ring_idx; 2036 int rxst_index, rxst_wrap; 2037 2038 ET_LOCK_ASSERT(sc); 2039 2040 ifp = sc->ifp; 2041 rxsd = &sc->sc_rx_status; 2042 rxst_ring = &sc->sc_rxstat_ring; 2043 2044 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2045 return; 2046 2047 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2048 BUS_DMASYNC_POSTREAD); 2049 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2050 BUS_DMASYNC_POSTREAD); 2051 2052 npost[0] = npost[1] = 0; 2053 rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 2054 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 2055 rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 2056 ET_RXS_STATRING_INDEX_SHIFT; 2057 2058 while (rxst_index != rxst_ring->rsr_index || 2059 rxst_wrap != rxst_ring->rsr_wrap) { 2060 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2061 break; 2062 2063 MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 2064 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 2065 rxst_info1 = le32toh(st->rxst_info1); 2066 rxst_info2 = le32toh(st->rxst_info2); 2067 buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 2068 ET_RXST_INFO2_LEN_SHIFT; 2069 buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 2070 ET_RXST_INFO2_BUFIDX_SHIFT; 2071 ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 2072 ET_RXST_INFO2_RINGIDX_SHIFT; 2073 2074 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 2075 rxst_ring->rsr_index = 0; 2076 rxst_ring->rsr_wrap ^= 1; 2077 } 2078 rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 2079 if (rxst_ring->rsr_wrap) 2080 rxstat_pos |= ET_RXSTAT_POS_WRAP; 2081 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 2082 2083 if (ring_idx >= ET_RX_NRING) { 2084 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2085 if_printf(ifp, "invalid ring index %d\n", ring_idx); 2086 continue; 2087 } 2088 if (buf_idx >= ET_RX_NDESC) { 2089 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2090 if_printf(ifp, "invalid buf index %d\n", buf_idx); 2091 continue; 2092 } 2093 2094 rbd = &sc->sc_rx_data[ring_idx]; 2095 m = rbd->rbd_buf[buf_idx].rb_mbuf; 2096 if ((rxst_info1 & ET_RXST_INFO1_OK) == 0){ 2097 /* Discard errored frame. */ 2098 rbd->rbd_discard(rbd, buf_idx); 2099 } else if (rbd->rbd_newbuf(rbd, buf_idx) != 0) { 2100 /* No available mbufs, discard it. */ 2101 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2102 rbd->rbd_discard(rbd, buf_idx); 2103 } else { 2104 buflen -= ETHER_CRC_LEN; 2105 if (buflen < ETHER_HDR_LEN) { 2106 m_freem(m); 2107 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2108 } else { 2109 m->m_pkthdr.len = m->m_len = buflen; 2110 m->m_pkthdr.rcvif = ifp; 2111 ET_UNLOCK(sc); 2112 if_input(ifp, m); 2113 ET_LOCK(sc); 2114 } 2115 } 2116 2117 rx_ring = &sc->sc_rx_ring[ring_idx]; 2118 if (buf_idx != rx_ring->rr_index) { 2119 if_printf(ifp, 2120 "WARNING!! ring %d, buf_idx %d, rr_idx %d\n", 2121 ring_idx, buf_idx, rx_ring->rr_index); 2122 } 2123 2124 MPASS(rx_ring->rr_index < ET_RX_NDESC); 2125 if (++rx_ring->rr_index == ET_RX_NDESC) { 2126 rx_ring->rr_index = 0; 2127 rx_ring->rr_wrap ^= 1; 2128 } 2129 rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 2130 if (rx_ring->rr_wrap) 2131 rxring_pos |= ET_RX_RING_POS_WRAP; 2132 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 2133 } 2134 2135 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2136 BUS_DMASYNC_PREREAD); 2137 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2138 BUS_DMASYNC_PREREAD); 2139 } 2140 2141 static int 2142 et_encap(struct et_softc *sc, struct mbuf **m0) 2143 { 2144 struct et_txdesc_ring *tx_ring; 2145 struct et_txbuf_data *tbd; 2146 struct et_txdesc *td; 2147 struct mbuf *m; 2148 bus_dma_segment_t segs[ET_NSEG_MAX]; 2149 bus_dmamap_t map; 2150 uint32_t csum_flags, last_td_ctrl2; 2151 int error, i, idx, first_idx, last_idx, nsegs; 2152 2153 tx_ring = &sc->sc_tx_ring; 2154 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2155 tbd = &sc->sc_tx_data; 2156 first_idx = tx_ring->tr_ready_index; 2157 map = tbd->tbd_buf[first_idx].tb_dmap; 2158 2159 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, &nsegs, 2160 0); 2161 if (error == EFBIG) { 2162 m = m_collapse(*m0, M_NOWAIT, ET_NSEG_MAX); 2163 if (m == NULL) { 2164 m_freem(*m0); 2165 *m0 = NULL; 2166 return (ENOMEM); 2167 } 2168 *m0 = m; 2169 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, 2170 &nsegs, 0); 2171 if (error != 0) { 2172 m_freem(*m0); 2173 *m0 = NULL; 2174 return (error); 2175 } 2176 } else if (error != 0) 2177 return (error); 2178 2179 /* Check for descriptor overruns. */ 2180 if (tbd->tbd_used + nsegs > ET_TX_NDESC - 1) { 2181 bus_dmamap_unload(sc->sc_tx_tag, map); 2182 return (ENOBUFS); 2183 } 2184 bus_dmamap_sync(sc->sc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2185 2186 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 2187 sc->sc_tx += nsegs; 2188 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 2189 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 2190 last_td_ctrl2 |= ET_TDCTRL2_INTR; 2191 } 2192 2193 m = *m0; 2194 csum_flags = 0; 2195 if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 2196 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2197 csum_flags |= ET_TDCTRL2_CSUM_IP; 2198 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2199 csum_flags |= ET_TDCTRL2_CSUM_UDP; 2200 else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2201 csum_flags |= ET_TDCTRL2_CSUM_TCP; 2202 } 2203 last_idx = -1; 2204 for (i = 0; i < nsegs; ++i) { 2205 idx = (first_idx + i) % ET_TX_NDESC; 2206 td = &tx_ring->tr_desc[idx]; 2207 td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 2208 td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 2209 td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 2210 if (i == nsegs - 1) { 2211 /* Last frag */ 2212 td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 2213 last_idx = idx; 2214 } else 2215 td->td_ctrl2 = htole32(csum_flags); 2216 2217 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2218 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 2219 tx_ring->tr_ready_index = 0; 2220 tx_ring->tr_ready_wrap ^= 1; 2221 } 2222 } 2223 td = &tx_ring->tr_desc[first_idx]; 2224 /* First frag */ 2225 td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); 2226 2227 MPASS(last_idx >= 0); 2228 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 2229 tbd->tbd_buf[last_idx].tb_dmap = map; 2230 tbd->tbd_buf[last_idx].tb_mbuf = m; 2231 2232 tbd->tbd_used += nsegs; 2233 MPASS(tbd->tbd_used <= ET_TX_NDESC); 2234 2235 return (0); 2236 } 2237 2238 static void 2239 et_txeof(struct et_softc *sc) 2240 { 2241 struct et_txdesc_ring *tx_ring; 2242 struct et_txbuf_data *tbd; 2243 struct et_txbuf *tb; 2244 if_t ifp; 2245 uint32_t tx_done; 2246 int end, wrap; 2247 2248 ET_LOCK_ASSERT(sc); 2249 2250 ifp = sc->ifp; 2251 tx_ring = &sc->sc_tx_ring; 2252 tbd = &sc->sc_tx_data; 2253 2254 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2255 return; 2256 2257 if (tbd->tbd_used == 0) 2258 return; 2259 2260 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2261 BUS_DMASYNC_POSTWRITE); 2262 2263 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2264 end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 2265 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2266 2267 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2268 MPASS(tbd->tbd_start_index < ET_TX_NDESC); 2269 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2270 if (tb->tb_mbuf != NULL) { 2271 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 2272 BUS_DMASYNC_POSTWRITE); 2273 bus_dmamap_unload(sc->sc_tx_tag, tb->tb_dmap); 2274 m_freem(tb->tb_mbuf); 2275 tb->tb_mbuf = NULL; 2276 } 2277 2278 if (++tbd->tbd_start_index == ET_TX_NDESC) { 2279 tbd->tbd_start_index = 0; 2280 tbd->tbd_start_wrap ^= 1; 2281 } 2282 2283 MPASS(tbd->tbd_used > 0); 2284 tbd->tbd_used--; 2285 } 2286 2287 if (tbd->tbd_used == 0) 2288 sc->watchdog_timer = 0; 2289 if (tbd->tbd_used + ET_NSEG_SPARE < ET_TX_NDESC) 2290 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2291 } 2292 2293 static void 2294 et_tick(void *xsc) 2295 { 2296 struct et_softc *sc; 2297 struct mii_data *mii; 2298 2299 sc = xsc; 2300 ET_LOCK_ASSERT(sc); 2301 mii = device_get_softc(sc->sc_miibus); 2302 2303 mii_tick(mii); 2304 et_stats_update(sc); 2305 if (et_watchdog(sc) == EJUSTRETURN) 2306 return; 2307 callout_reset(&sc->sc_tick, hz, et_tick, sc); 2308 } 2309 2310 static int 2311 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx) 2312 { 2313 struct et_softc *sc; 2314 struct et_rxdesc *desc; 2315 struct et_rxbuf *rb; 2316 struct mbuf *m; 2317 bus_dma_segment_t segs[1]; 2318 bus_dmamap_t dmap; 2319 int nsegs; 2320 2321 MPASS(buf_idx < ET_RX_NDESC); 2322 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2323 if (m == NULL) 2324 return (ENOBUFS); 2325 m->m_len = m->m_pkthdr.len = MCLBYTES; 2326 m_adj(m, ETHER_ALIGN); 2327 2328 sc = rbd->rbd_softc; 2329 rb = &rbd->rbd_buf[buf_idx]; 2330 2331 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_tag, sc->sc_rx_sparemap, m, 2332 segs, &nsegs, 0) != 0) { 2333 m_freem(m); 2334 return (ENOBUFS); 2335 } 2336 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2337 2338 if (rb->rb_mbuf != NULL) { 2339 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, 2340 BUS_DMASYNC_POSTREAD); 2341 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 2342 } 2343 dmap = rb->rb_dmap; 2344 rb->rb_dmap = sc->sc_rx_sparemap; 2345 sc->sc_rx_sparemap = dmap; 2346 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2347 2348 rb->rb_mbuf = m; 2349 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2350 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2351 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2352 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2353 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2354 BUS_DMASYNC_PREWRITE); 2355 return (0); 2356 } 2357 2358 static void 2359 et_rxbuf_discard(struct et_rxbuf_data *rbd, int buf_idx) 2360 { 2361 struct et_rxdesc *desc; 2362 2363 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2364 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2365 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2366 BUS_DMASYNC_PREWRITE); 2367 } 2368 2369 static int 2370 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx) 2371 { 2372 struct et_softc *sc; 2373 struct et_rxdesc *desc; 2374 struct et_rxbuf *rb; 2375 struct mbuf *m; 2376 bus_dma_segment_t segs[1]; 2377 bus_dmamap_t dmap; 2378 int nsegs; 2379 2380 MPASS(buf_idx < ET_RX_NDESC); 2381 MGETHDR(m, M_NOWAIT, MT_DATA); 2382 if (m == NULL) 2383 return (ENOBUFS); 2384 m->m_len = m->m_pkthdr.len = MHLEN; 2385 m_adj(m, ETHER_ALIGN); 2386 2387 sc = rbd->rbd_softc; 2388 rb = &rbd->rbd_buf[buf_idx]; 2389 2390 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap, 2391 m, segs, &nsegs, 0) != 0) { 2392 m_freem(m); 2393 return (ENOBUFS); 2394 } 2395 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2396 2397 if (rb->rb_mbuf != NULL) { 2398 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, 2399 BUS_DMASYNC_POSTREAD); 2400 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 2401 } 2402 dmap = rb->rb_dmap; 2403 rb->rb_dmap = sc->sc_rx_mini_sparemap; 2404 sc->sc_rx_mini_sparemap = dmap; 2405 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2406 2407 rb->rb_mbuf = m; 2408 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2409 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2410 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2411 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2412 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2413 BUS_DMASYNC_PREWRITE); 2414 return (0); 2415 } 2416 2417 #define ET_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2418 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2419 #define ET_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2420 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2421 2422 /* 2423 * Create sysctl tree 2424 */ 2425 static void 2426 et_add_sysctls(struct et_softc * sc) 2427 { 2428 struct sysctl_ctx_list *ctx; 2429 struct sysctl_oid_list *children, *parent; 2430 struct sysctl_oid *tree; 2431 struct et_hw_stats *stats; 2432 2433 ctx = device_get_sysctl_ctx(sc->dev); 2434 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2435 2436 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 2437 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2438 et_sysctl_rx_intr_npkts, "I", "RX IM, # packets per RX interrupt"); 2439 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 2440 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2441 et_sysctl_rx_intr_delay, "I", 2442 "RX IM, RX interrupt delay (x10 usec)"); 2443 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 2444 CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 2445 "TX IM, # segments per TX interrupt"); 2446 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 2447 CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 2448 2449 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 2450 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ET statistics"); 2451 parent = SYSCTL_CHILDREN(tree); 2452 2453 /* TX/RX statistics. */ 2454 stats = &sc->sc_stats; 2455 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_64", &stats->pkts_64, 2456 "0 to 64 bytes frames"); 2457 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_65_127", &stats->pkts_65, 2458 "65 to 127 bytes frames"); 2459 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_128_255", &stats->pkts_128, 2460 "128 to 255 bytes frames"); 2461 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_256_511", &stats->pkts_256, 2462 "256 to 511 bytes frames"); 2463 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_512_1023", &stats->pkts_512, 2464 "512 to 1023 bytes frames"); 2465 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1024_1518", &stats->pkts_1024, 2466 "1024 to 1518 bytes frames"); 2467 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1519_1522", &stats->pkts_1519, 2468 "1519 to 1522 bytes frames"); 2469 2470 /* RX statistics. */ 2471 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2472 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics"); 2473 children = SYSCTL_CHILDREN(tree); 2474 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2475 &stats->rx_bytes, "Good bytes"); 2476 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2477 &stats->rx_frames, "Good frames"); 2478 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2479 &stats->rx_crcerrs, "CRC errors"); 2480 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2481 &stats->rx_mcast, "Multicast frames"); 2482 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2483 &stats->rx_bcast, "Broadcast frames"); 2484 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2485 &stats->rx_control, "Control frames"); 2486 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2487 &stats->rx_pause, "Pause frames"); 2488 ET_SYSCTL_STAT_ADD32(ctx, children, "unknown_control", 2489 &stats->rx_unknown_control, "Unknown control frames"); 2490 ET_SYSCTL_STAT_ADD32(ctx, children, "align_errs", 2491 &stats->rx_alignerrs, "Alignment errors"); 2492 ET_SYSCTL_STAT_ADD32(ctx, children, "len_errs", 2493 &stats->rx_lenerrs, "Frames with length mismatched"); 2494 ET_SYSCTL_STAT_ADD32(ctx, children, "code_errs", 2495 &stats->rx_codeerrs, "Frames with code error"); 2496 ET_SYSCTL_STAT_ADD32(ctx, children, "cs_errs", 2497 &stats->rx_cserrs, "Frames with carrier sense error"); 2498 ET_SYSCTL_STAT_ADD32(ctx, children, "runts", 2499 &stats->rx_runts, "Too short frames"); 2500 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2501 &stats->rx_oversize, "Oversized frames"); 2502 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2503 &stats->rx_fragments, "Fragmented frames"); 2504 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2505 &stats->rx_jabbers, "Frames with jabber error"); 2506 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2507 &stats->rx_drop, "Dropped frames"); 2508 2509 /* TX statistics. */ 2510 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2511 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics"); 2512 children = SYSCTL_CHILDREN(tree); 2513 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2514 &stats->tx_bytes, "Good bytes"); 2515 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2516 &stats->tx_frames, "Good frames"); 2517 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2518 &stats->tx_mcast, "Multicast frames"); 2519 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2520 &stats->tx_bcast, "Broadcast frames"); 2521 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2522 &stats->tx_pause, "Pause frames"); 2523 ET_SYSCTL_STAT_ADD32(ctx, children, "deferred", 2524 &stats->tx_deferred, "Deferred frames"); 2525 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_deferred", 2526 &stats->tx_excess_deferred, "Excessively deferred frames"); 2527 ET_SYSCTL_STAT_ADD32(ctx, children, "single_colls", 2528 &stats->tx_single_colls, "Single collisions"); 2529 ET_SYSCTL_STAT_ADD32(ctx, children, "multi_colls", 2530 &stats->tx_multi_colls, "Multiple collisions"); 2531 ET_SYSCTL_STAT_ADD32(ctx, children, "late_colls", 2532 &stats->tx_late_colls, "Late collisions"); 2533 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_colls", 2534 &stats->tx_excess_colls, "Excess collisions"); 2535 ET_SYSCTL_STAT_ADD32(ctx, children, "total_colls", 2536 &stats->tx_total_colls, "Total collisions"); 2537 ET_SYSCTL_STAT_ADD32(ctx, children, "pause_honored", 2538 &stats->tx_pause_honored, "Honored pause frames"); 2539 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2540 &stats->tx_drop, "Dropped frames"); 2541 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2542 &stats->tx_jabbers, "Frames with jabber errors"); 2543 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2544 &stats->tx_crcerrs, "Frames with CRC errors"); 2545 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2546 &stats->tx_control, "Control frames"); 2547 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2548 &stats->tx_oversize, "Oversized frames"); 2549 ET_SYSCTL_STAT_ADD32(ctx, children, "undersize", 2550 &stats->tx_undersize, "Undersized frames"); 2551 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2552 &stats->tx_fragments, "Fragmented frames"); 2553 } 2554 2555 #undef ET_SYSCTL_STAT_ADD32 2556 #undef ET_SYSCTL_STAT_ADD64 2557 2558 static int 2559 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2560 { 2561 struct et_softc *sc; 2562 if_t ifp; 2563 int error, v; 2564 2565 sc = arg1; 2566 ifp = sc->ifp; 2567 v = sc->sc_rx_intr_npkts; 2568 error = sysctl_handle_int(oidp, &v, 0, req); 2569 if (error || req->newptr == NULL) 2570 goto back; 2571 if (v <= 0) { 2572 error = EINVAL; 2573 goto back; 2574 } 2575 2576 if (sc->sc_rx_intr_npkts != v) { 2577 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2578 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2579 sc->sc_rx_intr_npkts = v; 2580 } 2581 back: 2582 return (error); 2583 } 2584 2585 static int 2586 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2587 { 2588 struct et_softc *sc; 2589 if_t ifp; 2590 int error, v; 2591 2592 sc = arg1; 2593 ifp = sc->ifp; 2594 v = sc->sc_rx_intr_delay; 2595 error = sysctl_handle_int(oidp, &v, 0, req); 2596 if (error || req->newptr == NULL) 2597 goto back; 2598 if (v <= 0) { 2599 error = EINVAL; 2600 goto back; 2601 } 2602 2603 if (sc->sc_rx_intr_delay != v) { 2604 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2605 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2606 sc->sc_rx_intr_delay = v; 2607 } 2608 back: 2609 return (error); 2610 } 2611 2612 static void 2613 et_stats_update(struct et_softc *sc) 2614 { 2615 struct et_hw_stats *stats; 2616 2617 stats = &sc->sc_stats; 2618 stats->pkts_64 += CSR_READ_4(sc, ET_STAT_PKTS_64); 2619 stats->pkts_65 += CSR_READ_4(sc, ET_STAT_PKTS_65_127); 2620 stats->pkts_128 += CSR_READ_4(sc, ET_STAT_PKTS_128_255); 2621 stats->pkts_256 += CSR_READ_4(sc, ET_STAT_PKTS_256_511); 2622 stats->pkts_512 += CSR_READ_4(sc, ET_STAT_PKTS_512_1023); 2623 stats->pkts_1024 += CSR_READ_4(sc, ET_STAT_PKTS_1024_1518); 2624 stats->pkts_1519 += CSR_READ_4(sc, ET_STAT_PKTS_1519_1522); 2625 2626 stats->rx_bytes += CSR_READ_4(sc, ET_STAT_RX_BYTES); 2627 stats->rx_frames += CSR_READ_4(sc, ET_STAT_RX_FRAMES); 2628 stats->rx_crcerrs += CSR_READ_4(sc, ET_STAT_RX_CRC_ERR); 2629 stats->rx_mcast += CSR_READ_4(sc, ET_STAT_RX_MCAST); 2630 stats->rx_bcast += CSR_READ_4(sc, ET_STAT_RX_BCAST); 2631 stats->rx_control += CSR_READ_4(sc, ET_STAT_RX_CTL); 2632 stats->rx_pause += CSR_READ_4(sc, ET_STAT_RX_PAUSE); 2633 stats->rx_unknown_control += CSR_READ_4(sc, ET_STAT_RX_UNKNOWN_CTL); 2634 stats->rx_alignerrs += CSR_READ_4(sc, ET_STAT_RX_ALIGN_ERR); 2635 stats->rx_lenerrs += CSR_READ_4(sc, ET_STAT_RX_LEN_ERR); 2636 stats->rx_codeerrs += CSR_READ_4(sc, ET_STAT_RX_CODE_ERR); 2637 stats->rx_cserrs += CSR_READ_4(sc, ET_STAT_RX_CS_ERR); 2638 stats->rx_runts += CSR_READ_4(sc, ET_STAT_RX_RUNT); 2639 stats->rx_oversize += CSR_READ_4(sc, ET_STAT_RX_OVERSIZE); 2640 stats->rx_fragments += CSR_READ_4(sc, ET_STAT_RX_FRAG); 2641 stats->rx_jabbers += CSR_READ_4(sc, ET_STAT_RX_JABBER); 2642 stats->rx_drop += CSR_READ_4(sc, ET_STAT_RX_DROP); 2643 2644 stats->tx_bytes += CSR_READ_4(sc, ET_STAT_TX_BYTES); 2645 stats->tx_frames += CSR_READ_4(sc, ET_STAT_TX_FRAMES); 2646 stats->tx_mcast += CSR_READ_4(sc, ET_STAT_TX_MCAST); 2647 stats->tx_bcast += CSR_READ_4(sc, ET_STAT_TX_BCAST); 2648 stats->tx_pause += CSR_READ_4(sc, ET_STAT_TX_PAUSE); 2649 stats->tx_deferred += CSR_READ_4(sc, ET_STAT_TX_DEFER); 2650 stats->tx_excess_deferred += CSR_READ_4(sc, ET_STAT_TX_EXCESS_DEFER); 2651 stats->tx_single_colls += CSR_READ_4(sc, ET_STAT_TX_SINGLE_COL); 2652 stats->tx_multi_colls += CSR_READ_4(sc, ET_STAT_TX_MULTI_COL); 2653 stats->tx_late_colls += CSR_READ_4(sc, ET_STAT_TX_LATE_COL); 2654 stats->tx_excess_colls += CSR_READ_4(sc, ET_STAT_TX_EXCESS_COL); 2655 stats->tx_total_colls += CSR_READ_4(sc, ET_STAT_TX_TOTAL_COL); 2656 stats->tx_pause_honored += CSR_READ_4(sc, ET_STAT_TX_PAUSE_HONOR); 2657 stats->tx_drop += CSR_READ_4(sc, ET_STAT_TX_DROP); 2658 stats->tx_jabbers += CSR_READ_4(sc, ET_STAT_TX_JABBER); 2659 stats->tx_crcerrs += CSR_READ_4(sc, ET_STAT_TX_CRC_ERR); 2660 stats->tx_control += CSR_READ_4(sc, ET_STAT_TX_CTL); 2661 stats->tx_oversize += CSR_READ_4(sc, ET_STAT_TX_OVERSIZE); 2662 stats->tx_undersize += CSR_READ_4(sc, ET_STAT_TX_UNDERSIZE); 2663 stats->tx_fragments += CSR_READ_4(sc, ET_STAT_TX_FRAG); 2664 } 2665 2666 static uint64_t 2667 et_get_counter(if_t ifp, ift_counter cnt) 2668 { 2669 struct et_softc *sc; 2670 struct et_hw_stats *stats; 2671 2672 sc = if_getsoftc(ifp); 2673 stats = &sc->sc_stats; 2674 2675 switch (cnt) { 2676 case IFCOUNTER_OPACKETS: 2677 return (stats->tx_frames); 2678 case IFCOUNTER_COLLISIONS: 2679 return (stats->tx_total_colls); 2680 case IFCOUNTER_OERRORS: 2681 return (stats->tx_drop + stats->tx_jabbers + 2682 stats->tx_crcerrs + stats->tx_excess_deferred + 2683 stats->tx_late_colls); 2684 case IFCOUNTER_IPACKETS: 2685 return (stats->rx_frames); 2686 case IFCOUNTER_IERRORS: 2687 return (stats->rx_crcerrs + stats->rx_alignerrs + 2688 stats->rx_lenerrs + stats->rx_codeerrs + stats->rx_cserrs + 2689 stats->rx_runts + stats->rx_jabbers + stats->rx_drop); 2690 default: 2691 return (if_get_counter_default(ifp, cnt)); 2692 } 2693 } 2694 2695 static int 2696 et_suspend(device_t dev) 2697 { 2698 struct et_softc *sc; 2699 uint32_t pmcfg; 2700 2701 sc = device_get_softc(dev); 2702 ET_LOCK(sc); 2703 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) != 0) 2704 et_stop(sc); 2705 /* Diable all clocks and put PHY into COMA. */ 2706 pmcfg = CSR_READ_4(sc, ET_PM); 2707 pmcfg &= ~(EM_PM_GIGEPHY_ENB | ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | 2708 ET_PM_RXCLK_GATE); 2709 pmcfg |= ET_PM_PHY_SW_COMA; 2710 CSR_WRITE_4(sc, ET_PM, pmcfg); 2711 ET_UNLOCK(sc); 2712 return (0); 2713 } 2714 2715 static int 2716 et_resume(device_t dev) 2717 { 2718 struct et_softc *sc; 2719 uint32_t pmcfg; 2720 2721 sc = device_get_softc(dev); 2722 ET_LOCK(sc); 2723 /* Take PHY out of COMA and enable clocks. */ 2724 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 2725 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 2726 pmcfg |= EM_PM_GIGEPHY_ENB; 2727 CSR_WRITE_4(sc, ET_PM, pmcfg); 2728 if ((if_getflags(sc->ifp) & IFF_UP) != 0) 2729 et_init_locked(sc); 2730 ET_UNLOCK(sc); 2731 return (0); 2732 } 2733