1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <[email protected]> 5 * Copyright (c) 2009 Norikatsu Shigemura <[email protected]> 6 * Copyright (c) 2009-2012 Jung-uk Kim <[email protected]> 7 * All rights reserved. 8 * Copyright (c) 2017-2020 Conrad Meyer <[email protected]>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the AMD CPU on-die thermal sensors. 34 * Initially based on the k8temp Linux driver. 35 */ 36 37 #include <sys/cdefs.h> 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/sysctl.h> 46 #include <sys/systm.h> 47 48 #include <machine/cpufunc.h> 49 #include <machine/md_var.h> 50 #include <machine/specialreg.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <x86/pci_cfgreg.h> 54 55 #include <dev/amdsmn/amdsmn.h> 56 57 typedef enum { 58 CORE0_SENSOR0, 59 CORE0_SENSOR1, 60 CORE1_SENSOR0, 61 CORE1_SENSOR1, 62 CORE0, 63 CORE1, 64 CCD1, 65 CCD_BASE = CCD1, 66 CCD2, 67 CCD3, 68 CCD4, 69 CCD5, 70 CCD6, 71 CCD7, 72 CCD8, 73 CCD9, 74 CCD10, 75 CCD11, 76 CCD12, 77 CCD_MAX = CCD12, 78 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 79 } amdsensor_t; 80 81 struct amdtemp_softc { 82 int sc_ncores; 83 int sc_ntemps; 84 int sc_flags; 85 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 86 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 87 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 88 int32_t sc_offset; 89 int32_t sc_temp_base; 90 int32_t (*sc_gettemp)(device_t, amdsensor_t); 91 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 92 struct intr_config_hook sc_ich; 93 device_t sc_smn; 94 struct mtx sc_lock; 95 }; 96 97 /* 98 * N.B. The numbers in macro names below are significant and represent CPU 99 * family and model numbers. Do not make up fictitious family or model numbers 100 * when adding support for new devices. 101 */ 102 #define VENDORID_AMD 0x1022 103 #define DEVICEID_AMD_MISC0F 0x1103 104 #define DEVICEID_AMD_MISC10 0x1203 105 #define DEVICEID_AMD_MISC11 0x1303 106 #define DEVICEID_AMD_MISC14 0x1703 107 #define DEVICEID_AMD_MISC15 0x1603 108 #define DEVICEID_AMD_MISC15_M10H 0x1403 109 #define DEVICEID_AMD_MISC15_M30H 0x141d 110 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 111 #define DEVICEID_AMD_MISC16 0x1533 112 #define DEVICEID_AMD_MISC16_M30H 0x1583 113 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 114 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 115 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */ 116 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630 117 #define DEVICEID_AMD_HOSTB19H_M10H_ROOT 0x14a4 118 #define DEVICEID_AMD_HOSTB19H_M60H_ROOT 0x14d8 119 120 static const struct amdtemp_product { 121 uint16_t amdtemp_vendorid; 122 uint16_t amdtemp_deviceid; 123 /* 124 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 125 * drivers do not attach to that device. 126 */ 127 bool amdtemp_has_cpuid; 128 } amdtemp_products[] = { 129 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 130 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 131 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 132 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 133 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 134 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 135 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 136 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 137 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 138 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 139 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 140 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 141 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 142 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false }, 143 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M10H_ROOT, false }, 144 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M60H_ROOT, false }, 145 }; 146 147 /* 148 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 149 */ 150 #define AMDTEMP_REPTMP_CTRL 0xa4 151 152 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 153 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 154 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 155 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 156 157 /* 158 * Reported Temperature, Family 15h, M60+ 159 * 160 * Same register bit definitions as other Family 15h CPUs, but access is 161 * indirect via SMN, like Family 17h. 162 */ 163 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 164 165 /* 166 * Reported Temperature, Family 17h 167 * 168 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 169 * provide the current temp. bit 19, when clear, means the temp is reported in 170 * a range 0.."225C" (probable typo for 255C), and when set changes the range 171 * to -49..206C. 172 */ 173 #define AMDTEMP_17H_CUR_TMP 0x59800 174 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 175 /* 176 * Bits 16-17, when set, mean that CUR_TMP is read-write. When it is, the 177 * 49 degree offset should apply as well. This was revealed in a Linux 178 * patch from an AMD employee. 179 */ 180 #define AMDTEMP_17H_CUR_TMP_TJ_SEL ((1u << 17) | (1u << 16)) 181 /* 182 * The following register set was discovered experimentally by Ondrej Čerman 183 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 184 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 185 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 186 */ 187 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 188 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 189 190 #define AMDTEMP_ZEN4_10H_CCD_TMP_BASE 0x59b00 191 #define AMDTEMP_ZEN4_CCD_TMP_BASE 0x59b08 192 193 /* 194 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 195 */ 196 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 197 198 /* 199 * Thermaltrip Status Register (Family 0Fh only) 200 */ 201 #define AMDTEMP_THERMTP_STAT 0xe4 202 #define AMDTEMP_TTSR_SELCORE 0x04 203 #define AMDTEMP_TTSR_SELSENSOR 0x40 204 205 /* 206 * DRAM Configuration High Register 207 */ 208 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 209 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 210 211 /* 212 * CPU Family/Model Register 213 */ 214 #define AMDTEMP_CPUID 0xfc 215 216 /* 217 * Device methods. 218 */ 219 static void amdtemp_identify(driver_t *driver, device_t parent); 220 static int amdtemp_probe(device_t dev); 221 static int amdtemp_attach(device_t dev); 222 static void amdtemp_intrhook(void *arg); 223 static int amdtemp_detach(device_t dev); 224 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 225 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 226 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 227 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 228 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 229 static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model); 230 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 231 232 static device_method_t amdtemp_methods[] = { 233 /* Device interface */ 234 DEVMETHOD(device_identify, amdtemp_identify), 235 DEVMETHOD(device_probe, amdtemp_probe), 236 DEVMETHOD(device_attach, amdtemp_attach), 237 DEVMETHOD(device_detach, amdtemp_detach), 238 239 DEVMETHOD_END 240 }; 241 242 static driver_t amdtemp_driver = { 243 "amdtemp", 244 amdtemp_methods, 245 sizeof(struct amdtemp_softc), 246 }; 247 248 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, NULL, NULL); 249 MODULE_VERSION(amdtemp, 1); 250 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 251 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 252 nitems(amdtemp_products)); 253 254 static bool 255 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 256 { 257 int i; 258 uint16_t vendor, devid; 259 260 vendor = pci_get_vendor(dev); 261 devid = pci_get_device(dev); 262 263 for (i = 0; i < nitems(amdtemp_products); i++) { 264 if (vendor == amdtemp_products[i].amdtemp_vendorid && 265 devid == amdtemp_products[i].amdtemp_deviceid) { 266 if (product_out != NULL) 267 *product_out = &amdtemp_products[i]; 268 return (true); 269 } 270 } 271 return (false); 272 } 273 274 static void 275 amdtemp_identify(driver_t *driver, device_t parent) 276 { 277 device_t child; 278 279 /* Make sure we're not being doubly invoked. */ 280 if (device_find_child(parent, "amdtemp", -1) != NULL) 281 return; 282 283 if (amdtemp_match(parent, NULL)) { 284 child = device_add_child(parent, "amdtemp", -1); 285 if (child == NULL) 286 device_printf(parent, "add amdtemp child failed\n"); 287 } 288 } 289 290 static int 291 amdtemp_probe(device_t dev) 292 { 293 uint32_t family, model; 294 295 if (resource_disabled("amdtemp", 0)) 296 return (ENXIO); 297 if (!amdtemp_match(device_get_parent(dev), NULL)) 298 return (ENXIO); 299 300 family = CPUID_TO_FAMILY(cpu_id); 301 model = CPUID_TO_MODEL(cpu_id); 302 303 switch (family) { 304 case 0x0f: 305 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 306 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 307 return (ENXIO); 308 break; 309 case 0x10: 310 case 0x11: 311 case 0x12: 312 case 0x14: 313 case 0x15: 314 case 0x16: 315 case 0x17: 316 case 0x19: 317 break; 318 default: 319 return (ENXIO); 320 } 321 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 322 323 return (BUS_PROBE_GENERIC); 324 } 325 326 static int 327 amdtemp_attach(device_t dev) 328 { 329 char tn[32]; 330 u_int regs[4]; 331 const struct amdtemp_product *product; 332 struct amdtemp_softc *sc; 333 struct sysctl_ctx_list *sysctlctx; 334 struct sysctl_oid *sysctlnode; 335 uint32_t cpuid, family, model; 336 u_int bid; 337 int erratum319, unit; 338 bool needsmn; 339 340 sc = device_get_softc(dev); 341 erratum319 = 0; 342 needsmn = false; 343 344 if (!amdtemp_match(device_get_parent(dev), &product)) 345 return (ENXIO); 346 347 cpuid = cpu_id; 348 family = CPUID_TO_FAMILY(cpuid); 349 model = CPUID_TO_MODEL(cpuid); 350 351 /* 352 * This checks for the byzantine condition of running a heterogenous 353 * revision multi-socket system where the attach thread is potentially 354 * probing a remote socket's PCI device. 355 * 356 * Currently, such scenarios are unsupported on models using the SMN 357 * (because on those models, amdtemp(4) attaches to a different PCI 358 * device than the one that contains AMDTEMP_CPUID). 359 * 360 * The ancient 0x0F family of devices only supports this register from 361 * models 40h+. 362 */ 363 if (product->amdtemp_has_cpuid && (family > 0x0f || 364 (family == 0x0f && model >= 0x40))) { 365 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 366 4); 367 family = CPUID_TO_FAMILY(cpuid); 368 model = CPUID_TO_MODEL(cpuid); 369 } 370 371 switch (family) { 372 case 0x0f: 373 /* 374 * Thermaltrip Status Register 375 * 376 * - ThermSenseCoreSel 377 * 378 * Revision F & G: 0 - Core1, 1 - Core0 379 * Other: 0 - Core0, 1 - Core1 380 * 381 * - CurTmp 382 * 383 * Revision G: bits 23-14 384 * Other: bits 23-16 385 * 386 * XXX According to the BKDG, CurTmp, ThermSenseSel and 387 * ThermSenseCoreSel bits were introduced in Revision F 388 * but CurTmp seems working fine as early as Revision C. 389 * However, it is not clear whether ThermSenseSel and/or 390 * ThermSenseCoreSel work in undocumented cases as well. 391 * In fact, the Linux driver suggests it may not work but 392 * we just assume it does until we find otherwise. 393 * 394 * XXX According to Linux, CurTmp starts at -28C on 395 * Socket AM2 Revision G processors, which is not 396 * documented anywhere. 397 */ 398 if (model >= 0x40) 399 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 400 if (model >= 0x60 && model != 0xc1) { 401 do_cpuid(0x80000001, regs); 402 bid = (regs[1] >> 9) & 0x1f; 403 switch (model) { 404 case 0x68: /* Socket S1g1 */ 405 case 0x6c: 406 case 0x7c: 407 break; 408 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 409 if (bid != 0x0b && bid != 0x0c) 410 sc->sc_flags |= 411 AMDTEMP_FLAG_ALT_OFFSET; 412 break; 413 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 414 case 0x7f: 415 if (bid != 0x07 && bid != 0x09 && 416 bid != 0x0c) 417 sc->sc_flags |= 418 AMDTEMP_FLAG_ALT_OFFSET; 419 break; 420 default: 421 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 422 } 423 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 424 } 425 426 /* 427 * There are two sensors per core. 428 */ 429 sc->sc_ntemps = 2; 430 431 sc->sc_gettemp = amdtemp_gettemp0f; 432 break; 433 case 0x10: 434 /* 435 * Erratum 319 Inaccurate Temperature Measurement 436 * 437 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 438 */ 439 do_cpuid(0x80000001, regs); 440 switch ((regs[1] >> 28) & 0xf) { 441 case 0: /* Socket F */ 442 erratum319 = 1; 443 break; 444 case 1: /* Socket AM2+ or AM3 */ 445 if ((pci_cfgregread(pci_get_domain(dev), 446 pci_get_bus(dev), pci_get_slot(dev), 2, 447 AMDTEMP_DRAM_CONF_HIGH, 2) & 448 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 449 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 450 break; 451 /* XXX 00100F42h (RB-C2) exists in both formats. */ 452 erratum319 = 1; 453 break; 454 } 455 /* FALLTHROUGH */ 456 case 0x11: 457 case 0x12: 458 case 0x14: 459 case 0x15: 460 case 0x16: 461 sc->sc_ntemps = 1; 462 /* 463 * Some later (60h+) models of family 15h use a similar SMN 464 * network as family 17h. (However, the register index differs 465 * from 17h and the decoding matches other 10h-15h models, 466 * which differ from 17h.) 467 */ 468 if (family == 0x15 && model >= 0x60) { 469 sc->sc_gettemp = amdtemp_gettemp15hm60h; 470 needsmn = true; 471 } else 472 sc->sc_gettemp = amdtemp_gettemp; 473 break; 474 case 0x17: 475 case 0x19: 476 sc->sc_ntemps = 1; 477 sc->sc_gettemp = amdtemp_gettemp17h; 478 needsmn = true; 479 break; 480 default: 481 device_printf(dev, "Bogus family 0x%x\n", family); 482 return (ENXIO); 483 } 484 485 if (needsmn) { 486 sc->sc_smn = device_find_child( 487 device_get_parent(dev), "amdsmn", -1); 488 if (sc->sc_smn == NULL) { 489 if (bootverbose) 490 device_printf(dev, "No SMN device found\n"); 491 return (ENXIO); 492 } 493 } 494 495 /* Find number of cores per package. */ 496 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 497 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 498 if (sc->sc_ncores > MAXCPU) 499 return (ENXIO); 500 501 mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF); 502 if (erratum319) 503 device_printf(dev, 504 "Erratum 319: temperature measurement may be inaccurate\n"); 505 if (bootverbose) 506 device_printf(dev, "Found %d cores and %d sensors.\n", 507 sc->sc_ncores, 508 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 509 510 /* 511 * dev.amdtemp.N tree. 512 */ 513 unit = device_get_unit(dev); 514 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 515 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 516 517 sysctlctx = device_get_sysctl_ctx(dev); 518 SYSCTL_ADD_INT(sysctlctx, 519 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 520 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 521 "Temperature sensor offset"); 522 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 523 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 524 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0"); 525 526 SYSCTL_ADD_PROC(sysctlctx, 527 SYSCTL_CHILDREN(sysctlnode), 528 OID_AUTO, "sensor0", 529 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 530 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 531 "Core 0 / Sensor 0 temperature"); 532 533 sc->sc_temp_base = AMDTEMP_17H_CCD_TMP_BASE; 534 535 if (family == 0x17) 536 amdtemp_probe_ccd_sensors17h(dev, model); 537 else if (family == 0x19) 538 amdtemp_probe_ccd_sensors19h(dev, model); 539 else if (sc->sc_ntemps > 1) { 540 SYSCTL_ADD_PROC(sysctlctx, 541 SYSCTL_CHILDREN(sysctlnode), 542 OID_AUTO, "sensor1", 543 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 544 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 545 "Core 0 / Sensor 1 temperature"); 546 547 if (sc->sc_ncores > 1) { 548 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 549 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 550 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE, 551 0, "Core 1"); 552 553 SYSCTL_ADD_PROC(sysctlctx, 554 SYSCTL_CHILDREN(sysctlnode), 555 OID_AUTO, "sensor0", 556 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 557 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 558 "Core 1 / Sensor 0 temperature"); 559 560 SYSCTL_ADD_PROC(sysctlctx, 561 SYSCTL_CHILDREN(sysctlnode), 562 OID_AUTO, "sensor1", 563 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 564 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 565 "Core 1 / Sensor 1 temperature"); 566 } 567 } 568 569 /* 570 * Try to create dev.cpu sysctl entries and setup intrhook function. 571 * This is needed because the cpu driver may be loaded late on boot, 572 * after us. 573 */ 574 amdtemp_intrhook(dev); 575 sc->sc_ich.ich_func = amdtemp_intrhook; 576 sc->sc_ich.ich_arg = dev; 577 if (config_intrhook_establish(&sc->sc_ich) != 0) { 578 device_printf(dev, "config_intrhook_establish failed!\n"); 579 return (ENXIO); 580 } 581 582 return (0); 583 } 584 585 void 586 amdtemp_intrhook(void *arg) 587 { 588 struct amdtemp_softc *sc; 589 struct sysctl_ctx_list *sysctlctx; 590 device_t dev = (device_t)arg; 591 device_t acpi, cpu, nexus; 592 amdsensor_t sensor; 593 int i; 594 595 sc = device_get_softc(dev); 596 597 /* 598 * dev.cpu.N.temperature. 599 */ 600 nexus = device_find_child(root_bus, "nexus", 0); 601 acpi = device_find_child(nexus, "acpi", 0); 602 603 for (i = 0; i < sc->sc_ncores; i++) { 604 if (sc->sc_sysctl_cpu[i] != NULL) 605 continue; 606 cpu = device_find_child(acpi, "cpu", 607 device_get_unit(dev) * sc->sc_ncores + i); 608 if (cpu != NULL) { 609 sysctlctx = device_get_sysctl_ctx(cpu); 610 611 sensor = sc->sc_ntemps > 1 ? 612 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 613 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 614 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 615 OID_AUTO, "temperature", 616 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 617 dev, sensor, amdtemp_sysctl, "IK", 618 "Current temparature"); 619 } 620 } 621 if (sc->sc_ich.ich_arg != NULL) 622 config_intrhook_disestablish(&sc->sc_ich); 623 } 624 625 int 626 amdtemp_detach(device_t dev) 627 { 628 struct amdtemp_softc *sc = device_get_softc(dev); 629 int i; 630 631 for (i = 0; i < sc->sc_ncores; i++) 632 if (sc->sc_sysctl_cpu[i] != NULL) 633 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 634 635 /* NewBus removes the dev.amdtemp.N tree by itself. */ 636 637 mtx_destroy(&sc->sc_lock); 638 return (0); 639 } 640 641 static int 642 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 643 { 644 device_t dev = (device_t)arg1; 645 struct amdtemp_softc *sc = device_get_softc(dev); 646 amdsensor_t sensor = (amdsensor_t)arg2; 647 int32_t auxtemp[2], temp; 648 int error; 649 650 switch (sensor) { 651 case CORE0: 652 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 653 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 654 temp = imax(auxtemp[0], auxtemp[1]); 655 break; 656 case CORE1: 657 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 658 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 659 temp = imax(auxtemp[0], auxtemp[1]); 660 break; 661 default: 662 temp = sc->sc_gettemp(dev, sensor); 663 break; 664 } 665 error = sysctl_handle_int(oidp, &temp, 0, req); 666 667 return (error); 668 } 669 670 #define AMDTEMP_ZERO_C_TO_K 2731 671 672 static int32_t 673 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 674 { 675 struct amdtemp_softc *sc = device_get_softc(dev); 676 uint32_t mask, offset, temp; 677 678 mtx_lock(&sc->sc_lock); 679 680 /* Set Sensor/Core selector. */ 681 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 682 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 683 switch (sensor) { 684 case CORE0_SENSOR1: 685 temp |= AMDTEMP_TTSR_SELSENSOR; 686 /* FALLTHROUGH */ 687 case CORE0_SENSOR0: 688 case CORE0: 689 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 690 temp |= AMDTEMP_TTSR_SELCORE; 691 break; 692 case CORE1_SENSOR1: 693 temp |= AMDTEMP_TTSR_SELSENSOR; 694 /* FALLTHROUGH */ 695 case CORE1_SENSOR0: 696 case CORE1: 697 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 698 temp |= AMDTEMP_TTSR_SELCORE; 699 break; 700 default: 701 __assert_unreachable(); 702 } 703 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 704 705 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 706 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 707 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 708 temp = ((temp >> 14) & mask) * 5 / 2; 709 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 710 711 mtx_unlock(&sc->sc_lock); 712 return (temp); 713 } 714 715 static uint32_t 716 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 717 { 718 uint32_t temp; 719 720 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 721 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 722 723 if (minus49) 724 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 725 726 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 727 return (temp); 728 } 729 730 static uint32_t 731 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 732 { 733 bool minus49; 734 735 /* 736 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 737 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 738 * documented in BKDGs prior to family 15h model 00h.) 739 */ 740 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 741 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 742 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 743 744 return (amdtemp_decode_fam10h_to_17h(sc_offset, 745 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 746 } 747 748 static uint32_t 749 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 750 { 751 bool minus49; 752 753 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0) 754 || ((val & AMDTEMP_17H_CUR_TMP_TJ_SEL) == AMDTEMP_17H_CUR_TMP_TJ_SEL); 755 return (amdtemp_decode_fam10h_to_17h(sc_offset, 756 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 757 } 758 759 static int32_t 760 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 761 { 762 struct amdtemp_softc *sc = device_get_softc(dev); 763 uint32_t temp; 764 765 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 766 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 767 } 768 769 static int32_t 770 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 771 { 772 struct amdtemp_softc *sc = device_get_softc(dev); 773 uint32_t val; 774 int error __diagused; 775 776 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 777 KASSERT(error == 0, ("amdsmn_read")); 778 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 779 } 780 781 static int32_t 782 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 783 { 784 struct amdtemp_softc *sc = device_get_softc(dev); 785 uint32_t val; 786 int error __diagused; 787 788 switch (sensor) { 789 case CORE0_SENSOR0: 790 /* Tctl */ 791 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 792 KASSERT(error == 0, ("amdsmn_read")); 793 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 794 case CCD_BASE ... CCD_MAX: 795 /* Tccd<N> */ 796 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + 797 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 798 KASSERT(error == 0, ("amdsmn_read2")); 799 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 800 ("sensor %d: not valid", (int)sensor)); 801 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 802 default: 803 __assert_unreachable(); 804 } 805 } 806 807 static void 808 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg) 809 { 810 char sensor_name[16], sensor_descr[32]; 811 struct amdtemp_softc *sc; 812 uint32_t i, val; 813 int error; 814 815 sc = device_get_softc(dev); 816 for (i = 0; i < maxreg; i++) { 817 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + 818 (i * sizeof(val)), &val); 819 if (error != 0) 820 continue; 821 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 822 continue; 823 824 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 825 snprintf(sensor_descr, sizeof(sensor_descr), 826 "CCD %u temperature (Tccd%u)", i, i); 827 828 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 829 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 830 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 831 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 832 } 833 } 834 835 static void 836 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 837 { 838 uint32_t maxreg; 839 840 switch (model) { 841 case 0x00 ... 0x2f: /* Zen1, Zen+ */ 842 maxreg = 4; 843 break; 844 case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */ 845 case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */ 846 case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */ 847 maxreg = 8; 848 _Static_assert((int)NUM_CCDS >= 8, ""); 849 break; 850 default: 851 device_printf(dev, 852 "Unrecognized Family 17h Model: %02xh\n", model); 853 return; 854 } 855 856 amdtemp_probe_ccd_sensors(dev, maxreg); 857 } 858 859 static void 860 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model) 861 { 862 struct amdtemp_softc *sc = device_get_softc(dev); 863 uint32_t maxreg; 864 865 switch (model) { 866 case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */ 867 case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */ 868 maxreg = 8; 869 _Static_assert((int)NUM_CCDS >= 8, ""); 870 break; 871 case 0x10 ... 0x1f: 872 sc->sc_temp_base = AMDTEMP_ZEN4_10H_CCD_TMP_BASE; 873 maxreg = 12; 874 _Static_assert((int)NUM_CCDS >= 12, ""); 875 break; 876 case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */ 877 sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE; 878 maxreg = 8; 879 _Static_assert((int)NUM_CCDS >= 8, ""); 880 break; 881 default: 882 device_printf(dev, 883 "Unrecognized Family 19h Model: %02xh\n", model); 884 return; 885 } 886 887 amdtemp_probe_ccd_sensors(dev, maxreg); 888 } 889