1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <[email protected]> 5 * Copyright (c) 2009 Norikatsu Shigemura <[email protected]> 6 * Copyright (c) 2009-2012 Jung-uk Kim <[email protected]> 7 * All rights reserved. 8 * Copyright (c) 2017-2020 Conrad Meyer <[email protected]>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the AMD CPU on-die thermal sensors. 34 * Initially based on the k8temp Linux driver. 35 */ 36 37 #include <sys/cdefs.h> 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/sysctl.h> 46 #include <sys/systm.h> 47 48 #include <machine/cpufunc.h> 49 #include <machine/md_var.h> 50 #include <machine/specialreg.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <x86/pci_cfgreg.h> 54 55 #include <dev/amdsmn/amdsmn.h> 56 57 typedef enum { 58 CORE0_SENSOR0, 59 CORE0_SENSOR1, 60 CORE1_SENSOR0, 61 CORE1_SENSOR1, 62 CORE0, 63 CORE1, 64 CCD1, 65 CCD_BASE = CCD1, 66 CCD2, 67 CCD3, 68 CCD4, 69 CCD5, 70 CCD6, 71 CCD7, 72 CCD8, 73 CCD9, 74 CCD10, 75 CCD11, 76 CCD12, 77 CCD_MAX = CCD12, 78 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 79 } amdsensor_t; 80 81 struct amdtemp_softc { 82 int sc_ncores; 83 int sc_ntemps; 84 int sc_flags; 85 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 86 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 87 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 88 int32_t sc_offset; 89 int32_t sc_temp_base; 90 int32_t (*sc_gettemp)(device_t, amdsensor_t); 91 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 92 struct intr_config_hook sc_ich; 93 device_t sc_smn; 94 struct mtx sc_lock; 95 }; 96 97 /* 98 * N.B. The numbers in macro names below are significant and represent CPU 99 * family and model numbers. Do not make up fictitious family or model numbers 100 * when adding support for new devices. 101 */ 102 #define VENDORID_AMD 0x1022 103 #define DEVICEID_AMD_MISC0F 0x1103 104 #define DEVICEID_AMD_MISC10 0x1203 105 #define DEVICEID_AMD_MISC11 0x1303 106 #define DEVICEID_AMD_MISC14 0x1703 107 #define DEVICEID_AMD_MISC15 0x1603 108 #define DEVICEID_AMD_MISC15_M10H 0x1403 109 #define DEVICEID_AMD_MISC15_M30H 0x141d 110 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 111 #define DEVICEID_AMD_MISC16 0x1533 112 #define DEVICEID_AMD_MISC16_M30H 0x1583 113 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 114 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 115 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */ 116 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630 117 #define DEVICEID_AMD_HOSTB19H_M10H_ROOT 0x14a4 118 #define DEVICEID_AMD_HOSTB19H_M40H_ROOT 0x14b5 119 #define DEVICEID_AMD_HOSTB19H_M60H_ROOT 0x14d8 120 #define DEVICEID_AMD_HOSTB19H_M70H_ROOT 0x14e8 121 122 static const struct amdtemp_product { 123 uint16_t amdtemp_vendorid; 124 uint16_t amdtemp_deviceid; 125 /* 126 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 127 * drivers do not attach to that device. 128 */ 129 bool amdtemp_has_cpuid; 130 } amdtemp_products[] = { 131 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 132 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 133 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 134 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 135 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 136 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 137 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 138 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 139 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 140 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 141 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 142 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 143 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 144 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false }, 145 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M10H_ROOT, false }, 146 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M40H_ROOT, false }, 147 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M60H_ROOT, false }, 148 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M70H_ROOT, false }, 149 }; 150 151 /* 152 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 153 */ 154 #define AMDTEMP_REPTMP_CTRL 0xa4 155 156 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 157 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 158 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 159 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 160 161 /* 162 * Reported Temperature, Family 15h, M60+ 163 * 164 * Same register bit definitions as other Family 15h CPUs, but access is 165 * indirect via SMN, like Family 17h. 166 */ 167 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 168 169 /* 170 * Reported Temperature, Family 17h 171 * 172 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 173 * provide the current temp. bit 19, when clear, means the temp is reported in 174 * a range 0.."225C" (probable typo for 255C), and when set changes the range 175 * to -49..206C. 176 */ 177 #define AMDTEMP_17H_CUR_TMP 0x59800 178 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 179 /* 180 * Bits 16-17, when set, mean that CUR_TMP is read-write. When it is, the 181 * 49 degree offset should apply as well. This was revealed in a Linux 182 * patch from an AMD employee. 183 */ 184 #define AMDTEMP_17H_CUR_TMP_TJ_SEL ((1u << 17) | (1u << 16)) 185 /* 186 * The following register set was discovered experimentally by Ondrej Čerman 187 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 188 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 189 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 190 */ 191 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 192 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 193 194 #define AMDTEMP_ZEN4_10H_CCD_TMP_BASE 0x59b00 195 #define AMDTEMP_ZEN4_CCD_TMP_BASE 0x59b08 196 197 /* 198 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 199 */ 200 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 201 202 /* 203 * Thermaltrip Status Register (Family 0Fh only) 204 */ 205 #define AMDTEMP_THERMTP_STAT 0xe4 206 #define AMDTEMP_TTSR_SELCORE 0x04 207 #define AMDTEMP_TTSR_SELSENSOR 0x40 208 209 /* 210 * DRAM Configuration High Register 211 */ 212 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 213 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 214 215 /* 216 * CPU Family/Model Register 217 */ 218 #define AMDTEMP_CPUID 0xfc 219 220 /* 221 * Device methods. 222 */ 223 static void amdtemp_identify(driver_t *driver, device_t parent); 224 static int amdtemp_probe(device_t dev); 225 static int amdtemp_attach(device_t dev); 226 static void amdtemp_intrhook(void *arg); 227 static int amdtemp_detach(device_t dev); 228 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 229 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 230 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 231 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 232 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 233 static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model); 234 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 235 236 static device_method_t amdtemp_methods[] = { 237 /* Device interface */ 238 DEVMETHOD(device_identify, amdtemp_identify), 239 DEVMETHOD(device_probe, amdtemp_probe), 240 DEVMETHOD(device_attach, amdtemp_attach), 241 DEVMETHOD(device_detach, amdtemp_detach), 242 243 DEVMETHOD_END 244 }; 245 246 static driver_t amdtemp_driver = { 247 "amdtemp", 248 amdtemp_methods, 249 sizeof(struct amdtemp_softc), 250 }; 251 252 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, NULL, NULL); 253 MODULE_VERSION(amdtemp, 1); 254 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 255 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 256 nitems(amdtemp_products)); 257 258 static bool 259 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 260 { 261 int i; 262 uint16_t vendor, devid; 263 264 vendor = pci_get_vendor(dev); 265 devid = pci_get_device(dev); 266 267 for (i = 0; i < nitems(amdtemp_products); i++) { 268 if (vendor == amdtemp_products[i].amdtemp_vendorid && 269 devid == amdtemp_products[i].amdtemp_deviceid) { 270 if (product_out != NULL) 271 *product_out = &amdtemp_products[i]; 272 return (true); 273 } 274 } 275 return (false); 276 } 277 278 static void 279 amdtemp_identify(driver_t *driver, device_t parent) 280 { 281 device_t child; 282 283 /* Make sure we're not being doubly invoked. */ 284 if (device_find_child(parent, "amdtemp", -1) != NULL) 285 return; 286 287 if (amdtemp_match(parent, NULL)) { 288 child = device_add_child(parent, "amdtemp", -1); 289 if (child == NULL) 290 device_printf(parent, "add amdtemp child failed\n"); 291 } 292 } 293 294 static int 295 amdtemp_probe(device_t dev) 296 { 297 uint32_t family, model; 298 299 if (resource_disabled("amdtemp", 0)) 300 return (ENXIO); 301 if (!amdtemp_match(device_get_parent(dev), NULL)) 302 return (ENXIO); 303 304 family = CPUID_TO_FAMILY(cpu_id); 305 model = CPUID_TO_MODEL(cpu_id); 306 307 switch (family) { 308 case 0x0f: 309 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 310 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 311 return (ENXIO); 312 break; 313 case 0x10: 314 case 0x11: 315 case 0x12: 316 case 0x14: 317 case 0x15: 318 case 0x16: 319 case 0x17: 320 case 0x19: 321 break; 322 default: 323 return (ENXIO); 324 } 325 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 326 327 return (BUS_PROBE_GENERIC); 328 } 329 330 static int 331 amdtemp_attach(device_t dev) 332 { 333 char tn[32]; 334 u_int regs[4]; 335 const struct amdtemp_product *product; 336 struct amdtemp_softc *sc; 337 struct sysctl_ctx_list *sysctlctx; 338 struct sysctl_oid *sysctlnode; 339 uint32_t cpuid, family, model; 340 u_int bid; 341 int erratum319, unit; 342 bool needsmn; 343 344 sc = device_get_softc(dev); 345 erratum319 = 0; 346 needsmn = false; 347 348 if (!amdtemp_match(device_get_parent(dev), &product)) 349 return (ENXIO); 350 351 cpuid = cpu_id; 352 family = CPUID_TO_FAMILY(cpuid); 353 model = CPUID_TO_MODEL(cpuid); 354 355 /* 356 * This checks for the byzantine condition of running a heterogenous 357 * revision multi-socket system where the attach thread is potentially 358 * probing a remote socket's PCI device. 359 * 360 * Currently, such scenarios are unsupported on models using the SMN 361 * (because on those models, amdtemp(4) attaches to a different PCI 362 * device than the one that contains AMDTEMP_CPUID). 363 * 364 * The ancient 0x0F family of devices only supports this register from 365 * models 40h+. 366 */ 367 if (product->amdtemp_has_cpuid && (family > 0x0f || 368 (family == 0x0f && model >= 0x40))) { 369 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 370 4); 371 family = CPUID_TO_FAMILY(cpuid); 372 model = CPUID_TO_MODEL(cpuid); 373 } 374 375 switch (family) { 376 case 0x0f: 377 /* 378 * Thermaltrip Status Register 379 * 380 * - ThermSenseCoreSel 381 * 382 * Revision F & G: 0 - Core1, 1 - Core0 383 * Other: 0 - Core0, 1 - Core1 384 * 385 * - CurTmp 386 * 387 * Revision G: bits 23-14 388 * Other: bits 23-16 389 * 390 * XXX According to the BKDG, CurTmp, ThermSenseSel and 391 * ThermSenseCoreSel bits were introduced in Revision F 392 * but CurTmp seems working fine as early as Revision C. 393 * However, it is not clear whether ThermSenseSel and/or 394 * ThermSenseCoreSel work in undocumented cases as well. 395 * In fact, the Linux driver suggests it may not work but 396 * we just assume it does until we find otherwise. 397 * 398 * XXX According to Linux, CurTmp starts at -28C on 399 * Socket AM2 Revision G processors, which is not 400 * documented anywhere. 401 */ 402 if (model >= 0x40) 403 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 404 if (model >= 0x60 && model != 0xc1) { 405 do_cpuid(0x80000001, regs); 406 bid = (regs[1] >> 9) & 0x1f; 407 switch (model) { 408 case 0x68: /* Socket S1g1 */ 409 case 0x6c: 410 case 0x7c: 411 break; 412 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 413 if (bid != 0x0b && bid != 0x0c) 414 sc->sc_flags |= 415 AMDTEMP_FLAG_ALT_OFFSET; 416 break; 417 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 418 case 0x7f: 419 if (bid != 0x07 && bid != 0x09 && 420 bid != 0x0c) 421 sc->sc_flags |= 422 AMDTEMP_FLAG_ALT_OFFSET; 423 break; 424 default: 425 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 426 } 427 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 428 } 429 430 /* 431 * There are two sensors per core. 432 */ 433 sc->sc_ntemps = 2; 434 435 sc->sc_gettemp = amdtemp_gettemp0f; 436 break; 437 case 0x10: 438 /* 439 * Erratum 319 Inaccurate Temperature Measurement 440 * 441 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 442 */ 443 do_cpuid(0x80000001, regs); 444 switch ((regs[1] >> 28) & 0xf) { 445 case 0: /* Socket F */ 446 erratum319 = 1; 447 break; 448 case 1: /* Socket AM2+ or AM3 */ 449 if ((pci_cfgregread(pci_get_domain(dev), 450 pci_get_bus(dev), pci_get_slot(dev), 2, 451 AMDTEMP_DRAM_CONF_HIGH, 2) & 452 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 453 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 454 break; 455 /* XXX 00100F42h (RB-C2) exists in both formats. */ 456 erratum319 = 1; 457 break; 458 } 459 /* FALLTHROUGH */ 460 case 0x11: 461 case 0x12: 462 case 0x14: 463 case 0x15: 464 case 0x16: 465 sc->sc_ntemps = 1; 466 /* 467 * Some later (60h+) models of family 15h use a similar SMN 468 * network as family 17h. (However, the register index differs 469 * from 17h and the decoding matches other 10h-15h models, 470 * which differ from 17h.) 471 */ 472 if (family == 0x15 && model >= 0x60) { 473 sc->sc_gettemp = amdtemp_gettemp15hm60h; 474 needsmn = true; 475 } else 476 sc->sc_gettemp = amdtemp_gettemp; 477 break; 478 case 0x17: 479 case 0x19: 480 sc->sc_ntemps = 1; 481 sc->sc_gettemp = amdtemp_gettemp17h; 482 needsmn = true; 483 break; 484 default: 485 device_printf(dev, "Bogus family 0x%x\n", family); 486 return (ENXIO); 487 } 488 489 if (needsmn) { 490 sc->sc_smn = device_find_child( 491 device_get_parent(dev), "amdsmn", -1); 492 if (sc->sc_smn == NULL) { 493 if (bootverbose) 494 device_printf(dev, "No SMN device found\n"); 495 return (ENXIO); 496 } 497 } 498 499 /* Find number of cores per package. */ 500 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 501 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 502 if (sc->sc_ncores > MAXCPU) 503 return (ENXIO); 504 505 mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF); 506 if (erratum319) 507 device_printf(dev, 508 "Erratum 319: temperature measurement may be inaccurate\n"); 509 if (bootverbose) 510 device_printf(dev, "Found %d cores and %d sensors.\n", 511 sc->sc_ncores, 512 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 513 514 /* 515 * dev.amdtemp.N tree. 516 */ 517 unit = device_get_unit(dev); 518 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 519 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 520 521 sysctlctx = device_get_sysctl_ctx(dev); 522 SYSCTL_ADD_INT(sysctlctx, 523 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 524 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 525 "Temperature sensor offset"); 526 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 527 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 528 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0"); 529 530 SYSCTL_ADD_PROC(sysctlctx, 531 SYSCTL_CHILDREN(sysctlnode), 532 OID_AUTO, "sensor0", 533 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 534 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 535 "Core 0 / Sensor 0 temperature"); 536 537 sc->sc_temp_base = AMDTEMP_17H_CCD_TMP_BASE; 538 539 if (family == 0x17) 540 amdtemp_probe_ccd_sensors17h(dev, model); 541 else if (family == 0x19) 542 amdtemp_probe_ccd_sensors19h(dev, model); 543 else if (sc->sc_ntemps > 1) { 544 SYSCTL_ADD_PROC(sysctlctx, 545 SYSCTL_CHILDREN(sysctlnode), 546 OID_AUTO, "sensor1", 547 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 548 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 549 "Core 0 / Sensor 1 temperature"); 550 551 if (sc->sc_ncores > 1) { 552 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 553 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 554 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE, 555 0, "Core 1"); 556 557 SYSCTL_ADD_PROC(sysctlctx, 558 SYSCTL_CHILDREN(sysctlnode), 559 OID_AUTO, "sensor0", 560 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 561 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 562 "Core 1 / Sensor 0 temperature"); 563 564 SYSCTL_ADD_PROC(sysctlctx, 565 SYSCTL_CHILDREN(sysctlnode), 566 OID_AUTO, "sensor1", 567 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 568 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 569 "Core 1 / Sensor 1 temperature"); 570 } 571 } 572 573 /* 574 * Try to create dev.cpu sysctl entries and setup intrhook function. 575 * This is needed because the cpu driver may be loaded late on boot, 576 * after us. 577 */ 578 amdtemp_intrhook(dev); 579 sc->sc_ich.ich_func = amdtemp_intrhook; 580 sc->sc_ich.ich_arg = dev; 581 if (config_intrhook_establish(&sc->sc_ich) != 0) { 582 device_printf(dev, "config_intrhook_establish failed!\n"); 583 return (ENXIO); 584 } 585 586 return (0); 587 } 588 589 void 590 amdtemp_intrhook(void *arg) 591 { 592 struct amdtemp_softc *sc; 593 struct sysctl_ctx_list *sysctlctx; 594 device_t dev = (device_t)arg; 595 device_t acpi, cpu, nexus; 596 amdsensor_t sensor; 597 int i; 598 599 sc = device_get_softc(dev); 600 601 /* 602 * dev.cpu.N.temperature. 603 */ 604 nexus = device_find_child(root_bus, "nexus", 0); 605 acpi = device_find_child(nexus, "acpi", 0); 606 607 for (i = 0; i < sc->sc_ncores; i++) { 608 if (sc->sc_sysctl_cpu[i] != NULL) 609 continue; 610 cpu = device_find_child(acpi, "cpu", 611 device_get_unit(dev) * sc->sc_ncores + i); 612 if (cpu != NULL) { 613 sysctlctx = device_get_sysctl_ctx(cpu); 614 615 sensor = sc->sc_ntemps > 1 ? 616 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 617 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 618 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 619 OID_AUTO, "temperature", 620 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 621 dev, sensor, amdtemp_sysctl, "IK", 622 "Current temparature"); 623 } 624 } 625 if (sc->sc_ich.ich_arg != NULL) 626 config_intrhook_disestablish(&sc->sc_ich); 627 } 628 629 int 630 amdtemp_detach(device_t dev) 631 { 632 struct amdtemp_softc *sc = device_get_softc(dev); 633 int i; 634 635 for (i = 0; i < sc->sc_ncores; i++) 636 if (sc->sc_sysctl_cpu[i] != NULL) 637 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 638 639 /* NewBus removes the dev.amdtemp.N tree by itself. */ 640 641 mtx_destroy(&sc->sc_lock); 642 return (0); 643 } 644 645 static int 646 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 647 { 648 device_t dev = (device_t)arg1; 649 struct amdtemp_softc *sc = device_get_softc(dev); 650 amdsensor_t sensor = (amdsensor_t)arg2; 651 int32_t auxtemp[2], temp; 652 int error; 653 654 switch (sensor) { 655 case CORE0: 656 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 657 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 658 temp = imax(auxtemp[0], auxtemp[1]); 659 break; 660 case CORE1: 661 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 662 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 663 temp = imax(auxtemp[0], auxtemp[1]); 664 break; 665 default: 666 temp = sc->sc_gettemp(dev, sensor); 667 break; 668 } 669 error = sysctl_handle_int(oidp, &temp, 0, req); 670 671 return (error); 672 } 673 674 #define AMDTEMP_ZERO_C_TO_K 2731 675 676 static int32_t 677 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 678 { 679 struct amdtemp_softc *sc = device_get_softc(dev); 680 uint32_t mask, offset, temp; 681 682 mtx_lock(&sc->sc_lock); 683 684 /* Set Sensor/Core selector. */ 685 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 686 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 687 switch (sensor) { 688 case CORE0_SENSOR1: 689 temp |= AMDTEMP_TTSR_SELSENSOR; 690 /* FALLTHROUGH */ 691 case CORE0_SENSOR0: 692 case CORE0: 693 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 694 temp |= AMDTEMP_TTSR_SELCORE; 695 break; 696 case CORE1_SENSOR1: 697 temp |= AMDTEMP_TTSR_SELSENSOR; 698 /* FALLTHROUGH */ 699 case CORE1_SENSOR0: 700 case CORE1: 701 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 702 temp |= AMDTEMP_TTSR_SELCORE; 703 break; 704 default: 705 __assert_unreachable(); 706 } 707 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 708 709 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 710 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 711 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 712 temp = ((temp >> 14) & mask) * 5 / 2; 713 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 714 715 mtx_unlock(&sc->sc_lock); 716 return (temp); 717 } 718 719 static uint32_t 720 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 721 { 722 uint32_t temp; 723 724 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 725 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 726 727 if (minus49) 728 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 729 730 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 731 return (temp); 732 } 733 734 static uint32_t 735 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 736 { 737 bool minus49; 738 739 /* 740 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 741 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 742 * documented in BKDGs prior to family 15h model 00h.) 743 */ 744 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 745 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 746 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 747 748 return (amdtemp_decode_fam10h_to_17h(sc_offset, 749 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 750 } 751 752 static uint32_t 753 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 754 { 755 bool minus49; 756 757 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0) 758 || ((val & AMDTEMP_17H_CUR_TMP_TJ_SEL) == AMDTEMP_17H_CUR_TMP_TJ_SEL); 759 return (amdtemp_decode_fam10h_to_17h(sc_offset, 760 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 761 } 762 763 static int32_t 764 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 765 { 766 struct amdtemp_softc *sc = device_get_softc(dev); 767 uint32_t temp; 768 769 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 770 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 771 } 772 773 static int32_t 774 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 775 { 776 struct amdtemp_softc *sc = device_get_softc(dev); 777 uint32_t val; 778 int error __diagused; 779 780 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 781 KASSERT(error == 0, ("amdsmn_read")); 782 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 783 } 784 785 static int32_t 786 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 787 { 788 struct amdtemp_softc *sc = device_get_softc(dev); 789 uint32_t val; 790 int error __diagused; 791 792 switch (sensor) { 793 case CORE0_SENSOR0: 794 /* Tctl */ 795 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 796 KASSERT(error == 0, ("amdsmn_read")); 797 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 798 case CCD_BASE ... CCD_MAX: 799 /* Tccd<N> */ 800 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + 801 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 802 KASSERT(error == 0, ("amdsmn_read2")); 803 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 804 ("sensor %d: not valid", (int)sensor)); 805 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 806 default: 807 __assert_unreachable(); 808 } 809 } 810 811 static void 812 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg) 813 { 814 char sensor_name[16], sensor_descr[32]; 815 struct amdtemp_softc *sc; 816 uint32_t i, val; 817 int error; 818 819 sc = device_get_softc(dev); 820 for (i = 0; i < maxreg; i++) { 821 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + 822 (i * sizeof(val)), &val); 823 if (error != 0) 824 continue; 825 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 826 continue; 827 828 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 829 snprintf(sensor_descr, sizeof(sensor_descr), 830 "CCD %u temperature (Tccd%u)", i, i); 831 832 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 833 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 834 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 835 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 836 } 837 } 838 839 static void 840 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 841 { 842 uint32_t maxreg; 843 844 switch (model) { 845 case 0x00 ... 0x2f: /* Zen1, Zen+ */ 846 maxreg = 4; 847 break; 848 case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */ 849 case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */ 850 case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */ 851 maxreg = 8; 852 _Static_assert((int)NUM_CCDS >= 8, ""); 853 break; 854 default: 855 device_printf(dev, 856 "Unrecognized Family 17h Model: %02xh\n", model); 857 return; 858 } 859 860 amdtemp_probe_ccd_sensors(dev, maxreg); 861 } 862 863 static void 864 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model) 865 { 866 struct amdtemp_softc *sc = device_get_softc(dev); 867 uint32_t maxreg; 868 869 switch (model) { 870 case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */ 871 case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */ 872 maxreg = 8; 873 _Static_assert((int)NUM_CCDS >= 8, ""); 874 break; 875 case 0x10 ... 0x1f: 876 sc->sc_temp_base = AMDTEMP_ZEN4_10H_CCD_TMP_BASE; 877 maxreg = 12; 878 _Static_assert((int)NUM_CCDS >= 12, ""); 879 break; 880 case 0x40 ... 0x4f: /* Zen3+ Ryzen "Rembrandt" */ 881 case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */ 882 case 0x70 ... 0x7f: /* Zen4 Ryzen "Phoenix" */ 883 sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE; 884 maxreg = 8; 885 _Static_assert((int)NUM_CCDS >= 8, ""); 886 break; 887 default: 888 device_printf(dev, 889 "Unrecognized Family 19h Model: %02xh\n", model); 890 return; 891 } 892 893 amdtemp_probe_ccd_sensors(dev, maxreg); 894 } 895