1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <[email protected]> 5 * Copyright (c) 2009 Norikatsu Shigemura <[email protected]> 6 * Copyright (c) 2009-2012 Jung-uk Kim <[email protected]> 7 * All rights reserved. 8 * Copyright (c) 2017-2020 Conrad Meyer <[email protected]>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the AMD CPU on-die thermal sensors. 34 * Initially based on the k8temp Linux driver. 35 */ 36 37 #include <sys/cdefs.h> 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/sysctl.h> 46 #include <sys/systm.h> 47 48 #include <machine/cpufunc.h> 49 #include <machine/md_var.h> 50 #include <machine/specialreg.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <x86/pci_cfgreg.h> 54 55 #include <dev/amdsmn/amdsmn.h> 56 57 typedef enum { 58 CORE0_SENSOR0, 59 CORE0_SENSOR1, 60 CORE1_SENSOR0, 61 CORE1_SENSOR1, 62 CORE0, 63 CORE1, 64 CCD1, 65 CCD_BASE = CCD1, 66 CCD2, 67 CCD3, 68 CCD4, 69 CCD5, 70 CCD6, 71 CCD7, 72 CCD8, 73 CCD_MAX = CCD8, 74 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 75 } amdsensor_t; 76 77 struct amdtemp_softc { 78 int sc_ncores; 79 int sc_ntemps; 80 int sc_flags; 81 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 82 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 83 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 84 int32_t sc_offset; 85 int32_t sc_temp_base; 86 int32_t (*sc_gettemp)(device_t, amdsensor_t); 87 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 88 struct intr_config_hook sc_ich; 89 device_t sc_smn; 90 struct mtx sc_lock; 91 }; 92 93 /* 94 * N.B. The numbers in macro names below are significant and represent CPU 95 * family and model numbers. Do not make up fictitious family or model numbers 96 * when adding support for new devices. 97 */ 98 #define VENDORID_AMD 0x1022 99 #define DEVICEID_AMD_MISC0F 0x1103 100 #define DEVICEID_AMD_MISC10 0x1203 101 #define DEVICEID_AMD_MISC11 0x1303 102 #define DEVICEID_AMD_MISC14 0x1703 103 #define DEVICEID_AMD_MISC15 0x1603 104 #define DEVICEID_AMD_MISC15_M10H 0x1403 105 #define DEVICEID_AMD_MISC15_M30H 0x141d 106 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 107 #define DEVICEID_AMD_MISC16 0x1533 108 #define DEVICEID_AMD_MISC16_M30H 0x1583 109 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 110 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 111 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */ 112 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630 113 #define DEVICEID_AMD_HOSTB19H_M60H_ROOT 0x14d8 114 115 static const struct amdtemp_product { 116 uint16_t amdtemp_vendorid; 117 uint16_t amdtemp_deviceid; 118 /* 119 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 120 * drivers do not attach to that device. 121 */ 122 bool amdtemp_has_cpuid; 123 } amdtemp_products[] = { 124 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 125 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 126 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 127 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 128 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 129 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 130 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 131 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 132 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 133 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 134 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 135 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 136 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 137 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false }, 138 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M60H_ROOT, false }, 139 }; 140 141 /* 142 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 143 */ 144 #define AMDTEMP_REPTMP_CTRL 0xa4 145 146 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 147 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 148 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 149 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 150 151 /* 152 * Reported Temperature, Family 15h, M60+ 153 * 154 * Same register bit definitions as other Family 15h CPUs, but access is 155 * indirect via SMN, like Family 17h. 156 */ 157 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 158 159 /* 160 * Reported Temperature, Family 17h 161 * 162 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 163 * provide the current temp. bit 19, when clear, means the temp is reported in 164 * a range 0.."225C" (probable typo for 255C), and when set changes the range 165 * to -49..206C. 166 */ 167 #define AMDTEMP_17H_CUR_TMP 0x59800 168 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 169 /* 170 * Bits 16-17, when set, mean that CUR_TMP is read-write. When it is, the 171 * 49 degree offset should apply as well. This was revealed in a Linux 172 * patch from an AMD employee. 173 */ 174 #define AMDTEMP_17H_CUR_TMP_TJ_SEL ((1u << 17) | (1u << 16)) 175 /* 176 * The following register set was discovered experimentally by Ondrej Čerman 177 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 178 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 179 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 180 */ 181 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 182 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 183 184 #define AMDTEMP_ZEN4_CCD_TMP_BASE 0x59b08 185 186 /* 187 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 188 */ 189 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 190 191 /* 192 * Thermaltrip Status Register (Family 0Fh only) 193 */ 194 #define AMDTEMP_THERMTP_STAT 0xe4 195 #define AMDTEMP_TTSR_SELCORE 0x04 196 #define AMDTEMP_TTSR_SELSENSOR 0x40 197 198 /* 199 * DRAM Configuration High Register 200 */ 201 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 202 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 203 204 /* 205 * CPU Family/Model Register 206 */ 207 #define AMDTEMP_CPUID 0xfc 208 209 /* 210 * Device methods. 211 */ 212 static void amdtemp_identify(driver_t *driver, device_t parent); 213 static int amdtemp_probe(device_t dev); 214 static int amdtemp_attach(device_t dev); 215 static void amdtemp_intrhook(void *arg); 216 static int amdtemp_detach(device_t dev); 217 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 218 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 219 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 220 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 221 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 222 static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model); 223 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 224 225 static device_method_t amdtemp_methods[] = { 226 /* Device interface */ 227 DEVMETHOD(device_identify, amdtemp_identify), 228 DEVMETHOD(device_probe, amdtemp_probe), 229 DEVMETHOD(device_attach, amdtemp_attach), 230 DEVMETHOD(device_detach, amdtemp_detach), 231 232 DEVMETHOD_END 233 }; 234 235 static driver_t amdtemp_driver = { 236 "amdtemp", 237 amdtemp_methods, 238 sizeof(struct amdtemp_softc), 239 }; 240 241 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, NULL, NULL); 242 MODULE_VERSION(amdtemp, 1); 243 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 244 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 245 nitems(amdtemp_products)); 246 247 static bool 248 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 249 { 250 int i; 251 uint16_t vendor, devid; 252 253 vendor = pci_get_vendor(dev); 254 devid = pci_get_device(dev); 255 256 for (i = 0; i < nitems(amdtemp_products); i++) { 257 if (vendor == amdtemp_products[i].amdtemp_vendorid && 258 devid == amdtemp_products[i].amdtemp_deviceid) { 259 if (product_out != NULL) 260 *product_out = &amdtemp_products[i]; 261 return (true); 262 } 263 } 264 return (false); 265 } 266 267 static void 268 amdtemp_identify(driver_t *driver, device_t parent) 269 { 270 device_t child; 271 272 /* Make sure we're not being doubly invoked. */ 273 if (device_find_child(parent, "amdtemp", -1) != NULL) 274 return; 275 276 if (amdtemp_match(parent, NULL)) { 277 child = device_add_child(parent, "amdtemp", -1); 278 if (child == NULL) 279 device_printf(parent, "add amdtemp child failed\n"); 280 } 281 } 282 283 static int 284 amdtemp_probe(device_t dev) 285 { 286 uint32_t family, model; 287 288 if (resource_disabled("amdtemp", 0)) 289 return (ENXIO); 290 if (!amdtemp_match(device_get_parent(dev), NULL)) 291 return (ENXIO); 292 293 family = CPUID_TO_FAMILY(cpu_id); 294 model = CPUID_TO_MODEL(cpu_id); 295 296 switch (family) { 297 case 0x0f: 298 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 299 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 300 return (ENXIO); 301 break; 302 case 0x10: 303 case 0x11: 304 case 0x12: 305 case 0x14: 306 case 0x15: 307 case 0x16: 308 case 0x17: 309 case 0x19: 310 break; 311 default: 312 return (ENXIO); 313 } 314 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 315 316 return (BUS_PROBE_GENERIC); 317 } 318 319 static int 320 amdtemp_attach(device_t dev) 321 { 322 char tn[32]; 323 u_int regs[4]; 324 const struct amdtemp_product *product; 325 struct amdtemp_softc *sc; 326 struct sysctl_ctx_list *sysctlctx; 327 struct sysctl_oid *sysctlnode; 328 uint32_t cpuid, family, model; 329 u_int bid; 330 int erratum319, unit; 331 bool needsmn; 332 333 sc = device_get_softc(dev); 334 erratum319 = 0; 335 needsmn = false; 336 337 if (!amdtemp_match(device_get_parent(dev), &product)) 338 return (ENXIO); 339 340 cpuid = cpu_id; 341 family = CPUID_TO_FAMILY(cpuid); 342 model = CPUID_TO_MODEL(cpuid); 343 344 /* 345 * This checks for the byzantine condition of running a heterogenous 346 * revision multi-socket system where the attach thread is potentially 347 * probing a remote socket's PCI device. 348 * 349 * Currently, such scenarios are unsupported on models using the SMN 350 * (because on those models, amdtemp(4) attaches to a different PCI 351 * device than the one that contains AMDTEMP_CPUID). 352 * 353 * The ancient 0x0F family of devices only supports this register from 354 * models 40h+. 355 */ 356 if (product->amdtemp_has_cpuid && (family > 0x0f || 357 (family == 0x0f && model >= 0x40))) { 358 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 359 4); 360 family = CPUID_TO_FAMILY(cpuid); 361 model = CPUID_TO_MODEL(cpuid); 362 } 363 364 switch (family) { 365 case 0x0f: 366 /* 367 * Thermaltrip Status Register 368 * 369 * - ThermSenseCoreSel 370 * 371 * Revision F & G: 0 - Core1, 1 - Core0 372 * Other: 0 - Core0, 1 - Core1 373 * 374 * - CurTmp 375 * 376 * Revision G: bits 23-14 377 * Other: bits 23-16 378 * 379 * XXX According to the BKDG, CurTmp, ThermSenseSel and 380 * ThermSenseCoreSel bits were introduced in Revision F 381 * but CurTmp seems working fine as early as Revision C. 382 * However, it is not clear whether ThermSenseSel and/or 383 * ThermSenseCoreSel work in undocumented cases as well. 384 * In fact, the Linux driver suggests it may not work but 385 * we just assume it does until we find otherwise. 386 * 387 * XXX According to Linux, CurTmp starts at -28C on 388 * Socket AM2 Revision G processors, which is not 389 * documented anywhere. 390 */ 391 if (model >= 0x40) 392 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 393 if (model >= 0x60 && model != 0xc1) { 394 do_cpuid(0x80000001, regs); 395 bid = (regs[1] >> 9) & 0x1f; 396 switch (model) { 397 case 0x68: /* Socket S1g1 */ 398 case 0x6c: 399 case 0x7c: 400 break; 401 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 402 if (bid != 0x0b && bid != 0x0c) 403 sc->sc_flags |= 404 AMDTEMP_FLAG_ALT_OFFSET; 405 break; 406 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 407 case 0x7f: 408 if (bid != 0x07 && bid != 0x09 && 409 bid != 0x0c) 410 sc->sc_flags |= 411 AMDTEMP_FLAG_ALT_OFFSET; 412 break; 413 default: 414 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 415 } 416 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 417 } 418 419 /* 420 * There are two sensors per core. 421 */ 422 sc->sc_ntemps = 2; 423 424 sc->sc_gettemp = amdtemp_gettemp0f; 425 break; 426 case 0x10: 427 /* 428 * Erratum 319 Inaccurate Temperature Measurement 429 * 430 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 431 */ 432 do_cpuid(0x80000001, regs); 433 switch ((regs[1] >> 28) & 0xf) { 434 case 0: /* Socket F */ 435 erratum319 = 1; 436 break; 437 case 1: /* Socket AM2+ or AM3 */ 438 if ((pci_cfgregread(pci_get_domain(dev), 439 pci_get_bus(dev), pci_get_slot(dev), 2, 440 AMDTEMP_DRAM_CONF_HIGH, 2) & 441 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 442 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 443 break; 444 /* XXX 00100F42h (RB-C2) exists in both formats. */ 445 erratum319 = 1; 446 break; 447 } 448 /* FALLTHROUGH */ 449 case 0x11: 450 case 0x12: 451 case 0x14: 452 case 0x15: 453 case 0x16: 454 sc->sc_ntemps = 1; 455 /* 456 * Some later (60h+) models of family 15h use a similar SMN 457 * network as family 17h. (However, the register index differs 458 * from 17h and the decoding matches other 10h-15h models, 459 * which differ from 17h.) 460 */ 461 if (family == 0x15 && model >= 0x60) { 462 sc->sc_gettemp = amdtemp_gettemp15hm60h; 463 needsmn = true; 464 } else 465 sc->sc_gettemp = amdtemp_gettemp; 466 break; 467 case 0x17: 468 case 0x19: 469 sc->sc_ntemps = 1; 470 sc->sc_gettemp = amdtemp_gettemp17h; 471 needsmn = true; 472 break; 473 default: 474 device_printf(dev, "Bogus family 0x%x\n", family); 475 return (ENXIO); 476 } 477 478 if (needsmn) { 479 sc->sc_smn = device_find_child( 480 device_get_parent(dev), "amdsmn", -1); 481 if (sc->sc_smn == NULL) { 482 if (bootverbose) 483 device_printf(dev, "No SMN device found\n"); 484 return (ENXIO); 485 } 486 } 487 488 /* Find number of cores per package. */ 489 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 490 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 491 if (sc->sc_ncores > MAXCPU) 492 return (ENXIO); 493 494 mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF); 495 if (erratum319) 496 device_printf(dev, 497 "Erratum 319: temperature measurement may be inaccurate\n"); 498 if (bootverbose) 499 device_printf(dev, "Found %d cores and %d sensors.\n", 500 sc->sc_ncores, 501 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 502 503 /* 504 * dev.amdtemp.N tree. 505 */ 506 unit = device_get_unit(dev); 507 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 508 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 509 510 sysctlctx = device_get_sysctl_ctx(dev); 511 SYSCTL_ADD_INT(sysctlctx, 512 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 513 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 514 "Temperature sensor offset"); 515 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 516 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 517 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0"); 518 519 SYSCTL_ADD_PROC(sysctlctx, 520 SYSCTL_CHILDREN(sysctlnode), 521 OID_AUTO, "sensor0", 522 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 523 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 524 "Core 0 / Sensor 0 temperature"); 525 526 sc->sc_temp_base = AMDTEMP_17H_CCD_TMP_BASE; 527 528 if (family == 0x17) 529 amdtemp_probe_ccd_sensors17h(dev, model); 530 else if (family == 0x19) 531 amdtemp_probe_ccd_sensors19h(dev, model); 532 else if (sc->sc_ntemps > 1) { 533 SYSCTL_ADD_PROC(sysctlctx, 534 SYSCTL_CHILDREN(sysctlnode), 535 OID_AUTO, "sensor1", 536 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 537 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 538 "Core 0 / Sensor 1 temperature"); 539 540 if (sc->sc_ncores > 1) { 541 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 542 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 543 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE, 544 0, "Core 1"); 545 546 SYSCTL_ADD_PROC(sysctlctx, 547 SYSCTL_CHILDREN(sysctlnode), 548 OID_AUTO, "sensor0", 549 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 550 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 551 "Core 1 / Sensor 0 temperature"); 552 553 SYSCTL_ADD_PROC(sysctlctx, 554 SYSCTL_CHILDREN(sysctlnode), 555 OID_AUTO, "sensor1", 556 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 557 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 558 "Core 1 / Sensor 1 temperature"); 559 } 560 } 561 562 /* 563 * Try to create dev.cpu sysctl entries and setup intrhook function. 564 * This is needed because the cpu driver may be loaded late on boot, 565 * after us. 566 */ 567 amdtemp_intrhook(dev); 568 sc->sc_ich.ich_func = amdtemp_intrhook; 569 sc->sc_ich.ich_arg = dev; 570 if (config_intrhook_establish(&sc->sc_ich) != 0) { 571 device_printf(dev, "config_intrhook_establish failed!\n"); 572 return (ENXIO); 573 } 574 575 return (0); 576 } 577 578 void 579 amdtemp_intrhook(void *arg) 580 { 581 struct amdtemp_softc *sc; 582 struct sysctl_ctx_list *sysctlctx; 583 device_t dev = (device_t)arg; 584 device_t acpi, cpu, nexus; 585 amdsensor_t sensor; 586 int i; 587 588 sc = device_get_softc(dev); 589 590 /* 591 * dev.cpu.N.temperature. 592 */ 593 nexus = device_find_child(root_bus, "nexus", 0); 594 acpi = device_find_child(nexus, "acpi", 0); 595 596 for (i = 0; i < sc->sc_ncores; i++) { 597 if (sc->sc_sysctl_cpu[i] != NULL) 598 continue; 599 cpu = device_find_child(acpi, "cpu", 600 device_get_unit(dev) * sc->sc_ncores + i); 601 if (cpu != NULL) { 602 sysctlctx = device_get_sysctl_ctx(cpu); 603 604 sensor = sc->sc_ntemps > 1 ? 605 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 606 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 607 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 608 OID_AUTO, "temperature", 609 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 610 dev, sensor, amdtemp_sysctl, "IK", 611 "Current temparature"); 612 } 613 } 614 if (sc->sc_ich.ich_arg != NULL) 615 config_intrhook_disestablish(&sc->sc_ich); 616 } 617 618 int 619 amdtemp_detach(device_t dev) 620 { 621 struct amdtemp_softc *sc = device_get_softc(dev); 622 int i; 623 624 for (i = 0; i < sc->sc_ncores; i++) 625 if (sc->sc_sysctl_cpu[i] != NULL) 626 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 627 628 /* NewBus removes the dev.amdtemp.N tree by itself. */ 629 630 mtx_destroy(&sc->sc_lock); 631 return (0); 632 } 633 634 static int 635 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 636 { 637 device_t dev = (device_t)arg1; 638 struct amdtemp_softc *sc = device_get_softc(dev); 639 amdsensor_t sensor = (amdsensor_t)arg2; 640 int32_t auxtemp[2], temp; 641 int error; 642 643 switch (sensor) { 644 case CORE0: 645 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 646 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 647 temp = imax(auxtemp[0], auxtemp[1]); 648 break; 649 case CORE1: 650 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 651 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 652 temp = imax(auxtemp[0], auxtemp[1]); 653 break; 654 default: 655 temp = sc->sc_gettemp(dev, sensor); 656 break; 657 } 658 error = sysctl_handle_int(oidp, &temp, 0, req); 659 660 return (error); 661 } 662 663 #define AMDTEMP_ZERO_C_TO_K 2731 664 665 static int32_t 666 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 667 { 668 struct amdtemp_softc *sc = device_get_softc(dev); 669 uint32_t mask, offset, temp; 670 671 mtx_lock(&sc->sc_lock); 672 673 /* Set Sensor/Core selector. */ 674 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 675 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 676 switch (sensor) { 677 case CORE0_SENSOR1: 678 temp |= AMDTEMP_TTSR_SELSENSOR; 679 /* FALLTHROUGH */ 680 case CORE0_SENSOR0: 681 case CORE0: 682 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 683 temp |= AMDTEMP_TTSR_SELCORE; 684 break; 685 case CORE1_SENSOR1: 686 temp |= AMDTEMP_TTSR_SELSENSOR; 687 /* FALLTHROUGH */ 688 case CORE1_SENSOR0: 689 case CORE1: 690 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 691 temp |= AMDTEMP_TTSR_SELCORE; 692 break; 693 default: 694 __assert_unreachable(); 695 } 696 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 697 698 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 699 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 700 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 701 temp = ((temp >> 14) & mask) * 5 / 2; 702 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 703 704 mtx_unlock(&sc->sc_lock); 705 return (temp); 706 } 707 708 static uint32_t 709 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 710 { 711 uint32_t temp; 712 713 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 714 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 715 716 if (minus49) 717 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 718 719 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 720 return (temp); 721 } 722 723 static uint32_t 724 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 725 { 726 bool minus49; 727 728 /* 729 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 730 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 731 * documented in BKDGs prior to family 15h model 00h.) 732 */ 733 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 734 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 735 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 736 737 return (amdtemp_decode_fam10h_to_17h(sc_offset, 738 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 739 } 740 741 static uint32_t 742 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 743 { 744 bool minus49; 745 746 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0) 747 || ((val & AMDTEMP_17H_CUR_TMP_TJ_SEL) == AMDTEMP_17H_CUR_TMP_TJ_SEL); 748 return (amdtemp_decode_fam10h_to_17h(sc_offset, 749 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 750 } 751 752 static int32_t 753 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 754 { 755 struct amdtemp_softc *sc = device_get_softc(dev); 756 uint32_t temp; 757 758 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 759 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 760 } 761 762 static int32_t 763 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 764 { 765 struct amdtemp_softc *sc = device_get_softc(dev); 766 uint32_t val; 767 int error __diagused; 768 769 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 770 KASSERT(error == 0, ("amdsmn_read")); 771 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 772 } 773 774 static int32_t 775 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 776 { 777 struct amdtemp_softc *sc = device_get_softc(dev); 778 uint32_t val; 779 int error __diagused; 780 781 switch (sensor) { 782 case CORE0_SENSOR0: 783 /* Tctl */ 784 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 785 KASSERT(error == 0, ("amdsmn_read")); 786 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 787 case CCD_BASE ... CCD_MAX: 788 /* Tccd<N> */ 789 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + 790 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 791 KASSERT(error == 0, ("amdsmn_read2")); 792 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 793 ("sensor %d: not valid", (int)sensor)); 794 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 795 default: 796 __assert_unreachable(); 797 } 798 } 799 800 static void 801 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg) 802 { 803 char sensor_name[16], sensor_descr[32]; 804 struct amdtemp_softc *sc; 805 uint32_t i, val; 806 int error; 807 808 sc = device_get_softc(dev); 809 for (i = 0; i < maxreg; i++) { 810 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + 811 (i * sizeof(val)), &val); 812 if (error != 0) 813 continue; 814 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 815 continue; 816 817 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 818 snprintf(sensor_descr, sizeof(sensor_descr), 819 "CCD %u temperature (Tccd%u)", i, i); 820 821 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 822 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 823 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 824 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 825 } 826 } 827 828 static void 829 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 830 { 831 uint32_t maxreg; 832 833 switch (model) { 834 case 0x00 ... 0x2f: /* Zen1, Zen+ */ 835 maxreg = 4; 836 break; 837 case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */ 838 case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */ 839 case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */ 840 maxreg = 8; 841 _Static_assert((int)NUM_CCDS >= 8, ""); 842 break; 843 default: 844 device_printf(dev, 845 "Unrecognized Family 17h Model: %02xh\n", model); 846 return; 847 } 848 849 amdtemp_probe_ccd_sensors(dev, maxreg); 850 } 851 852 static void 853 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model) 854 { 855 struct amdtemp_softc *sc = device_get_softc(dev); 856 uint32_t maxreg; 857 858 switch (model) { 859 case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */ 860 case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */ 861 maxreg = 8; 862 _Static_assert((int)NUM_CCDS >= 8, ""); 863 break; 864 case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */ 865 sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE; 866 maxreg = 8; 867 _Static_assert((int)NUM_CCDS >= 8, ""); 868 break; 869 default: 870 device_printf(dev, 871 "Unrecognized Family 19h Model: %02xh\n", model); 872 return; 873 } 874 875 amdtemp_probe_ccd_sensors(dev, maxreg); 876 } 877