1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <[email protected]> 5 * Copyright (c) 2009 Norikatsu Shigemura <[email protected]> 6 * Copyright (c) 2009-2012 Jung-uk Kim <[email protected]> 7 * All rights reserved. 8 * Copyright (c) 2017-2020 Conrad Meyer <[email protected]>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the AMD CPU on-die thermal sensors. 34 * Initially based on the k8temp Linux driver. 35 */ 36 37 #include <sys/cdefs.h> 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/sysctl.h> 46 #include <sys/systm.h> 47 48 #include <machine/cpufunc.h> 49 #include <machine/md_var.h> 50 #include <machine/specialreg.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <x86/pci_cfgreg.h> 54 55 #include <dev/amdsmn/amdsmn.h> 56 57 typedef enum { 58 CORE0_SENSOR0, 59 CORE0_SENSOR1, 60 CORE1_SENSOR0, 61 CORE1_SENSOR1, 62 CORE0, 63 CORE1, 64 CCD1, 65 CCD_BASE = CCD1, 66 CCD2, 67 CCD3, 68 CCD4, 69 CCD5, 70 CCD6, 71 CCD7, 72 CCD8, 73 CCD9, 74 CCD10, 75 CCD11, 76 CCD12, 77 CCD_MAX = CCD12, 78 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 79 } amdsensor_t; 80 81 struct amdtemp_softc { 82 int sc_ncores; 83 int sc_ntemps; 84 int sc_flags; 85 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 86 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 87 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 88 int32_t sc_offset; 89 int32_t sc_temp_base; 90 int32_t (*sc_gettemp)(device_t, amdsensor_t); 91 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 92 struct intr_config_hook sc_ich; 93 device_t sc_smn; 94 struct mtx sc_lock; 95 }; 96 97 /* 98 * N.B. The numbers in macro names below are significant and represent CPU 99 * family and model numbers. Do not make up fictitious family or model numbers 100 * when adding support for new devices. 101 */ 102 #define VENDORID_AMD 0x1022 103 #define DEVICEID_AMD_MISC0F 0x1103 104 #define DEVICEID_AMD_MISC10 0x1203 105 #define DEVICEID_AMD_MISC11 0x1303 106 #define DEVICEID_AMD_MISC14 0x1703 107 #define DEVICEID_AMD_MISC15 0x1603 108 #define DEVICEID_AMD_MISC15_M10H 0x1403 109 #define DEVICEID_AMD_MISC15_M30H 0x141d 110 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 111 #define DEVICEID_AMD_MISC16 0x1533 112 #define DEVICEID_AMD_MISC16_M30H 0x1583 113 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 114 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 115 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */ 116 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630 117 #define DEVICEID_AMD_HOSTB19H_M10H_ROOT 0x14a4 118 #define DEVICEID_AMD_HOSTB19H_M60H_ROOT 0x14d8 119 #define DEVICEID_AMD_HOSTB19H_M70H_ROOT 0x14e8 120 121 static const struct amdtemp_product { 122 uint16_t amdtemp_vendorid; 123 uint16_t amdtemp_deviceid; 124 /* 125 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 126 * drivers do not attach to that device. 127 */ 128 bool amdtemp_has_cpuid; 129 } amdtemp_products[] = { 130 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 131 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 132 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 133 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 134 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 135 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 136 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 137 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 138 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 139 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 140 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 141 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 142 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 143 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false }, 144 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M10H_ROOT, false }, 145 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M60H_ROOT, false }, 146 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M70H_ROOT, false }, 147 }; 148 149 /* 150 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 151 */ 152 #define AMDTEMP_REPTMP_CTRL 0xa4 153 154 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 155 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 156 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 157 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 158 159 /* 160 * Reported Temperature, Family 15h, M60+ 161 * 162 * Same register bit definitions as other Family 15h CPUs, but access is 163 * indirect via SMN, like Family 17h. 164 */ 165 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 166 167 /* 168 * Reported Temperature, Family 17h 169 * 170 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 171 * provide the current temp. bit 19, when clear, means the temp is reported in 172 * a range 0.."225C" (probable typo for 255C), and when set changes the range 173 * to -49..206C. 174 */ 175 #define AMDTEMP_17H_CUR_TMP 0x59800 176 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 177 /* 178 * Bits 16-17, when set, mean that CUR_TMP is read-write. When it is, the 179 * 49 degree offset should apply as well. This was revealed in a Linux 180 * patch from an AMD employee. 181 */ 182 #define AMDTEMP_17H_CUR_TMP_TJ_SEL ((1u << 17) | (1u << 16)) 183 /* 184 * The following register set was discovered experimentally by Ondrej Čerman 185 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 186 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 187 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 188 */ 189 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 190 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 191 192 #define AMDTEMP_ZEN4_10H_CCD_TMP_BASE 0x59b00 193 #define AMDTEMP_ZEN4_CCD_TMP_BASE 0x59b08 194 195 /* 196 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 197 */ 198 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 199 200 /* 201 * Thermaltrip Status Register (Family 0Fh only) 202 */ 203 #define AMDTEMP_THERMTP_STAT 0xe4 204 #define AMDTEMP_TTSR_SELCORE 0x04 205 #define AMDTEMP_TTSR_SELSENSOR 0x40 206 207 /* 208 * DRAM Configuration High Register 209 */ 210 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 211 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 212 213 /* 214 * CPU Family/Model Register 215 */ 216 #define AMDTEMP_CPUID 0xfc 217 218 /* 219 * Device methods. 220 */ 221 static void amdtemp_identify(driver_t *driver, device_t parent); 222 static int amdtemp_probe(device_t dev); 223 static int amdtemp_attach(device_t dev); 224 static void amdtemp_intrhook(void *arg); 225 static int amdtemp_detach(device_t dev); 226 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 227 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 228 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 229 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 230 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 231 static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model); 232 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 233 234 static device_method_t amdtemp_methods[] = { 235 /* Device interface */ 236 DEVMETHOD(device_identify, amdtemp_identify), 237 DEVMETHOD(device_probe, amdtemp_probe), 238 DEVMETHOD(device_attach, amdtemp_attach), 239 DEVMETHOD(device_detach, amdtemp_detach), 240 241 DEVMETHOD_END 242 }; 243 244 static driver_t amdtemp_driver = { 245 "amdtemp", 246 amdtemp_methods, 247 sizeof(struct amdtemp_softc), 248 }; 249 250 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, NULL, NULL); 251 MODULE_VERSION(amdtemp, 1); 252 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 253 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 254 nitems(amdtemp_products)); 255 256 static bool 257 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 258 { 259 int i; 260 uint16_t vendor, devid; 261 262 vendor = pci_get_vendor(dev); 263 devid = pci_get_device(dev); 264 265 for (i = 0; i < nitems(amdtemp_products); i++) { 266 if (vendor == amdtemp_products[i].amdtemp_vendorid && 267 devid == amdtemp_products[i].amdtemp_deviceid) { 268 if (product_out != NULL) 269 *product_out = &amdtemp_products[i]; 270 return (true); 271 } 272 } 273 return (false); 274 } 275 276 static void 277 amdtemp_identify(driver_t *driver, device_t parent) 278 { 279 device_t child; 280 281 /* Make sure we're not being doubly invoked. */ 282 if (device_find_child(parent, "amdtemp", -1) != NULL) 283 return; 284 285 if (amdtemp_match(parent, NULL)) { 286 child = device_add_child(parent, "amdtemp", -1); 287 if (child == NULL) 288 device_printf(parent, "add amdtemp child failed\n"); 289 } 290 } 291 292 static int 293 amdtemp_probe(device_t dev) 294 { 295 uint32_t family, model; 296 297 if (resource_disabled("amdtemp", 0)) 298 return (ENXIO); 299 if (!amdtemp_match(device_get_parent(dev), NULL)) 300 return (ENXIO); 301 302 family = CPUID_TO_FAMILY(cpu_id); 303 model = CPUID_TO_MODEL(cpu_id); 304 305 switch (family) { 306 case 0x0f: 307 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 308 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 309 return (ENXIO); 310 break; 311 case 0x10: 312 case 0x11: 313 case 0x12: 314 case 0x14: 315 case 0x15: 316 case 0x16: 317 case 0x17: 318 case 0x19: 319 break; 320 default: 321 return (ENXIO); 322 } 323 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 324 325 return (BUS_PROBE_GENERIC); 326 } 327 328 static int 329 amdtemp_attach(device_t dev) 330 { 331 char tn[32]; 332 u_int regs[4]; 333 const struct amdtemp_product *product; 334 struct amdtemp_softc *sc; 335 struct sysctl_ctx_list *sysctlctx; 336 struct sysctl_oid *sysctlnode; 337 uint32_t cpuid, family, model; 338 u_int bid; 339 int erratum319, unit; 340 bool needsmn; 341 342 sc = device_get_softc(dev); 343 erratum319 = 0; 344 needsmn = false; 345 346 if (!amdtemp_match(device_get_parent(dev), &product)) 347 return (ENXIO); 348 349 cpuid = cpu_id; 350 family = CPUID_TO_FAMILY(cpuid); 351 model = CPUID_TO_MODEL(cpuid); 352 353 /* 354 * This checks for the byzantine condition of running a heterogenous 355 * revision multi-socket system where the attach thread is potentially 356 * probing a remote socket's PCI device. 357 * 358 * Currently, such scenarios are unsupported on models using the SMN 359 * (because on those models, amdtemp(4) attaches to a different PCI 360 * device than the one that contains AMDTEMP_CPUID). 361 * 362 * The ancient 0x0F family of devices only supports this register from 363 * models 40h+. 364 */ 365 if (product->amdtemp_has_cpuid && (family > 0x0f || 366 (family == 0x0f && model >= 0x40))) { 367 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 368 4); 369 family = CPUID_TO_FAMILY(cpuid); 370 model = CPUID_TO_MODEL(cpuid); 371 } 372 373 switch (family) { 374 case 0x0f: 375 /* 376 * Thermaltrip Status Register 377 * 378 * - ThermSenseCoreSel 379 * 380 * Revision F & G: 0 - Core1, 1 - Core0 381 * Other: 0 - Core0, 1 - Core1 382 * 383 * - CurTmp 384 * 385 * Revision G: bits 23-14 386 * Other: bits 23-16 387 * 388 * XXX According to the BKDG, CurTmp, ThermSenseSel and 389 * ThermSenseCoreSel bits were introduced in Revision F 390 * but CurTmp seems working fine as early as Revision C. 391 * However, it is not clear whether ThermSenseSel and/or 392 * ThermSenseCoreSel work in undocumented cases as well. 393 * In fact, the Linux driver suggests it may not work but 394 * we just assume it does until we find otherwise. 395 * 396 * XXX According to Linux, CurTmp starts at -28C on 397 * Socket AM2 Revision G processors, which is not 398 * documented anywhere. 399 */ 400 if (model >= 0x40) 401 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 402 if (model >= 0x60 && model != 0xc1) { 403 do_cpuid(0x80000001, regs); 404 bid = (regs[1] >> 9) & 0x1f; 405 switch (model) { 406 case 0x68: /* Socket S1g1 */ 407 case 0x6c: 408 case 0x7c: 409 break; 410 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 411 if (bid != 0x0b && bid != 0x0c) 412 sc->sc_flags |= 413 AMDTEMP_FLAG_ALT_OFFSET; 414 break; 415 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 416 case 0x7f: 417 if (bid != 0x07 && bid != 0x09 && 418 bid != 0x0c) 419 sc->sc_flags |= 420 AMDTEMP_FLAG_ALT_OFFSET; 421 break; 422 default: 423 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 424 } 425 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 426 } 427 428 /* 429 * There are two sensors per core. 430 */ 431 sc->sc_ntemps = 2; 432 433 sc->sc_gettemp = amdtemp_gettemp0f; 434 break; 435 case 0x10: 436 /* 437 * Erratum 319 Inaccurate Temperature Measurement 438 * 439 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 440 */ 441 do_cpuid(0x80000001, regs); 442 switch ((regs[1] >> 28) & 0xf) { 443 case 0: /* Socket F */ 444 erratum319 = 1; 445 break; 446 case 1: /* Socket AM2+ or AM3 */ 447 if ((pci_cfgregread(pci_get_domain(dev), 448 pci_get_bus(dev), pci_get_slot(dev), 2, 449 AMDTEMP_DRAM_CONF_HIGH, 2) & 450 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 451 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 452 break; 453 /* XXX 00100F42h (RB-C2) exists in both formats. */ 454 erratum319 = 1; 455 break; 456 } 457 /* FALLTHROUGH */ 458 case 0x11: 459 case 0x12: 460 case 0x14: 461 case 0x15: 462 case 0x16: 463 sc->sc_ntemps = 1; 464 /* 465 * Some later (60h+) models of family 15h use a similar SMN 466 * network as family 17h. (However, the register index differs 467 * from 17h and the decoding matches other 10h-15h models, 468 * which differ from 17h.) 469 */ 470 if (family == 0x15 && model >= 0x60) { 471 sc->sc_gettemp = amdtemp_gettemp15hm60h; 472 needsmn = true; 473 } else 474 sc->sc_gettemp = amdtemp_gettemp; 475 break; 476 case 0x17: 477 case 0x19: 478 sc->sc_ntemps = 1; 479 sc->sc_gettemp = amdtemp_gettemp17h; 480 needsmn = true; 481 break; 482 default: 483 device_printf(dev, "Bogus family 0x%x\n", family); 484 return (ENXIO); 485 } 486 487 if (needsmn) { 488 sc->sc_smn = device_find_child( 489 device_get_parent(dev), "amdsmn", -1); 490 if (sc->sc_smn == NULL) { 491 if (bootverbose) 492 device_printf(dev, "No SMN device found\n"); 493 return (ENXIO); 494 } 495 } 496 497 /* Find number of cores per package. */ 498 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 499 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 500 if (sc->sc_ncores > MAXCPU) 501 return (ENXIO); 502 503 mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF); 504 if (erratum319) 505 device_printf(dev, 506 "Erratum 319: temperature measurement may be inaccurate\n"); 507 if (bootverbose) 508 device_printf(dev, "Found %d cores and %d sensors.\n", 509 sc->sc_ncores, 510 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 511 512 /* 513 * dev.amdtemp.N tree. 514 */ 515 unit = device_get_unit(dev); 516 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 517 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 518 519 sysctlctx = device_get_sysctl_ctx(dev); 520 SYSCTL_ADD_INT(sysctlctx, 521 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 522 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 523 "Temperature sensor offset"); 524 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 525 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 526 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0"); 527 528 SYSCTL_ADD_PROC(sysctlctx, 529 SYSCTL_CHILDREN(sysctlnode), 530 OID_AUTO, "sensor0", 531 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 532 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 533 "Core 0 / Sensor 0 temperature"); 534 535 sc->sc_temp_base = AMDTEMP_17H_CCD_TMP_BASE; 536 537 if (family == 0x17) 538 amdtemp_probe_ccd_sensors17h(dev, model); 539 else if (family == 0x19) 540 amdtemp_probe_ccd_sensors19h(dev, model); 541 else if (sc->sc_ntemps > 1) { 542 SYSCTL_ADD_PROC(sysctlctx, 543 SYSCTL_CHILDREN(sysctlnode), 544 OID_AUTO, "sensor1", 545 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 546 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 547 "Core 0 / Sensor 1 temperature"); 548 549 if (sc->sc_ncores > 1) { 550 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 551 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 552 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE, 553 0, "Core 1"); 554 555 SYSCTL_ADD_PROC(sysctlctx, 556 SYSCTL_CHILDREN(sysctlnode), 557 OID_AUTO, "sensor0", 558 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 559 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 560 "Core 1 / Sensor 0 temperature"); 561 562 SYSCTL_ADD_PROC(sysctlctx, 563 SYSCTL_CHILDREN(sysctlnode), 564 OID_AUTO, "sensor1", 565 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 566 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 567 "Core 1 / Sensor 1 temperature"); 568 } 569 } 570 571 /* 572 * Try to create dev.cpu sysctl entries and setup intrhook function. 573 * This is needed because the cpu driver may be loaded late on boot, 574 * after us. 575 */ 576 amdtemp_intrhook(dev); 577 sc->sc_ich.ich_func = amdtemp_intrhook; 578 sc->sc_ich.ich_arg = dev; 579 if (config_intrhook_establish(&sc->sc_ich) != 0) { 580 device_printf(dev, "config_intrhook_establish failed!\n"); 581 return (ENXIO); 582 } 583 584 return (0); 585 } 586 587 void 588 amdtemp_intrhook(void *arg) 589 { 590 struct amdtemp_softc *sc; 591 struct sysctl_ctx_list *sysctlctx; 592 device_t dev = (device_t)arg; 593 device_t acpi, cpu, nexus; 594 amdsensor_t sensor; 595 int i; 596 597 sc = device_get_softc(dev); 598 599 /* 600 * dev.cpu.N.temperature. 601 */ 602 nexus = device_find_child(root_bus, "nexus", 0); 603 acpi = device_find_child(nexus, "acpi", 0); 604 605 for (i = 0; i < sc->sc_ncores; i++) { 606 if (sc->sc_sysctl_cpu[i] != NULL) 607 continue; 608 cpu = device_find_child(acpi, "cpu", 609 device_get_unit(dev) * sc->sc_ncores + i); 610 if (cpu != NULL) { 611 sysctlctx = device_get_sysctl_ctx(cpu); 612 613 sensor = sc->sc_ntemps > 1 ? 614 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 615 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 616 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 617 OID_AUTO, "temperature", 618 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 619 dev, sensor, amdtemp_sysctl, "IK", 620 "Current temparature"); 621 } 622 } 623 if (sc->sc_ich.ich_arg != NULL) 624 config_intrhook_disestablish(&sc->sc_ich); 625 } 626 627 int 628 amdtemp_detach(device_t dev) 629 { 630 struct amdtemp_softc *sc = device_get_softc(dev); 631 int i; 632 633 for (i = 0; i < sc->sc_ncores; i++) 634 if (sc->sc_sysctl_cpu[i] != NULL) 635 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 636 637 /* NewBus removes the dev.amdtemp.N tree by itself. */ 638 639 mtx_destroy(&sc->sc_lock); 640 return (0); 641 } 642 643 static int 644 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 645 { 646 device_t dev = (device_t)arg1; 647 struct amdtemp_softc *sc = device_get_softc(dev); 648 amdsensor_t sensor = (amdsensor_t)arg2; 649 int32_t auxtemp[2], temp; 650 int error; 651 652 switch (sensor) { 653 case CORE0: 654 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 655 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 656 temp = imax(auxtemp[0], auxtemp[1]); 657 break; 658 case CORE1: 659 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 660 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 661 temp = imax(auxtemp[0], auxtemp[1]); 662 break; 663 default: 664 temp = sc->sc_gettemp(dev, sensor); 665 break; 666 } 667 error = sysctl_handle_int(oidp, &temp, 0, req); 668 669 return (error); 670 } 671 672 #define AMDTEMP_ZERO_C_TO_K 2731 673 674 static int32_t 675 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 676 { 677 struct amdtemp_softc *sc = device_get_softc(dev); 678 uint32_t mask, offset, temp; 679 680 mtx_lock(&sc->sc_lock); 681 682 /* Set Sensor/Core selector. */ 683 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 684 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 685 switch (sensor) { 686 case CORE0_SENSOR1: 687 temp |= AMDTEMP_TTSR_SELSENSOR; 688 /* FALLTHROUGH */ 689 case CORE0_SENSOR0: 690 case CORE0: 691 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 692 temp |= AMDTEMP_TTSR_SELCORE; 693 break; 694 case CORE1_SENSOR1: 695 temp |= AMDTEMP_TTSR_SELSENSOR; 696 /* FALLTHROUGH */ 697 case CORE1_SENSOR0: 698 case CORE1: 699 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 700 temp |= AMDTEMP_TTSR_SELCORE; 701 break; 702 default: 703 __assert_unreachable(); 704 } 705 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 706 707 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 708 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 709 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 710 temp = ((temp >> 14) & mask) * 5 / 2; 711 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 712 713 mtx_unlock(&sc->sc_lock); 714 return (temp); 715 } 716 717 static uint32_t 718 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 719 { 720 uint32_t temp; 721 722 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 723 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 724 725 if (minus49) 726 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 727 728 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 729 return (temp); 730 } 731 732 static uint32_t 733 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 734 { 735 bool minus49; 736 737 /* 738 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 739 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 740 * documented in BKDGs prior to family 15h model 00h.) 741 */ 742 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 743 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 744 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 745 746 return (amdtemp_decode_fam10h_to_17h(sc_offset, 747 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 748 } 749 750 static uint32_t 751 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 752 { 753 bool minus49; 754 755 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0) 756 || ((val & AMDTEMP_17H_CUR_TMP_TJ_SEL) == AMDTEMP_17H_CUR_TMP_TJ_SEL); 757 return (amdtemp_decode_fam10h_to_17h(sc_offset, 758 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 759 } 760 761 static int32_t 762 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 763 { 764 struct amdtemp_softc *sc = device_get_softc(dev); 765 uint32_t temp; 766 767 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 768 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 769 } 770 771 static int32_t 772 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 773 { 774 struct amdtemp_softc *sc = device_get_softc(dev); 775 uint32_t val; 776 int error __diagused; 777 778 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 779 KASSERT(error == 0, ("amdsmn_read")); 780 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 781 } 782 783 static int32_t 784 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 785 { 786 struct amdtemp_softc *sc = device_get_softc(dev); 787 uint32_t val; 788 int error __diagused; 789 790 switch (sensor) { 791 case CORE0_SENSOR0: 792 /* Tctl */ 793 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 794 KASSERT(error == 0, ("amdsmn_read")); 795 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 796 case CCD_BASE ... CCD_MAX: 797 /* Tccd<N> */ 798 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + 799 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 800 KASSERT(error == 0, ("amdsmn_read2")); 801 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 802 ("sensor %d: not valid", (int)sensor)); 803 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 804 default: 805 __assert_unreachable(); 806 } 807 } 808 809 static void 810 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg) 811 { 812 char sensor_name[16], sensor_descr[32]; 813 struct amdtemp_softc *sc; 814 uint32_t i, val; 815 int error; 816 817 sc = device_get_softc(dev); 818 for (i = 0; i < maxreg; i++) { 819 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + 820 (i * sizeof(val)), &val); 821 if (error != 0) 822 continue; 823 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 824 continue; 825 826 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 827 snprintf(sensor_descr, sizeof(sensor_descr), 828 "CCD %u temperature (Tccd%u)", i, i); 829 830 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 831 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 832 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 833 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 834 } 835 } 836 837 static void 838 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 839 { 840 uint32_t maxreg; 841 842 switch (model) { 843 case 0x00 ... 0x2f: /* Zen1, Zen+ */ 844 maxreg = 4; 845 break; 846 case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */ 847 case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */ 848 case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */ 849 maxreg = 8; 850 _Static_assert((int)NUM_CCDS >= 8, ""); 851 break; 852 default: 853 device_printf(dev, 854 "Unrecognized Family 17h Model: %02xh\n", model); 855 return; 856 } 857 858 amdtemp_probe_ccd_sensors(dev, maxreg); 859 } 860 861 static void 862 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model) 863 { 864 struct amdtemp_softc *sc = device_get_softc(dev); 865 uint32_t maxreg; 866 867 switch (model) { 868 case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */ 869 case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */ 870 maxreg = 8; 871 _Static_assert((int)NUM_CCDS >= 8, ""); 872 break; 873 case 0x10 ... 0x1f: 874 sc->sc_temp_base = AMDTEMP_ZEN4_10H_CCD_TMP_BASE; 875 maxreg = 12; 876 _Static_assert((int)NUM_CCDS >= 12, ""); 877 break; 878 case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */ 879 case 0x70 ... 0x7f: /* Zen4 Ryzen "Phoenix" */ 880 sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE; 881 maxreg = 8; 882 _Static_assert((int)NUM_CCDS >= 8, ""); 883 break; 884 default: 885 device_printf(dev, 886 "Unrecognized Family 19h Model: %02xh\n", model); 887 return; 888 } 889 890 amdtemp_probe_ccd_sensors(dev, maxreg); 891 } 892