1 /*- 2 * Copyright (c) 2017-2020 Conrad Meyer <[email protected]> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Driver for the AMD Family 15h and 17h CPU System Management Network. 29 */ 30 31 #include <sys/cdefs.h> 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/lock.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/mutex.h> 39 #include <sys/sysctl.h> 40 #include <sys/systm.h> 41 42 #include <machine/cpufunc.h> 43 #include <machine/cputypes.h> 44 #include <machine/md_var.h> 45 #include <machine/specialreg.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <x86/pci_cfgreg.h> 49 50 #include <dev/amdsmn/amdsmn.h> 51 52 #define F15H_SMN_ADDR_REG 0xb8 53 #define F15H_SMN_DATA_REG 0xbc 54 #define F17H_SMN_ADDR_REG 0x60 55 #define F17H_SMN_DATA_REG 0x64 56 57 #define PCI_DEVICE_ID_AMD_15H_M60H_ROOT 0x1576 58 #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450 59 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0 60 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */ 61 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630 62 #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4 63 #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8 64 #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8 65 66 struct pciid; 67 struct amdsmn_softc { 68 struct mtx smn_lock; 69 const struct pciid *smn_pciid; 70 }; 71 72 static const struct pciid { 73 uint16_t amdsmn_vendorid; 74 uint16_t amdsmn_deviceid; 75 uint8_t amdsmn_addr_reg; 76 uint8_t amdsmn_data_reg; 77 } amdsmn_ids[] = { 78 { 79 .amdsmn_vendorid = CPU_VENDOR_AMD, 80 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_15H_M60H_ROOT, 81 .amdsmn_addr_reg = F15H_SMN_ADDR_REG, 82 .amdsmn_data_reg = F15H_SMN_DATA_REG, 83 }, 84 { 85 .amdsmn_vendorid = CPU_VENDOR_AMD, 86 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_ROOT, 87 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 88 .amdsmn_data_reg = F17H_SMN_DATA_REG, 89 }, 90 { 91 .amdsmn_vendorid = CPU_VENDOR_AMD, 92 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M10H_ROOT, 93 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 94 .amdsmn_data_reg = F17H_SMN_DATA_REG, 95 }, 96 { 97 .amdsmn_vendorid = CPU_VENDOR_AMD, 98 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M30H_ROOT, 99 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 100 .amdsmn_data_reg = F17H_SMN_DATA_REG, 101 }, 102 { 103 .amdsmn_vendorid = CPU_VENDOR_AMD, 104 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M60H_ROOT, 105 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 106 .amdsmn_data_reg = F17H_SMN_DATA_REG, 107 }, 108 { 109 .amdsmn_vendorid = CPU_VENDOR_AMD, 110 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M10H_ROOT, 111 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 112 .amdsmn_data_reg = F17H_SMN_DATA_REG, 113 }, 114 { 115 .amdsmn_vendorid = CPU_VENDOR_AMD, 116 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M60H_ROOT, 117 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 118 .amdsmn_data_reg = F17H_SMN_DATA_REG, 119 }, 120 { 121 .amdsmn_vendorid = CPU_VENDOR_AMD, 122 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M70H_ROOT, 123 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 124 .amdsmn_data_reg = F17H_SMN_DATA_REG, 125 }, 126 }; 127 128 /* 129 * Device methods. 130 */ 131 static void amdsmn_identify(driver_t *driver, device_t parent); 132 static int amdsmn_probe(device_t dev); 133 static int amdsmn_attach(device_t dev); 134 static int amdsmn_detach(device_t dev); 135 136 static device_method_t amdsmn_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_identify, amdsmn_identify), 139 DEVMETHOD(device_probe, amdsmn_probe), 140 DEVMETHOD(device_attach, amdsmn_attach), 141 DEVMETHOD(device_detach, amdsmn_detach), 142 DEVMETHOD_END 143 }; 144 145 static driver_t amdsmn_driver = { 146 "amdsmn", 147 amdsmn_methods, 148 sizeof(struct amdsmn_softc), 149 }; 150 151 DRIVER_MODULE(amdsmn, hostb, amdsmn_driver, NULL, NULL); 152 MODULE_VERSION(amdsmn, 1); 153 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdsmn, amdsmn_ids, 154 nitems(amdsmn_ids)); 155 156 static bool 157 amdsmn_match(device_t parent, const struct pciid **pciid_out) 158 { 159 uint16_t vendor, device; 160 size_t i; 161 162 vendor = pci_get_vendor(parent); 163 device = pci_get_device(parent); 164 165 for (i = 0; i < nitems(amdsmn_ids); i++) { 166 if (vendor == amdsmn_ids[i].amdsmn_vendorid && 167 device == amdsmn_ids[i].amdsmn_deviceid) { 168 if (pciid_out != NULL) 169 *pciid_out = &amdsmn_ids[i]; 170 return (true); 171 } 172 } 173 return (false); 174 } 175 176 static void 177 amdsmn_identify(driver_t *driver, device_t parent) 178 { 179 device_t child; 180 181 /* Make sure we're not being doubly invoked. */ 182 if (device_find_child(parent, "amdsmn", -1) != NULL) 183 return; 184 if (!amdsmn_match(parent, NULL)) 185 return; 186 187 child = device_add_child(parent, "amdsmn", -1); 188 if (child == NULL) 189 device_printf(parent, "add amdsmn child failed\n"); 190 } 191 192 static int 193 amdsmn_probe(device_t dev) 194 { 195 uint32_t family; 196 197 if (resource_disabled("amdsmn", 0)) 198 return (ENXIO); 199 if (!amdsmn_match(device_get_parent(dev), NULL)) 200 return (ENXIO); 201 202 family = CPUID_TO_FAMILY(cpu_id); 203 204 switch (family) { 205 case 0x15: 206 case 0x17: 207 case 0x19: 208 break; 209 default: 210 return (ENXIO); 211 } 212 device_set_descf(dev, "AMD Family %xh System Management Network", 213 family); 214 215 return (BUS_PROBE_GENERIC); 216 } 217 218 static int 219 amdsmn_attach(device_t dev) 220 { 221 struct amdsmn_softc *sc = device_get_softc(dev); 222 223 if (!amdsmn_match(device_get_parent(dev), &sc->smn_pciid)) 224 return (ENXIO); 225 226 mtx_init(&sc->smn_lock, "SMN mtx", "SMN", MTX_DEF); 227 return (0); 228 } 229 230 int 231 amdsmn_detach(device_t dev) 232 { 233 struct amdsmn_softc *sc = device_get_softc(dev); 234 235 mtx_destroy(&sc->smn_lock); 236 return (0); 237 } 238 239 int 240 amdsmn_read(device_t dev, uint32_t addr, uint32_t *value) 241 { 242 struct amdsmn_softc *sc = device_get_softc(dev); 243 device_t parent; 244 245 parent = device_get_parent(dev); 246 247 mtx_lock(&sc->smn_lock); 248 pci_write_config(parent, sc->smn_pciid->amdsmn_addr_reg, addr, 4); 249 *value = pci_read_config(parent, sc->smn_pciid->amdsmn_data_reg, 4); 250 mtx_unlock(&sc->smn_lock); 251 252 return (0); 253 } 254 255 int 256 amdsmn_write(device_t dev, uint32_t addr, uint32_t value) 257 { 258 struct amdsmn_softc *sc = device_get_softc(dev); 259 device_t parent; 260 261 parent = device_get_parent(dev); 262 263 mtx_lock(&sc->smn_lock); 264 pci_write_config(parent, sc->smn_pciid->amdsmn_addr_reg, addr, 4); 265 pci_write_config(parent, sc->smn_pciid->amdsmn_data_reg, value, 4); 266 mtx_unlock(&sc->smn_lock); 267 268 return (0); 269 } 270