1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <[email protected]> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/rman.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_llc.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/if_vlan_var.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/ip.h> 62 #include <netinet/tcp.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #include <machine/bus.h> 71 #include <machine/in_cksum.h> 72 73 #include <dev/ale/if_alereg.h> 74 #include <dev/ale/if_alevar.h> 75 76 /* "device miibus" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 /* For more information about Tx checksum offload issues see ale_encap(). */ 80 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 82 MODULE_DEPEND(ale, pci, 1, 1, 1); 83 MODULE_DEPEND(ale, ether, 1, 1, 1); 84 MODULE_DEPEND(ale, miibus, 1, 1, 1); 85 86 /* Tunables. */ 87 static int msi_disable = 0; 88 static int msix_disable = 0; 89 TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 90 TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 91 92 /* 93 * Devices supported by this driver. 94 */ 95 static const struct ale_dev { 96 uint16_t ale_vendorid; 97 uint16_t ale_deviceid; 98 const char *ale_name; 99 } ale_devs[] = { 100 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 101 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 102 }; 103 104 static int ale_attach(device_t); 105 static int ale_check_boundary(struct ale_softc *); 106 static int ale_detach(device_t); 107 static int ale_dma_alloc(struct ale_softc *); 108 static void ale_dma_free(struct ale_softc *); 109 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 110 static int ale_encap(struct ale_softc *, struct mbuf **); 111 static void ale_get_macaddr(struct ale_softc *); 112 static void ale_init(void *); 113 static void ale_init_locked(struct ale_softc *); 114 static void ale_init_rx_pages(struct ale_softc *); 115 static void ale_init_tx_ring(struct ale_softc *); 116 static void ale_int_task(void *, int); 117 static int ale_intr(void *); 118 static int ale_ioctl(if_t, u_long, caddr_t); 119 static void ale_mac_config(struct ale_softc *); 120 static int ale_miibus_readreg(device_t, int, int); 121 static void ale_miibus_statchg(device_t); 122 static int ale_miibus_writereg(device_t, int, int, int); 123 static int ale_mediachange(if_t); 124 static void ale_mediastatus(if_t, struct ifmediareq *); 125 static void ale_phy_reset(struct ale_softc *); 126 static int ale_probe(device_t); 127 static void ale_reset(struct ale_softc *); 128 static int ale_resume(device_t); 129 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 130 uint32_t, uint32_t *); 131 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 132 static int ale_rxeof(struct ale_softc *sc, int); 133 static void ale_rxfilter(struct ale_softc *); 134 static void ale_rxvlan(struct ale_softc *); 135 static void ale_setlinkspeed(struct ale_softc *); 136 static void ale_setwol(struct ale_softc *); 137 static int ale_shutdown(device_t); 138 static void ale_start(if_t); 139 static void ale_start_locked(if_t); 140 static void ale_stats_clear(struct ale_softc *); 141 static void ale_stats_update(struct ale_softc *); 142 static void ale_stop(struct ale_softc *); 143 static void ale_stop_mac(struct ale_softc *); 144 static int ale_suspend(device_t); 145 static void ale_sysctl_node(struct ale_softc *); 146 static void ale_tick(void *); 147 static void ale_txeof(struct ale_softc *); 148 static void ale_watchdog(struct ale_softc *); 149 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 151 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 152 153 static device_method_t ale_methods[] = { 154 /* Device interface. */ 155 DEVMETHOD(device_probe, ale_probe), 156 DEVMETHOD(device_attach, ale_attach), 157 DEVMETHOD(device_detach, ale_detach), 158 DEVMETHOD(device_shutdown, ale_shutdown), 159 DEVMETHOD(device_suspend, ale_suspend), 160 DEVMETHOD(device_resume, ale_resume), 161 162 /* MII interface. */ 163 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 164 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 165 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 166 167 DEVMETHOD_END 168 }; 169 170 static driver_t ale_driver = { 171 "ale", 172 ale_methods, 173 sizeof(struct ale_softc) 174 }; 175 176 DRIVER_MODULE(ale, pci, ale_driver, NULL, NULL); 177 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs, 178 nitems(ale_devs)); 179 DRIVER_MODULE(miibus, ale, miibus_driver, NULL, NULL); 180 181 static struct resource_spec ale_res_spec_mem[] = { 182 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 183 { -1, 0, 0 } 184 }; 185 186 static struct resource_spec ale_irq_spec_legacy[] = { 187 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 188 { -1, 0, 0 } 189 }; 190 191 static struct resource_spec ale_irq_spec_msi[] = { 192 { SYS_RES_IRQ, 1, RF_ACTIVE }, 193 { -1, 0, 0 } 194 }; 195 196 static struct resource_spec ale_irq_spec_msix[] = { 197 { SYS_RES_IRQ, 1, RF_ACTIVE }, 198 { -1, 0, 0 } 199 }; 200 201 static int 202 ale_miibus_readreg(device_t dev, int phy, int reg) 203 { 204 struct ale_softc *sc; 205 uint32_t v; 206 int i; 207 208 sc = device_get_softc(dev); 209 210 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 211 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 212 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 213 DELAY(5); 214 v = CSR_READ_4(sc, ALE_MDIO); 215 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 216 break; 217 } 218 219 if (i == 0) { 220 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 221 return (0); 222 } 223 224 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 225 } 226 227 static int 228 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 229 { 230 struct ale_softc *sc; 231 uint32_t v; 232 int i; 233 234 sc = device_get_softc(dev); 235 236 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 237 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 238 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 239 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 240 DELAY(5); 241 v = CSR_READ_4(sc, ALE_MDIO); 242 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 243 break; 244 } 245 246 if (i == 0) 247 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 248 249 return (0); 250 } 251 252 static void 253 ale_miibus_statchg(device_t dev) 254 { 255 struct ale_softc *sc; 256 struct mii_data *mii; 257 if_t ifp; 258 uint32_t reg; 259 260 sc = device_get_softc(dev); 261 mii = device_get_softc(sc->ale_miibus); 262 ifp = sc->ale_ifp; 263 if (mii == NULL || ifp == NULL || 264 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 265 return; 266 267 sc->ale_flags &= ~ALE_FLAG_LINK; 268 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 269 (IFM_ACTIVE | IFM_AVALID)) { 270 switch (IFM_SUBTYPE(mii->mii_media_active)) { 271 case IFM_10_T: 272 case IFM_100_TX: 273 sc->ale_flags |= ALE_FLAG_LINK; 274 break; 275 case IFM_1000_T: 276 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 277 sc->ale_flags |= ALE_FLAG_LINK; 278 break; 279 default: 280 break; 281 } 282 } 283 284 /* Stop Rx/Tx MACs. */ 285 ale_stop_mac(sc); 286 287 /* Program MACs with resolved speed/duplex/flow-control. */ 288 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 289 ale_mac_config(sc); 290 /* Reenable Tx/Rx MACs. */ 291 reg = CSR_READ_4(sc, ALE_MAC_CFG); 292 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 293 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 294 } 295 } 296 297 static void 298 ale_mediastatus(if_t ifp, struct ifmediareq *ifmr) 299 { 300 struct ale_softc *sc; 301 struct mii_data *mii; 302 303 sc = if_getsoftc(ifp); 304 ALE_LOCK(sc); 305 if ((if_getflags(ifp) & IFF_UP) == 0) { 306 ALE_UNLOCK(sc); 307 return; 308 } 309 mii = device_get_softc(sc->ale_miibus); 310 311 mii_pollstat(mii); 312 ifmr->ifm_status = mii->mii_media_status; 313 ifmr->ifm_active = mii->mii_media_active; 314 ALE_UNLOCK(sc); 315 } 316 317 static int 318 ale_mediachange(if_t ifp) 319 { 320 struct ale_softc *sc; 321 struct mii_data *mii; 322 struct mii_softc *miisc; 323 int error; 324 325 sc = if_getsoftc(ifp); 326 ALE_LOCK(sc); 327 mii = device_get_softc(sc->ale_miibus); 328 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 329 PHY_RESET(miisc); 330 error = mii_mediachg(mii); 331 ALE_UNLOCK(sc); 332 333 return (error); 334 } 335 336 static int 337 ale_probe(device_t dev) 338 { 339 const struct ale_dev *sp; 340 int i; 341 uint16_t vendor, devid; 342 343 vendor = pci_get_vendor(dev); 344 devid = pci_get_device(dev); 345 sp = ale_devs; 346 for (i = 0; i < nitems(ale_devs); i++) { 347 if (vendor == sp->ale_vendorid && 348 devid == sp->ale_deviceid) { 349 device_set_desc(dev, sp->ale_name); 350 return (BUS_PROBE_DEFAULT); 351 } 352 sp++; 353 } 354 355 return (ENXIO); 356 } 357 358 static void 359 ale_get_macaddr(struct ale_softc *sc) 360 { 361 uint32_t ea[2], reg; 362 int i, vpdc; 363 364 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 365 if ((reg & SPI_VPD_ENB) != 0) { 366 reg &= ~SPI_VPD_ENB; 367 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 368 } 369 370 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 371 /* 372 * PCI VPD capability found, let TWSI reload EEPROM. 373 * This will set ethernet address of controller. 374 */ 375 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 376 TWSI_CTRL_SW_LD_START); 377 for (i = 100; i > 0; i--) { 378 DELAY(1000); 379 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 380 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 381 break; 382 } 383 if (i == 0) 384 device_printf(sc->ale_dev, 385 "reloading EEPROM timeout!\n"); 386 } else { 387 if (bootverbose) 388 device_printf(sc->ale_dev, 389 "PCI VPD capability not found!\n"); 390 } 391 392 ea[0] = CSR_READ_4(sc, ALE_PAR0); 393 ea[1] = CSR_READ_4(sc, ALE_PAR1); 394 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 395 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 396 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 397 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 398 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 399 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 400 } 401 402 static void 403 ale_phy_reset(struct ale_softc *sc) 404 { 405 406 /* Reset magic from Linux. */ 407 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 408 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 409 GPHY_CTRL_PHY_PLL_ON); 410 DELAY(1000); 411 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 412 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 413 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 414 DELAY(1000); 415 416 #define ATPHY_DBG_ADDR 0x1D 417 #define ATPHY_DBG_DATA 0x1E 418 419 /* Enable hibernation mode. */ 420 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 421 ATPHY_DBG_ADDR, 0x0B); 422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 423 ATPHY_DBG_DATA, 0xBC00); 424 /* Set Class A/B for all modes. */ 425 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 426 ATPHY_DBG_ADDR, 0x00); 427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 428 ATPHY_DBG_DATA, 0x02EF); 429 /* Enable 10BT power saving. */ 430 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 431 ATPHY_DBG_ADDR, 0x12); 432 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 433 ATPHY_DBG_DATA, 0x4C04); 434 /* Adjust 1000T power. */ 435 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 436 ATPHY_DBG_ADDR, 0x04); 437 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 438 ATPHY_DBG_ADDR, 0x8BBB); 439 /* 10BT center tap voltage. */ 440 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 441 ATPHY_DBG_ADDR, 0x05); 442 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 443 ATPHY_DBG_ADDR, 0x2C46); 444 445 #undef ATPHY_DBG_ADDR 446 #undef ATPHY_DBG_DATA 447 DELAY(1000); 448 } 449 450 static int 451 ale_attach(device_t dev) 452 { 453 struct ale_softc *sc; 454 if_t ifp; 455 uint16_t burst; 456 int error, i, msic, msixc, pmc; 457 uint32_t rxf_len, txf_len; 458 459 error = 0; 460 sc = device_get_softc(dev); 461 sc->ale_dev = dev; 462 463 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 464 MTX_DEF); 465 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 466 NET_TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 467 468 /* Map the device. */ 469 pci_enable_busmaster(dev); 470 sc->ale_res_spec = ale_res_spec_mem; 471 sc->ale_irq_spec = ale_irq_spec_legacy; 472 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 473 if (error != 0) { 474 device_printf(dev, "cannot allocate memory resources.\n"); 475 goto fail; 476 } 477 478 /* Set PHY address. */ 479 sc->ale_phyaddr = ALE_PHY_ADDR; 480 481 /* Reset PHY. */ 482 ale_phy_reset(sc); 483 484 /* Reset the ethernet controller. */ 485 ale_reset(sc); 486 487 /* Get PCI and chip id/revision. */ 488 sc->ale_rev = pci_get_revid(dev); 489 if (sc->ale_rev >= 0xF0) { 490 /* L2E Rev. B. AR8114 */ 491 sc->ale_flags |= ALE_FLAG_FASTETHER; 492 } else { 493 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 494 /* L1E AR8121 */ 495 sc->ale_flags |= ALE_FLAG_JUMBO; 496 } else { 497 /* L2E Rev. A. AR8113 */ 498 sc->ale_flags |= ALE_FLAG_FASTETHER; 499 } 500 } 501 /* 502 * All known controllers seems to require 4 bytes alignment 503 * of Tx buffers to make Tx checksum offload with custom 504 * checksum generation method work. 505 */ 506 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 507 /* 508 * All known controllers seems to have issues on Rx checksum 509 * offload for fragmented IP datagrams. 510 */ 511 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 512 /* 513 * Don't use Tx CMB. It is known to cause RRS update failure 514 * under certain circumstances. Typical phenomenon of the 515 * issue would be unexpected sequence number encountered in 516 * Rx handler. 517 */ 518 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 519 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 520 MASTER_CHIP_REV_SHIFT; 521 if (bootverbose) { 522 device_printf(dev, "PCI device revision : 0x%04x\n", 523 sc->ale_rev); 524 device_printf(dev, "Chip id/revision : 0x%04x\n", 525 sc->ale_chip_rev); 526 } 527 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 528 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 529 /* 530 * Uninitialized hardware returns an invalid chip id/revision 531 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 532 */ 533 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 534 rxf_len == 0xFFFFFFF) { 535 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 536 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 537 txf_len, rxf_len); 538 error = ENXIO; 539 goto fail; 540 } 541 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 542 543 /* Allocate IRQ resources. */ 544 msixc = pci_msix_count(dev); 545 msic = pci_msi_count(dev); 546 if (bootverbose) { 547 device_printf(dev, "MSIX count : %d\n", msixc); 548 device_printf(dev, "MSI count : %d\n", msic); 549 } 550 551 /* Prefer MSIX over MSI. */ 552 if (msix_disable == 0 || msi_disable == 0) { 553 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 554 pci_alloc_msix(dev, &msixc) == 0) { 555 if (msixc == ALE_MSIX_MESSAGES) { 556 device_printf(dev, "Using %d MSIX messages.\n", 557 msixc); 558 sc->ale_flags |= ALE_FLAG_MSIX; 559 sc->ale_irq_spec = ale_irq_spec_msix; 560 } else 561 pci_release_msi(dev); 562 } 563 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 564 msic == ALE_MSI_MESSAGES && 565 pci_alloc_msi(dev, &msic) == 0) { 566 if (msic == ALE_MSI_MESSAGES) { 567 device_printf(dev, "Using %d MSI messages.\n", 568 msic); 569 sc->ale_flags |= ALE_FLAG_MSI; 570 sc->ale_irq_spec = ale_irq_spec_msi; 571 } else 572 pci_release_msi(dev); 573 } 574 } 575 576 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 577 if (error != 0) { 578 device_printf(dev, "cannot allocate IRQ resources.\n"); 579 goto fail; 580 } 581 582 /* Get DMA parameters from PCIe device control register. */ 583 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 584 sc->ale_flags |= ALE_FLAG_PCIE; 585 burst = pci_read_config(dev, i + 0x08, 2); 586 /* Max read request size. */ 587 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 588 DMA_CFG_RD_BURST_SHIFT; 589 /* Max payload size. */ 590 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 591 DMA_CFG_WR_BURST_SHIFT; 592 if (bootverbose) { 593 device_printf(dev, "Read request size : %d bytes.\n", 594 128 << ((burst >> 12) & 0x07)); 595 device_printf(dev, "TLP payload size : %d bytes.\n", 596 128 << ((burst >> 5) & 0x07)); 597 } 598 } else { 599 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 600 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 601 } 602 603 /* Create device sysctl node. */ 604 ale_sysctl_node(sc); 605 606 if ((error = ale_dma_alloc(sc)) != 0) 607 goto fail; 608 609 /* Load station address. */ 610 ale_get_macaddr(sc); 611 612 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 613 if_setsoftc(ifp, sc); 614 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 615 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 616 if_setioctlfn(ifp, ale_ioctl); 617 if_setstartfn(ifp, ale_start); 618 if_setinitfn(ifp, ale_init); 619 if_setsendqlen(ifp, ALE_TX_RING_CNT - 1); 620 if_setsendqready(ifp); 621 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4); 622 if_sethwassist(ifp, ALE_CSUM_FEATURES | CSUM_TSO); 623 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 624 sc->ale_flags |= ALE_FLAG_PMCAP; 625 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 626 } 627 if_setcapenable(ifp, if_getcapabilities(ifp)); 628 629 /* Set up MII bus. */ 630 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 631 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 632 MIIF_DOPAUSE); 633 if (error != 0) { 634 device_printf(dev, "attaching PHYs failed\n"); 635 goto fail; 636 } 637 638 ether_ifattach(ifp, sc->ale_eaddr); 639 640 /* VLAN capability setup. */ 641 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 642 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 643 if_setcapenable(ifp, if_getcapabilities(ifp)); 644 /* 645 * Even though controllers supported by ale(3) have Rx checksum 646 * offload bug the workaround for fragmented frames seemed to 647 * work so far. However it seems Rx checksum offload does not 648 * work under certain conditions. So disable Rx checksum offload 649 * until I find more clue about it but allow users to override it. 650 */ 651 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM); 652 653 /* Tell the upper layer(s) we support long frames. */ 654 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 655 656 /* Create local taskq. */ 657 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 658 taskqueue_thread_enqueue, &sc->ale_tq); 659 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 660 device_get_nameunit(sc->ale_dev)); 661 662 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 663 msic = ALE_MSIX_MESSAGES; 664 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 665 msic = ALE_MSI_MESSAGES; 666 else 667 msic = 1; 668 for (i = 0; i < msic; i++) { 669 error = bus_setup_intr(dev, sc->ale_irq[i], 670 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 671 &sc->ale_intrhand[i]); 672 if (error != 0) 673 break; 674 } 675 if (error != 0) { 676 device_printf(dev, "could not set up interrupt handler.\n"); 677 taskqueue_free(sc->ale_tq); 678 sc->ale_tq = NULL; 679 ether_ifdetach(ifp); 680 goto fail; 681 } 682 683 fail: 684 if (error != 0) 685 ale_detach(dev); 686 687 return (error); 688 } 689 690 static int 691 ale_detach(device_t dev) 692 { 693 struct ale_softc *sc; 694 if_t ifp; 695 int i, msic; 696 697 sc = device_get_softc(dev); 698 699 ifp = sc->ale_ifp; 700 if (device_is_attached(dev)) { 701 ether_ifdetach(ifp); 702 ALE_LOCK(sc); 703 ale_stop(sc); 704 ALE_UNLOCK(sc); 705 callout_drain(&sc->ale_tick_ch); 706 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 707 } 708 709 if (sc->ale_tq != NULL) { 710 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 711 taskqueue_free(sc->ale_tq); 712 sc->ale_tq = NULL; 713 } 714 715 if (sc->ale_miibus != NULL) { 716 device_delete_child(dev, sc->ale_miibus); 717 sc->ale_miibus = NULL; 718 } 719 bus_generic_detach(dev); 720 ale_dma_free(sc); 721 722 if (ifp != NULL) { 723 if_free(ifp); 724 sc->ale_ifp = NULL; 725 } 726 727 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 728 msic = ALE_MSIX_MESSAGES; 729 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 730 msic = ALE_MSI_MESSAGES; 731 else 732 msic = 1; 733 for (i = 0; i < msic; i++) { 734 if (sc->ale_intrhand[i] != NULL) { 735 bus_teardown_intr(dev, sc->ale_irq[i], 736 sc->ale_intrhand[i]); 737 sc->ale_intrhand[i] = NULL; 738 } 739 } 740 741 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 742 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 743 pci_release_msi(dev); 744 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 745 mtx_destroy(&sc->ale_mtx); 746 747 return (0); 748 } 749 750 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 751 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 752 753 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 754 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 755 756 static void 757 ale_sysctl_node(struct ale_softc *sc) 758 { 759 struct sysctl_ctx_list *ctx; 760 struct sysctl_oid_list *child, *parent; 761 struct sysctl_oid *tree; 762 struct ale_hw_stats *stats; 763 int error; 764 765 stats = &sc->ale_stats; 766 ctx = device_get_sysctl_ctx(sc->ale_dev); 767 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 768 769 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 770 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_rx_mod, 771 0, sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 772 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 773 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_tx_mod, 774 0, sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 775 /* Pull in device tunables. */ 776 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 777 error = resource_int_value(device_get_name(sc->ale_dev), 778 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 779 if (error == 0) { 780 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 781 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 782 device_printf(sc->ale_dev, "int_rx_mod value out of " 783 "range; using default: %d\n", 784 ALE_IM_RX_TIMER_DEFAULT); 785 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 786 } 787 } 788 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 789 error = resource_int_value(device_get_name(sc->ale_dev), 790 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 791 if (error == 0) { 792 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 793 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 794 device_printf(sc->ale_dev, "int_tx_mod value out of " 795 "range; using default: %d\n", 796 ALE_IM_TX_TIMER_DEFAULT); 797 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 798 } 799 } 800 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 801 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 802 &sc->ale_process_limit, 0, sysctl_hw_ale_proc_limit, "I", 803 "max number of Rx events to process"); 804 /* Pull in device tunables. */ 805 sc->ale_process_limit = ALE_PROC_DEFAULT; 806 error = resource_int_value(device_get_name(sc->ale_dev), 807 device_get_unit(sc->ale_dev), "process_limit", 808 &sc->ale_process_limit); 809 if (error == 0) { 810 if (sc->ale_process_limit < ALE_PROC_MIN || 811 sc->ale_process_limit > ALE_PROC_MAX) { 812 device_printf(sc->ale_dev, 813 "process_limit value out of range; " 814 "using default: %d\n", ALE_PROC_DEFAULT); 815 sc->ale_process_limit = ALE_PROC_DEFAULT; 816 } 817 } 818 819 /* Misc statistics. */ 820 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 821 &stats->reset_brk_seq, 822 "Controller resets due to broken Rx sequnce number"); 823 824 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 825 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ATE statistics"); 826 parent = SYSCTL_CHILDREN(tree); 827 828 /* Rx statistics. */ 829 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 830 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 831 child = SYSCTL_CHILDREN(tree); 832 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 833 &stats->rx_frames, "Good frames"); 834 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 835 &stats->rx_bcast_frames, "Good broadcast frames"); 836 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 837 &stats->rx_mcast_frames, "Good multicast frames"); 838 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 839 &stats->rx_pause_frames, "Pause control frames"); 840 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 841 &stats->rx_control_frames, "Control frames"); 842 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 843 &stats->rx_crcerrs, "CRC errors"); 844 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 845 &stats->rx_lenerrs, "Frames with length mismatched"); 846 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 847 &stats->rx_bytes, "Good octets"); 848 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 849 &stats->rx_bcast_bytes, "Good broadcast octets"); 850 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 851 &stats->rx_mcast_bytes, "Good multicast octets"); 852 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 853 &stats->rx_runts, "Too short frames"); 854 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 855 &stats->rx_fragments, "Fragmented frames"); 856 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 857 &stats->rx_pkts_64, "64 bytes frames"); 858 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 859 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 860 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 861 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 862 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 863 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 864 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 865 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 866 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 867 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 868 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 869 &stats->rx_pkts_1519_max, "1519 to max frames"); 870 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 871 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 872 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 873 &stats->rx_fifo_oflows, "FIFO overflows"); 874 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 875 &stats->rx_rrs_errs, "Return status write-back errors"); 876 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 877 &stats->rx_alignerrs, "Alignment errors"); 878 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 879 &stats->rx_pkts_filtered, 880 "Frames dropped due to address filtering"); 881 882 /* Tx statistics. */ 883 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 884 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 885 child = SYSCTL_CHILDREN(tree); 886 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 887 &stats->tx_frames, "Good frames"); 888 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 889 &stats->tx_bcast_frames, "Good broadcast frames"); 890 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 891 &stats->tx_mcast_frames, "Good multicast frames"); 892 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 893 &stats->tx_pause_frames, "Pause control frames"); 894 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 895 &stats->tx_control_frames, "Control frames"); 896 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 897 &stats->tx_excess_defer, "Frames with excessive derferrals"); 898 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 899 &stats->tx_excess_defer, "Frames with derferrals"); 900 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 901 &stats->tx_bytes, "Good octets"); 902 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 903 &stats->tx_bcast_bytes, "Good broadcast octets"); 904 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 905 &stats->tx_mcast_bytes, "Good multicast octets"); 906 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 907 &stats->tx_pkts_64, "64 bytes frames"); 908 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 909 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 910 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 911 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 912 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 913 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 914 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 915 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 916 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 917 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 918 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 919 &stats->tx_pkts_1519_max, "1519 to max frames"); 920 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 921 &stats->tx_single_colls, "Single collisions"); 922 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 923 &stats->tx_multi_colls, "Multiple collisions"); 924 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 925 &stats->tx_late_colls, "Late collisions"); 926 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 927 &stats->tx_excess_colls, "Excessive collisions"); 928 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 929 &stats->tx_underrun, "FIFO underruns"); 930 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 931 &stats->tx_desc_underrun, "Descriptor write-back errors"); 932 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 933 &stats->tx_lenerrs, "Frames with length mismatched"); 934 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 935 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 936 } 937 938 #undef ALE_SYSCTL_STAT_ADD32 939 #undef ALE_SYSCTL_STAT_ADD64 940 941 struct ale_dmamap_arg { 942 bus_addr_t ale_busaddr; 943 }; 944 945 static void 946 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 947 { 948 struct ale_dmamap_arg *ctx; 949 950 if (error != 0) 951 return; 952 953 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 954 955 ctx = (struct ale_dmamap_arg *)arg; 956 ctx->ale_busaddr = segs[0].ds_addr; 957 } 958 959 /* 960 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 961 * which specifies high address region of DMA blocks. Therefore these 962 * blocks should have the same high address of given 4GB address 963 * space(i.e. crossing 4GB boundary is not allowed). 964 */ 965 static int 966 ale_check_boundary(struct ale_softc *sc) 967 { 968 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 969 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 970 971 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 972 sc->ale_pagesize; 973 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 974 sc->ale_pagesize; 975 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 976 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 977 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 978 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 979 980 if ((ALE_ADDR_HI(tx_ring_end) != 981 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 982 (ALE_ADDR_HI(rx_page_end[0]) != 983 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 984 (ALE_ADDR_HI(rx_page_end[1]) != 985 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 986 (ALE_ADDR_HI(tx_cmb_end) != 987 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 988 (ALE_ADDR_HI(rx_cmb_end[0]) != 989 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 990 (ALE_ADDR_HI(rx_cmb_end[1]) != 991 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 992 return (EFBIG); 993 994 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 995 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 996 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 997 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 998 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 999 return (EFBIG); 1000 1001 return (0); 1002 } 1003 1004 static int 1005 ale_dma_alloc(struct ale_softc *sc) 1006 { 1007 struct ale_txdesc *txd; 1008 bus_addr_t lowaddr; 1009 struct ale_dmamap_arg ctx; 1010 int error, guard_size, i; 1011 1012 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1013 guard_size = ALE_JUMBO_FRAMELEN; 1014 else 1015 guard_size = ALE_MAX_FRAMELEN; 1016 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1017 ALE_RX_PAGE_ALIGN); 1018 lowaddr = BUS_SPACE_MAXADDR; 1019 again: 1020 /* Create parent DMA tag. */ 1021 error = bus_dma_tag_create( 1022 bus_get_dma_tag(sc->ale_dev), /* parent */ 1023 1, 0, /* alignment, boundary */ 1024 lowaddr, /* lowaddr */ 1025 BUS_SPACE_MAXADDR, /* highaddr */ 1026 NULL, NULL, /* filter, filterarg */ 1027 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1028 0, /* nsegments */ 1029 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1030 0, /* flags */ 1031 NULL, NULL, /* lockfunc, lockarg */ 1032 &sc->ale_cdata.ale_parent_tag); 1033 if (error != 0) { 1034 device_printf(sc->ale_dev, 1035 "could not create parent DMA tag.\n"); 1036 goto fail; 1037 } 1038 1039 /* Create DMA tag for Tx descriptor ring. */ 1040 error = bus_dma_tag_create( 1041 sc->ale_cdata.ale_parent_tag, /* parent */ 1042 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1043 BUS_SPACE_MAXADDR, /* lowaddr */ 1044 BUS_SPACE_MAXADDR, /* highaddr */ 1045 NULL, NULL, /* filter, filterarg */ 1046 ALE_TX_RING_SZ, /* maxsize */ 1047 1, /* nsegments */ 1048 ALE_TX_RING_SZ, /* maxsegsize */ 1049 0, /* flags */ 1050 NULL, NULL, /* lockfunc, lockarg */ 1051 &sc->ale_cdata.ale_tx_ring_tag); 1052 if (error != 0) { 1053 device_printf(sc->ale_dev, 1054 "could not create Tx ring DMA tag.\n"); 1055 goto fail; 1056 } 1057 1058 /* Create DMA tag for Rx pages. */ 1059 for (i = 0; i < ALE_RX_PAGES; i++) { 1060 error = bus_dma_tag_create( 1061 sc->ale_cdata.ale_parent_tag, /* parent */ 1062 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1063 BUS_SPACE_MAXADDR, /* lowaddr */ 1064 BUS_SPACE_MAXADDR, /* highaddr */ 1065 NULL, NULL, /* filter, filterarg */ 1066 sc->ale_pagesize, /* maxsize */ 1067 1, /* nsegments */ 1068 sc->ale_pagesize, /* maxsegsize */ 1069 0, /* flags */ 1070 NULL, NULL, /* lockfunc, lockarg */ 1071 &sc->ale_cdata.ale_rx_page[i].page_tag); 1072 if (error != 0) { 1073 device_printf(sc->ale_dev, 1074 "could not create Rx page %d DMA tag.\n", i); 1075 goto fail; 1076 } 1077 } 1078 1079 /* Create DMA tag for Tx coalescing message block. */ 1080 error = bus_dma_tag_create( 1081 sc->ale_cdata.ale_parent_tag, /* parent */ 1082 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1083 BUS_SPACE_MAXADDR, /* lowaddr */ 1084 BUS_SPACE_MAXADDR, /* highaddr */ 1085 NULL, NULL, /* filter, filterarg */ 1086 ALE_TX_CMB_SZ, /* maxsize */ 1087 1, /* nsegments */ 1088 ALE_TX_CMB_SZ, /* maxsegsize */ 1089 0, /* flags */ 1090 NULL, NULL, /* lockfunc, lockarg */ 1091 &sc->ale_cdata.ale_tx_cmb_tag); 1092 if (error != 0) { 1093 device_printf(sc->ale_dev, 1094 "could not create Tx CMB DMA tag.\n"); 1095 goto fail; 1096 } 1097 1098 /* Create DMA tag for Rx coalescing message block. */ 1099 for (i = 0; i < ALE_RX_PAGES; i++) { 1100 error = bus_dma_tag_create( 1101 sc->ale_cdata.ale_parent_tag, /* parent */ 1102 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1103 BUS_SPACE_MAXADDR, /* lowaddr */ 1104 BUS_SPACE_MAXADDR, /* highaddr */ 1105 NULL, NULL, /* filter, filterarg */ 1106 ALE_RX_CMB_SZ, /* maxsize */ 1107 1, /* nsegments */ 1108 ALE_RX_CMB_SZ, /* maxsegsize */ 1109 0, /* flags */ 1110 NULL, NULL, /* lockfunc, lockarg */ 1111 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1112 if (error != 0) { 1113 device_printf(sc->ale_dev, 1114 "could not create Rx page %d CMB DMA tag.\n", i); 1115 goto fail; 1116 } 1117 } 1118 1119 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1120 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1121 (void **)&sc->ale_cdata.ale_tx_ring, 1122 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1123 &sc->ale_cdata.ale_tx_ring_map); 1124 if (error != 0) { 1125 device_printf(sc->ale_dev, 1126 "could not allocate DMA'able memory for Tx ring.\n"); 1127 goto fail; 1128 } 1129 ctx.ale_busaddr = 0; 1130 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1131 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1132 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1133 if (error != 0 || ctx.ale_busaddr == 0) { 1134 device_printf(sc->ale_dev, 1135 "could not load DMA'able memory for Tx ring.\n"); 1136 goto fail; 1137 } 1138 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1139 1140 /* Rx pages. */ 1141 for (i = 0; i < ALE_RX_PAGES; i++) { 1142 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1143 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1144 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1145 &sc->ale_cdata.ale_rx_page[i].page_map); 1146 if (error != 0) { 1147 device_printf(sc->ale_dev, 1148 "could not allocate DMA'able memory for " 1149 "Rx page %d.\n", i); 1150 goto fail; 1151 } 1152 ctx.ale_busaddr = 0; 1153 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1154 sc->ale_cdata.ale_rx_page[i].page_map, 1155 sc->ale_cdata.ale_rx_page[i].page_addr, 1156 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1157 if (error != 0 || ctx.ale_busaddr == 0) { 1158 device_printf(sc->ale_dev, 1159 "could not load DMA'able memory for " 1160 "Rx page %d.\n", i); 1161 goto fail; 1162 } 1163 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1164 } 1165 1166 /* Tx CMB. */ 1167 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1168 (void **)&sc->ale_cdata.ale_tx_cmb, 1169 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1170 &sc->ale_cdata.ale_tx_cmb_map); 1171 if (error != 0) { 1172 device_printf(sc->ale_dev, 1173 "could not allocate DMA'able memory for Tx CMB.\n"); 1174 goto fail; 1175 } 1176 ctx.ale_busaddr = 0; 1177 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1178 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1179 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1180 if (error != 0 || ctx.ale_busaddr == 0) { 1181 device_printf(sc->ale_dev, 1182 "could not load DMA'able memory for Tx CMB.\n"); 1183 goto fail; 1184 } 1185 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1186 1187 /* Rx CMB. */ 1188 for (i = 0; i < ALE_RX_PAGES; i++) { 1189 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1190 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1191 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1192 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1193 if (error != 0) { 1194 device_printf(sc->ale_dev, "could not allocate " 1195 "DMA'able memory for Rx page %d CMB.\n", i); 1196 goto fail; 1197 } 1198 ctx.ale_busaddr = 0; 1199 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1200 sc->ale_cdata.ale_rx_page[i].cmb_map, 1201 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1202 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1203 if (error != 0 || ctx.ale_busaddr == 0) { 1204 device_printf(sc->ale_dev, "could not load DMA'able " 1205 "memory for Rx page %d CMB.\n", i); 1206 goto fail; 1207 } 1208 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1209 } 1210 1211 /* 1212 * Tx descriptors/RXF0/CMB DMA blocks share the same 1213 * high address region of 64bit DMA address space. 1214 */ 1215 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1216 (error = ale_check_boundary(sc)) != 0) { 1217 device_printf(sc->ale_dev, "4GB boundary crossed, " 1218 "switching to 32bit DMA addressing mode.\n"); 1219 ale_dma_free(sc); 1220 /* 1221 * Limit max allowable DMA address space to 32bit 1222 * and try again. 1223 */ 1224 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1225 goto again; 1226 } 1227 1228 /* 1229 * Create Tx buffer parent tag. 1230 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1231 * needs separate parent DMA tag as parent DMA address space 1232 * could be restricted to be within 32bit address space by 1233 * 4GB boundary crossing. 1234 */ 1235 error = bus_dma_tag_create( 1236 bus_get_dma_tag(sc->ale_dev), /* parent */ 1237 1, 0, /* alignment, boundary */ 1238 BUS_SPACE_MAXADDR, /* lowaddr */ 1239 BUS_SPACE_MAXADDR, /* highaddr */ 1240 NULL, NULL, /* filter, filterarg */ 1241 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1242 0, /* nsegments */ 1243 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1244 0, /* flags */ 1245 NULL, NULL, /* lockfunc, lockarg */ 1246 &sc->ale_cdata.ale_buffer_tag); 1247 if (error != 0) { 1248 device_printf(sc->ale_dev, 1249 "could not create parent buffer DMA tag.\n"); 1250 goto fail; 1251 } 1252 1253 /* Create DMA tag for Tx buffers. */ 1254 error = bus_dma_tag_create( 1255 sc->ale_cdata.ale_buffer_tag, /* parent */ 1256 1, 0, /* alignment, boundary */ 1257 BUS_SPACE_MAXADDR, /* lowaddr */ 1258 BUS_SPACE_MAXADDR, /* highaddr */ 1259 NULL, NULL, /* filter, filterarg */ 1260 ALE_TSO_MAXSIZE, /* maxsize */ 1261 ALE_MAXTXSEGS, /* nsegments */ 1262 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1263 0, /* flags */ 1264 NULL, NULL, /* lockfunc, lockarg */ 1265 &sc->ale_cdata.ale_tx_tag); 1266 if (error != 0) { 1267 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1268 goto fail; 1269 } 1270 1271 /* Create DMA maps for Tx buffers. */ 1272 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1273 txd = &sc->ale_cdata.ale_txdesc[i]; 1274 txd->tx_m = NULL; 1275 txd->tx_dmamap = NULL; 1276 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1277 &txd->tx_dmamap); 1278 if (error != 0) { 1279 device_printf(sc->ale_dev, 1280 "could not create Tx dmamap.\n"); 1281 goto fail; 1282 } 1283 } 1284 1285 fail: 1286 return (error); 1287 } 1288 1289 static void 1290 ale_dma_free(struct ale_softc *sc) 1291 { 1292 struct ale_txdesc *txd; 1293 int i; 1294 1295 /* Tx buffers. */ 1296 if (sc->ale_cdata.ale_tx_tag != NULL) { 1297 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1298 txd = &sc->ale_cdata.ale_txdesc[i]; 1299 if (txd->tx_dmamap != NULL) { 1300 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1301 txd->tx_dmamap); 1302 txd->tx_dmamap = NULL; 1303 } 1304 } 1305 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1306 sc->ale_cdata.ale_tx_tag = NULL; 1307 } 1308 /* Tx descriptor ring. */ 1309 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1310 if (sc->ale_cdata.ale_tx_ring_paddr != 0) 1311 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1312 sc->ale_cdata.ale_tx_ring_map); 1313 if (sc->ale_cdata.ale_tx_ring != NULL) 1314 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1315 sc->ale_cdata.ale_tx_ring, 1316 sc->ale_cdata.ale_tx_ring_map); 1317 sc->ale_cdata.ale_tx_ring_paddr = 0; 1318 sc->ale_cdata.ale_tx_ring = NULL; 1319 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1320 sc->ale_cdata.ale_tx_ring_tag = NULL; 1321 } 1322 /* Rx page block. */ 1323 for (i = 0; i < ALE_RX_PAGES; i++) { 1324 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1325 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0) 1326 bus_dmamap_unload( 1327 sc->ale_cdata.ale_rx_page[i].page_tag, 1328 sc->ale_cdata.ale_rx_page[i].page_map); 1329 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1330 bus_dmamem_free( 1331 sc->ale_cdata.ale_rx_page[i].page_tag, 1332 sc->ale_cdata.ale_rx_page[i].page_addr, 1333 sc->ale_cdata.ale_rx_page[i].page_map); 1334 sc->ale_cdata.ale_rx_page[i].page_paddr = 0; 1335 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1336 bus_dma_tag_destroy( 1337 sc->ale_cdata.ale_rx_page[i].page_tag); 1338 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1339 } 1340 } 1341 /* Rx CMB. */ 1342 for (i = 0; i < ALE_RX_PAGES; i++) { 1343 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1344 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0) 1345 bus_dmamap_unload( 1346 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1347 sc->ale_cdata.ale_rx_page[i].cmb_map); 1348 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1349 bus_dmamem_free( 1350 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1351 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1352 sc->ale_cdata.ale_rx_page[i].cmb_map); 1353 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0; 1354 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1355 bus_dma_tag_destroy( 1356 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1357 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1358 } 1359 } 1360 /* Tx CMB. */ 1361 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1362 if (sc->ale_cdata.ale_tx_cmb_paddr != 0) 1363 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1364 sc->ale_cdata.ale_tx_cmb_map); 1365 if (sc->ale_cdata.ale_tx_cmb != NULL) 1366 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1367 sc->ale_cdata.ale_tx_cmb, 1368 sc->ale_cdata.ale_tx_cmb_map); 1369 sc->ale_cdata.ale_tx_cmb_paddr = 0; 1370 sc->ale_cdata.ale_tx_cmb = NULL; 1371 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1372 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1373 } 1374 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1375 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1376 sc->ale_cdata.ale_buffer_tag = NULL; 1377 } 1378 if (sc->ale_cdata.ale_parent_tag != NULL) { 1379 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1380 sc->ale_cdata.ale_parent_tag = NULL; 1381 } 1382 } 1383 1384 static int 1385 ale_shutdown(device_t dev) 1386 { 1387 1388 return (ale_suspend(dev)); 1389 } 1390 1391 /* 1392 * Note, this driver resets the link speed to 10/100Mbps by 1393 * restarting auto-negotiation in suspend/shutdown phase but we 1394 * don't know whether that auto-negotiation would succeed or not 1395 * as driver has no control after powering off/suspend operation. 1396 * If the renegotiation fail WOL may not work. Running at 1Gbps 1397 * will draw more power than 375mA at 3.3V which is specified in 1398 * PCI specification and that would result in complete 1399 * shutdowning power to ethernet controller. 1400 * 1401 * TODO 1402 * Save current negotiated media speed/duplex/flow-control to 1403 * softc and restore the same link again after resuming. PHY 1404 * handling such as power down/resetting to 100Mbps may be better 1405 * handled in suspend method in phy driver. 1406 */ 1407 static void 1408 ale_setlinkspeed(struct ale_softc *sc) 1409 { 1410 struct mii_data *mii; 1411 int aneg, i; 1412 1413 mii = device_get_softc(sc->ale_miibus); 1414 mii_pollstat(mii); 1415 aneg = 0; 1416 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1417 (IFM_ACTIVE | IFM_AVALID)) { 1418 switch IFM_SUBTYPE(mii->mii_media_active) { 1419 case IFM_10_T: 1420 case IFM_100_TX: 1421 return; 1422 case IFM_1000_T: 1423 aneg++; 1424 break; 1425 default: 1426 break; 1427 } 1428 } 1429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1430 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1431 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1432 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1433 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1434 DELAY(1000); 1435 if (aneg != 0) { 1436 /* 1437 * Poll link state until ale(4) get a 10/100Mbps link. 1438 */ 1439 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1440 mii_pollstat(mii); 1441 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1442 == (IFM_ACTIVE | IFM_AVALID)) { 1443 switch (IFM_SUBTYPE( 1444 mii->mii_media_active)) { 1445 case IFM_10_T: 1446 case IFM_100_TX: 1447 ale_mac_config(sc); 1448 return; 1449 default: 1450 break; 1451 } 1452 } 1453 ALE_UNLOCK(sc); 1454 pause("alelnk", hz); 1455 ALE_LOCK(sc); 1456 } 1457 if (i == MII_ANEGTICKS_GIGE) 1458 device_printf(sc->ale_dev, 1459 "establishing a link failed, WOL may not work!"); 1460 } 1461 /* 1462 * No link, force MAC to have 100Mbps, full-duplex link. 1463 * This is the last resort and may/may not work. 1464 */ 1465 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1466 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1467 ale_mac_config(sc); 1468 } 1469 1470 static void 1471 ale_setwol(struct ale_softc *sc) 1472 { 1473 if_t ifp; 1474 uint32_t reg, pmcs; 1475 uint16_t pmstat; 1476 int pmc; 1477 1478 ALE_LOCK_ASSERT(sc); 1479 1480 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1481 /* Disable WOL. */ 1482 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1483 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1484 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1485 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1486 /* Force PHY power down. */ 1487 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1488 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1489 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1490 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1491 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1492 return; 1493 } 1494 1495 ifp = sc->ale_ifp; 1496 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1497 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1498 ale_setlinkspeed(sc); 1499 } 1500 1501 pmcs = 0; 1502 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 1503 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1504 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1505 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1506 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1507 MAC_CFG_BCAST); 1508 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 1509 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1510 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1511 reg |= MAC_CFG_RX_ENB; 1512 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1513 1514 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1515 /* WOL disabled, PHY power down. */ 1516 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1517 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1518 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1519 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1520 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1521 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1522 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1523 GPHY_CTRL_PWDOWN_HW); 1524 } 1525 /* Request PME. */ 1526 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1527 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1528 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1529 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1530 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1531 } 1532 1533 static int 1534 ale_suspend(device_t dev) 1535 { 1536 struct ale_softc *sc; 1537 1538 sc = device_get_softc(dev); 1539 1540 ALE_LOCK(sc); 1541 ale_stop(sc); 1542 ale_setwol(sc); 1543 ALE_UNLOCK(sc); 1544 1545 return (0); 1546 } 1547 1548 static int 1549 ale_resume(device_t dev) 1550 { 1551 struct ale_softc *sc; 1552 if_t ifp; 1553 int pmc; 1554 uint16_t pmstat; 1555 1556 sc = device_get_softc(dev); 1557 1558 ALE_LOCK(sc); 1559 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1560 /* Disable PME and clear PME status. */ 1561 pmstat = pci_read_config(sc->ale_dev, 1562 pmc + PCIR_POWER_STATUS, 2); 1563 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1564 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1565 pci_write_config(sc->ale_dev, 1566 pmc + PCIR_POWER_STATUS, pmstat, 2); 1567 } 1568 } 1569 /* Reset PHY. */ 1570 ale_phy_reset(sc); 1571 ifp = sc->ale_ifp; 1572 if ((if_getflags(ifp) & IFF_UP) != 0) { 1573 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1574 ale_init_locked(sc); 1575 } 1576 ALE_UNLOCK(sc); 1577 1578 return (0); 1579 } 1580 1581 static int 1582 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1583 { 1584 struct ale_txdesc *txd, *txd_last; 1585 struct tx_desc *desc; 1586 struct mbuf *m; 1587 struct ip *ip; 1588 struct tcphdr *tcp; 1589 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1590 bus_dmamap_t map; 1591 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1592 int error, i, nsegs, prod, si; 1593 1594 ALE_LOCK_ASSERT(sc); 1595 1596 M_ASSERTPKTHDR((*m_head)); 1597 1598 m = *m_head; 1599 ip = NULL; 1600 tcp = NULL; 1601 cflags = vtag = 0; 1602 ip_off = poff = 0; 1603 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1604 /* 1605 * AR81xx requires offset of TCP/UDP payload in its Tx 1606 * descriptor to perform hardware Tx checksum offload. 1607 * Additionally, TSO requires IP/TCP header size and 1608 * modification of IP/TCP header in order to make TSO 1609 * engine work. This kind of operation takes many CPU 1610 * cycles on FreeBSD so fast host CPU is required to 1611 * get smooth TSO performance. 1612 */ 1613 struct ether_header *eh; 1614 1615 if (M_WRITABLE(m) == 0) { 1616 /* Get a writable copy. */ 1617 m = m_dup(*m_head, M_NOWAIT); 1618 /* Release original mbufs. */ 1619 m_freem(*m_head); 1620 if (m == NULL) { 1621 *m_head = NULL; 1622 return (ENOBUFS); 1623 } 1624 *m_head = m; 1625 } 1626 1627 /* 1628 * Buggy-controller requires 4 byte aligned Tx buffer 1629 * to make custom checksum offload work. 1630 */ 1631 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1632 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1633 (mtod(m, intptr_t) & 3) != 0) { 1634 m = m_defrag(*m_head, M_NOWAIT); 1635 if (m == NULL) { 1636 m_freem(*m_head); 1637 *m_head = NULL; 1638 return (ENOBUFS); 1639 } 1640 *m_head = m; 1641 } 1642 1643 ip_off = sizeof(struct ether_header); 1644 m = m_pullup(m, ip_off); 1645 if (m == NULL) { 1646 *m_head = NULL; 1647 return (ENOBUFS); 1648 } 1649 eh = mtod(m, struct ether_header *); 1650 /* 1651 * Check if hardware VLAN insertion is off. 1652 * Additional check for LLC/SNAP frame? 1653 */ 1654 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1655 ip_off = sizeof(struct ether_vlan_header); 1656 m = m_pullup(m, ip_off); 1657 if (m == NULL) { 1658 *m_head = NULL; 1659 return (ENOBUFS); 1660 } 1661 } 1662 m = m_pullup(m, ip_off + sizeof(struct ip)); 1663 if (m == NULL) { 1664 *m_head = NULL; 1665 return (ENOBUFS); 1666 } 1667 ip = (struct ip *)(mtod(m, char *) + ip_off); 1668 poff = ip_off + (ip->ip_hl << 2); 1669 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1670 /* 1671 * XXX 1672 * AR81xx requires the first descriptor should 1673 * not include any TCP playload for TSO case. 1674 * (i.e. ethernet header + IP + TCP header only) 1675 * m_pullup(9) above will ensure this too. 1676 * However it's not correct if the first mbuf 1677 * of the chain does not use cluster. 1678 */ 1679 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1680 if (m == NULL) { 1681 *m_head = NULL; 1682 return (ENOBUFS); 1683 } 1684 ip = (struct ip *)(mtod(m, char *) + ip_off); 1685 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1686 m = m_pullup(m, poff + (tcp->th_off << 2)); 1687 if (m == NULL) { 1688 *m_head = NULL; 1689 return (ENOBUFS); 1690 } 1691 /* 1692 * AR81xx requires IP/TCP header size and offset as 1693 * well as TCP pseudo checksum which complicates 1694 * TSO configuration. I guess this comes from the 1695 * adherence to Microsoft NDIS Large Send 1696 * specification which requires insertion of 1697 * pseudo checksum by upper stack. The pseudo 1698 * checksum that NDIS refers to doesn't include 1699 * TCP payload length so ale(4) should recompute 1700 * the pseudo checksum here. Hopefully this wouldn't 1701 * be much burden on modern CPUs. 1702 * Reset IP checksum and recompute TCP pseudo 1703 * checksum as NDIS specification said. 1704 */ 1705 ip->ip_sum = 0; 1706 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1707 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1708 } 1709 *m_head = m; 1710 } 1711 1712 si = prod = sc->ale_cdata.ale_tx_prod; 1713 txd = &sc->ale_cdata.ale_txdesc[prod]; 1714 txd_last = txd; 1715 map = txd->tx_dmamap; 1716 1717 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1718 *m_head, txsegs, &nsegs, 0); 1719 if (error == EFBIG) { 1720 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1721 if (m == NULL) { 1722 m_freem(*m_head); 1723 *m_head = NULL; 1724 return (ENOMEM); 1725 } 1726 *m_head = m; 1727 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1728 *m_head, txsegs, &nsegs, 0); 1729 if (error != 0) { 1730 m_freem(*m_head); 1731 *m_head = NULL; 1732 return (error); 1733 } 1734 } else if (error != 0) 1735 return (error); 1736 if (nsegs == 0) { 1737 m_freem(*m_head); 1738 *m_head = NULL; 1739 return (EIO); 1740 } 1741 1742 /* Check descriptor overrun. */ 1743 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1744 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1745 return (ENOBUFS); 1746 } 1747 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1748 1749 m = *m_head; 1750 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1751 /* Request TSO and set MSS. */ 1752 cflags |= ALE_TD_TSO; 1753 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1754 /* Set IP/TCP header size. */ 1755 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1756 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1757 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1758 /* 1759 * AR81xx supports Tx custom checksum offload feature 1760 * that offloads single 16bit checksum computation. 1761 * So you can choose one among IP, TCP and UDP. 1762 * Normally driver sets checksum start/insertion 1763 * position from the information of TCP/UDP frame as 1764 * TCP/UDP checksum takes more time than that of IP. 1765 * However it seems that custom checksum offload 1766 * requires 4 bytes aligned Tx buffers due to hardware 1767 * bug. 1768 * AR81xx also supports explicit Tx checksum computation 1769 * if it is told that the size of IP header and TCP 1770 * header(for UDP, the header size does not matter 1771 * because it's fixed length). However with this scheme 1772 * TSO does not work so you have to choose one either 1773 * TSO or explicit Tx checksum offload. I chosen TSO 1774 * plus custom checksum offload with work-around which 1775 * will cover most common usage for this consumer 1776 * ethernet controller. The work-around takes a lot of 1777 * CPU cycles if Tx buffer is not aligned on 4 bytes 1778 * boundary, though. 1779 */ 1780 cflags |= ALE_TD_CXSUM; 1781 /* Set checksum start offset. */ 1782 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1783 /* Set checksum insertion position of TCP/UDP. */ 1784 cflags |= ((poff + m->m_pkthdr.csum_data) << 1785 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1786 } 1787 1788 /* Configure VLAN hardware tag insertion. */ 1789 if ((m->m_flags & M_VLANTAG) != 0) { 1790 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1791 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1792 cflags |= ALE_TD_INSERT_VLAN_TAG; 1793 } 1794 1795 i = 0; 1796 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1797 /* 1798 * Make sure the first fragment contains 1799 * only ethernet and IP/TCP header with options. 1800 */ 1801 hdrlen = poff + (tcp->th_off << 2); 1802 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1803 desc->addr = htole64(txsegs[i].ds_addr); 1804 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1805 desc->flags = htole32(cflags); 1806 sc->ale_cdata.ale_tx_cnt++; 1807 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1808 if (m->m_len - hdrlen > 0) { 1809 /* Handle remaining payload of the first fragment. */ 1810 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1811 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1812 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1813 vtag); 1814 desc->flags = htole32(cflags); 1815 sc->ale_cdata.ale_tx_cnt++; 1816 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1817 } 1818 i = 1; 1819 } 1820 for (; i < nsegs; i++) { 1821 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1822 desc->addr = htole64(txsegs[i].ds_addr); 1823 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1824 desc->flags = htole32(cflags); 1825 sc->ale_cdata.ale_tx_cnt++; 1826 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1827 } 1828 /* Update producer index. */ 1829 sc->ale_cdata.ale_tx_prod = prod; 1830 /* Set TSO header on the first descriptor. */ 1831 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1832 desc = &sc->ale_cdata.ale_tx_ring[si]; 1833 desc->flags |= htole32(ALE_TD_TSO_HDR); 1834 } 1835 1836 /* Finally set EOP on the last descriptor. */ 1837 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1838 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1839 desc->flags |= htole32(ALE_TD_EOP); 1840 1841 /* Swap dmamap of the first and the last. */ 1842 txd = &sc->ale_cdata.ale_txdesc[prod]; 1843 map = txd_last->tx_dmamap; 1844 txd_last->tx_dmamap = txd->tx_dmamap; 1845 txd->tx_dmamap = map; 1846 txd->tx_m = m; 1847 1848 /* Sync descriptors. */ 1849 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1850 sc->ale_cdata.ale_tx_ring_map, 1851 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1852 1853 return (0); 1854 } 1855 1856 static void 1857 ale_start(if_t ifp) 1858 { 1859 struct ale_softc *sc; 1860 1861 sc = if_getsoftc(ifp); 1862 ALE_LOCK(sc); 1863 ale_start_locked(ifp); 1864 ALE_UNLOCK(sc); 1865 } 1866 1867 static void 1868 ale_start_locked(if_t ifp) 1869 { 1870 struct ale_softc *sc; 1871 struct mbuf *m_head; 1872 int enq; 1873 1874 sc = if_getsoftc(ifp); 1875 1876 ALE_LOCK_ASSERT(sc); 1877 1878 /* Reclaim transmitted frames. */ 1879 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1880 ale_txeof(sc); 1881 1882 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1883 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1884 return; 1885 1886 for (enq = 0; !if_sendq_empty(ifp); ) { 1887 m_head = if_dequeue(ifp); 1888 if (m_head == NULL) 1889 break; 1890 /* 1891 * Pack the data into the transmit ring. If we 1892 * don't have room, set the OACTIVE flag and wait 1893 * for the NIC to drain the ring. 1894 */ 1895 if (ale_encap(sc, &m_head)) { 1896 if (m_head == NULL) 1897 break; 1898 if_sendq_prepend(ifp, m_head); 1899 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1900 break; 1901 } 1902 1903 enq++; 1904 /* 1905 * If there's a BPF listener, bounce a copy of this frame 1906 * to him. 1907 */ 1908 ETHER_BPF_MTAP(ifp, m_head); 1909 } 1910 1911 if (enq > 0) { 1912 /* Kick. */ 1913 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1914 sc->ale_cdata.ale_tx_prod); 1915 /* Set a timeout in case the chip goes out to lunch. */ 1916 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1917 } 1918 } 1919 1920 static void 1921 ale_watchdog(struct ale_softc *sc) 1922 { 1923 if_t ifp; 1924 1925 ALE_LOCK_ASSERT(sc); 1926 1927 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1928 return; 1929 1930 ifp = sc->ale_ifp; 1931 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1932 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1933 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1934 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1935 ale_init_locked(sc); 1936 return; 1937 } 1938 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1939 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1940 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1941 ale_init_locked(sc); 1942 if (!if_sendq_empty(ifp)) 1943 ale_start_locked(ifp); 1944 } 1945 1946 static int 1947 ale_ioctl(if_t ifp, u_long cmd, caddr_t data) 1948 { 1949 struct ale_softc *sc; 1950 struct ifreq *ifr; 1951 struct mii_data *mii; 1952 int error, mask; 1953 1954 sc = if_getsoftc(ifp); 1955 ifr = (struct ifreq *)data; 1956 error = 0; 1957 switch (cmd) { 1958 case SIOCSIFMTU: 1959 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1960 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1961 ifr->ifr_mtu > ETHERMTU)) 1962 error = EINVAL; 1963 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1964 ALE_LOCK(sc); 1965 if_setmtu(ifp, ifr->ifr_mtu); 1966 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1967 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1968 ale_init_locked(sc); 1969 } 1970 ALE_UNLOCK(sc); 1971 } 1972 break; 1973 case SIOCSIFFLAGS: 1974 ALE_LOCK(sc); 1975 if ((if_getflags(ifp) & IFF_UP) != 0) { 1976 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1977 if (((if_getflags(ifp) ^ sc->ale_if_flags) 1978 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1979 ale_rxfilter(sc); 1980 } else { 1981 ale_init_locked(sc); 1982 } 1983 } else { 1984 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1985 ale_stop(sc); 1986 } 1987 sc->ale_if_flags = if_getflags(ifp); 1988 ALE_UNLOCK(sc); 1989 break; 1990 case SIOCADDMULTI: 1991 case SIOCDELMULTI: 1992 ALE_LOCK(sc); 1993 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1994 ale_rxfilter(sc); 1995 ALE_UNLOCK(sc); 1996 break; 1997 case SIOCSIFMEDIA: 1998 case SIOCGIFMEDIA: 1999 mii = device_get_softc(sc->ale_miibus); 2000 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2001 break; 2002 case SIOCSIFCAP: 2003 ALE_LOCK(sc); 2004 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2005 if ((mask & IFCAP_TXCSUM) != 0 && 2006 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 2007 if_togglecapenable(ifp, IFCAP_TXCSUM); 2008 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2009 if_sethwassistbits(ifp, ALE_CSUM_FEATURES, 0); 2010 else 2011 if_sethwassistbits(ifp, 0, ALE_CSUM_FEATURES); 2012 } 2013 if ((mask & IFCAP_RXCSUM) != 0 && 2014 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 2015 if_togglecapenable(ifp, IFCAP_RXCSUM); 2016 if ((mask & IFCAP_TSO4) != 0 && 2017 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 2018 if_togglecapenable(ifp, IFCAP_TSO4); 2019 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 2020 if_sethwassistbits(ifp, CSUM_TSO, 0); 2021 else 2022 if_sethwassistbits(ifp, 0, CSUM_TSO); 2023 } 2024 2025 if ((mask & IFCAP_WOL_MCAST) != 0 && 2026 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 2027 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 2028 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2029 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2030 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2031 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2032 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2033 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2034 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2035 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2036 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2037 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2038 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2039 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2040 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2041 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 2042 ale_rxvlan(sc); 2043 } 2044 ALE_UNLOCK(sc); 2045 VLAN_CAPABILITIES(ifp); 2046 break; 2047 default: 2048 error = ether_ioctl(ifp, cmd, data); 2049 break; 2050 } 2051 2052 return (error); 2053 } 2054 2055 static void 2056 ale_mac_config(struct ale_softc *sc) 2057 { 2058 struct mii_data *mii; 2059 uint32_t reg; 2060 2061 ALE_LOCK_ASSERT(sc); 2062 2063 mii = device_get_softc(sc->ale_miibus); 2064 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2065 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2066 MAC_CFG_SPEED_MASK); 2067 /* Reprogram MAC with resolved speed/duplex. */ 2068 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2069 case IFM_10_T: 2070 case IFM_100_TX: 2071 reg |= MAC_CFG_SPEED_10_100; 2072 break; 2073 case IFM_1000_T: 2074 reg |= MAC_CFG_SPEED_1000; 2075 break; 2076 } 2077 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2078 reg |= MAC_CFG_FULL_DUPLEX; 2079 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2080 reg |= MAC_CFG_TX_FC; 2081 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2082 reg |= MAC_CFG_RX_FC; 2083 } 2084 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2085 } 2086 2087 static void 2088 ale_stats_clear(struct ale_softc *sc) 2089 { 2090 struct smb sb; 2091 uint32_t *reg; 2092 int i; 2093 2094 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2095 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2096 i += sizeof(uint32_t); 2097 } 2098 /* Read Tx statistics. */ 2099 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2100 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2101 i += sizeof(uint32_t); 2102 } 2103 } 2104 2105 static void 2106 ale_stats_update(struct ale_softc *sc) 2107 { 2108 struct ale_hw_stats *stat; 2109 struct smb sb, *smb; 2110 if_t ifp; 2111 uint32_t *reg; 2112 int i; 2113 2114 ALE_LOCK_ASSERT(sc); 2115 2116 ifp = sc->ale_ifp; 2117 stat = &sc->ale_stats; 2118 smb = &sb; 2119 2120 /* Read Rx statistics. */ 2121 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2122 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2123 i += sizeof(uint32_t); 2124 } 2125 /* Read Tx statistics. */ 2126 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2127 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2128 i += sizeof(uint32_t); 2129 } 2130 2131 /* Rx stats. */ 2132 stat->rx_frames += smb->rx_frames; 2133 stat->rx_bcast_frames += smb->rx_bcast_frames; 2134 stat->rx_mcast_frames += smb->rx_mcast_frames; 2135 stat->rx_pause_frames += smb->rx_pause_frames; 2136 stat->rx_control_frames += smb->rx_control_frames; 2137 stat->rx_crcerrs += smb->rx_crcerrs; 2138 stat->rx_lenerrs += smb->rx_lenerrs; 2139 stat->rx_bytes += smb->rx_bytes; 2140 stat->rx_runts += smb->rx_runts; 2141 stat->rx_fragments += smb->rx_fragments; 2142 stat->rx_pkts_64 += smb->rx_pkts_64; 2143 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2144 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2145 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2146 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2147 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2148 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2149 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2150 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2151 stat->rx_rrs_errs += smb->rx_rrs_errs; 2152 stat->rx_alignerrs += smb->rx_alignerrs; 2153 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2154 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2155 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2156 2157 /* Tx stats. */ 2158 stat->tx_frames += smb->tx_frames; 2159 stat->tx_bcast_frames += smb->tx_bcast_frames; 2160 stat->tx_mcast_frames += smb->tx_mcast_frames; 2161 stat->tx_pause_frames += smb->tx_pause_frames; 2162 stat->tx_excess_defer += smb->tx_excess_defer; 2163 stat->tx_control_frames += smb->tx_control_frames; 2164 stat->tx_deferred += smb->tx_deferred; 2165 stat->tx_bytes += smb->tx_bytes; 2166 stat->tx_pkts_64 += smb->tx_pkts_64; 2167 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2168 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2169 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2170 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2171 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2172 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2173 stat->tx_single_colls += smb->tx_single_colls; 2174 stat->tx_multi_colls += smb->tx_multi_colls; 2175 stat->tx_late_colls += smb->tx_late_colls; 2176 stat->tx_excess_colls += smb->tx_excess_colls; 2177 stat->tx_underrun += smb->tx_underrun; 2178 stat->tx_desc_underrun += smb->tx_desc_underrun; 2179 stat->tx_lenerrs += smb->tx_lenerrs; 2180 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2181 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2182 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2183 2184 /* Update counters in ifnet. */ 2185 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2186 2187 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2188 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2189 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2190 2191 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 2192 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 2193 2194 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2195 2196 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2197 smb->rx_crcerrs + smb->rx_lenerrs + 2198 smb->rx_runts + smb->rx_pkts_truncated + 2199 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2200 smb->rx_alignerrs); 2201 } 2202 2203 static int 2204 ale_intr(void *arg) 2205 { 2206 struct ale_softc *sc; 2207 uint32_t status; 2208 2209 sc = (struct ale_softc *)arg; 2210 2211 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2212 if ((status & ALE_INTRS) == 0) 2213 return (FILTER_STRAY); 2214 /* Disable interrupts. */ 2215 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2216 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2217 2218 return (FILTER_HANDLED); 2219 } 2220 2221 static void 2222 ale_int_task(void *arg, int pending) 2223 { 2224 struct ale_softc *sc; 2225 if_t ifp; 2226 uint32_t status; 2227 int more; 2228 2229 sc = (struct ale_softc *)arg; 2230 2231 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2232 ALE_LOCK(sc); 2233 if (sc->ale_morework != 0) 2234 status |= INTR_RX_PKT; 2235 if ((status & ALE_INTRS) == 0) 2236 goto done; 2237 2238 /* Acknowledge interrupts but still disable interrupts. */ 2239 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2240 2241 ifp = sc->ale_ifp; 2242 more = 0; 2243 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2244 more = ale_rxeof(sc, sc->ale_process_limit); 2245 if (more == EAGAIN) 2246 sc->ale_morework = 1; 2247 else if (more == EIO) { 2248 sc->ale_stats.reset_brk_seq++; 2249 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2250 ale_init_locked(sc); 2251 ALE_UNLOCK(sc); 2252 return; 2253 } 2254 2255 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2256 if ((status & INTR_DMA_RD_TO_RST) != 0) 2257 device_printf(sc->ale_dev, 2258 "DMA read error! -- resetting\n"); 2259 if ((status & INTR_DMA_WR_TO_RST) != 0) 2260 device_printf(sc->ale_dev, 2261 "DMA write error! -- resetting\n"); 2262 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2263 ale_init_locked(sc); 2264 ALE_UNLOCK(sc); 2265 return; 2266 } 2267 if (!if_sendq_empty(ifp)) 2268 ale_start_locked(ifp); 2269 } 2270 2271 if (more == EAGAIN || 2272 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2273 ALE_UNLOCK(sc); 2274 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2275 return; 2276 } 2277 2278 done: 2279 ALE_UNLOCK(sc); 2280 2281 /* Re-enable interrupts. */ 2282 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2283 } 2284 2285 static void 2286 ale_txeof(struct ale_softc *sc) 2287 { 2288 if_t ifp; 2289 struct ale_txdesc *txd; 2290 uint32_t cons, prod; 2291 int prog; 2292 2293 ALE_LOCK_ASSERT(sc); 2294 2295 ifp = sc->ale_ifp; 2296 2297 if (sc->ale_cdata.ale_tx_cnt == 0) 2298 return; 2299 2300 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2301 sc->ale_cdata.ale_tx_ring_map, 2302 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2303 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2304 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2305 sc->ale_cdata.ale_tx_cmb_map, 2306 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2307 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2308 } else 2309 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2310 cons = sc->ale_cdata.ale_tx_cons; 2311 /* 2312 * Go through our Tx list and free mbufs for those 2313 * frames which have been transmitted. 2314 */ 2315 for (prog = 0; cons != prod; prog++, 2316 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2317 if (sc->ale_cdata.ale_tx_cnt <= 0) 2318 break; 2319 prog++; 2320 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2321 sc->ale_cdata.ale_tx_cnt--; 2322 txd = &sc->ale_cdata.ale_txdesc[cons]; 2323 if (txd->tx_m != NULL) { 2324 /* Reclaim transmitted mbufs. */ 2325 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2326 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2327 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2328 txd->tx_dmamap); 2329 m_freem(txd->tx_m); 2330 txd->tx_m = NULL; 2331 } 2332 } 2333 2334 if (prog > 0) { 2335 sc->ale_cdata.ale_tx_cons = cons; 2336 /* 2337 * Unarm watchdog timer only when there is no pending 2338 * Tx descriptors in queue. 2339 */ 2340 if (sc->ale_cdata.ale_tx_cnt == 0) 2341 sc->ale_watchdog_timer = 0; 2342 } 2343 } 2344 2345 static void 2346 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2347 uint32_t length, uint32_t *prod) 2348 { 2349 struct ale_rx_page *rx_page; 2350 2351 rx_page = *page; 2352 /* Update consumer position. */ 2353 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2354 ALE_RX_PAGE_ALIGN); 2355 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2356 /* 2357 * End of Rx page reached, let hardware reuse 2358 * this page. 2359 */ 2360 rx_page->cons = 0; 2361 *rx_page->cmb_addr = 0; 2362 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2363 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2364 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2365 RXF_VALID); 2366 /* Switch to alternate Rx page. */ 2367 sc->ale_cdata.ale_rx_curp ^= 1; 2368 rx_page = *page = 2369 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2370 /* Page flipped, sync CMB and Rx page. */ 2371 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2372 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2373 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2374 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2375 /* Sync completed, cache updated producer index. */ 2376 *prod = *rx_page->cmb_addr; 2377 } 2378 } 2379 2380 /* 2381 * It seems that AR81xx controller can compute partial checksum. 2382 * The partial checksum value can be used to accelerate checksum 2383 * computation for fragmented TCP/UDP packets. Upper network stack 2384 * already takes advantage of the partial checksum value in IP 2385 * reassembly stage. But I'm not sure the correctness of the 2386 * partial hardware checksum assistance due to lack of data sheet. 2387 * In addition, the Rx feature of controller that requires copying 2388 * for every frames effectively nullifies one of most nice offload 2389 * capability of controller. 2390 */ 2391 static void 2392 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2393 { 2394 if_t ifp; 2395 struct ip *ip; 2396 char *p; 2397 2398 ifp = sc->ale_ifp; 2399 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2400 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2401 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2402 2403 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2404 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2405 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2406 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2407 m->m_pkthdr.csum_flags |= 2408 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2409 m->m_pkthdr.csum_data = 0xffff; 2410 } 2411 } else { 2412 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2413 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2414 p = mtod(m, char *); 2415 p += ETHER_HDR_LEN; 2416 if ((status & ALE_RD_802_3) != 0) 2417 p += LLC_SNAPFRAMELEN; 2418 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0 && 2419 (status & ALE_RD_VLAN) != 0) 2420 p += ETHER_VLAN_ENCAP_LEN; 2421 ip = (struct ip *)p; 2422 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2423 return; 2424 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2425 CSUM_PSEUDO_HDR; 2426 m->m_pkthdr.csum_data = 0xffff; 2427 } 2428 } 2429 /* 2430 * Don't mark bad checksum for TCP/UDP frames 2431 * as fragmented frames may always have set 2432 * bad checksummed bit of frame status. 2433 */ 2434 } 2435 2436 /* Process received frames. */ 2437 static int 2438 ale_rxeof(struct ale_softc *sc, int count) 2439 { 2440 struct ale_rx_page *rx_page; 2441 struct rx_rs *rs; 2442 if_t ifp; 2443 struct mbuf *m; 2444 uint32_t length, prod, seqno, status, vtags; 2445 int prog; 2446 2447 ifp = sc->ale_ifp; 2448 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2449 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2450 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2451 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2452 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2453 /* 2454 * Don't directly access producer index as hardware may 2455 * update it while Rx handler is in progress. It would 2456 * be even better if there is a way to let hardware 2457 * know how far driver processed its received frames. 2458 * Alternatively, hardware could provide a way to disable 2459 * CMB updates until driver acknowledges the end of CMB 2460 * access. 2461 */ 2462 prod = *rx_page->cmb_addr; 2463 for (prog = 0; prog < count; prog++) { 2464 if (rx_page->cons >= prod) 2465 break; 2466 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2467 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2468 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2469 /* 2470 * Normally I believe this should not happen unless 2471 * severe driver bug or corrupted memory. However 2472 * it seems to happen under certain conditions which 2473 * is triggered by abrupt Rx events such as initiation 2474 * of bulk transfer of remote host. It's not easy to 2475 * reproduce this and I doubt it could be related 2476 * with FIFO overflow of hardware or activity of Tx 2477 * CMB updates. I also remember similar behaviour 2478 * seen on RealTek 8139 which uses resembling Rx 2479 * scheme. 2480 */ 2481 if (bootverbose) 2482 device_printf(sc->ale_dev, 2483 "garbled seq: %u, expected: %u -- " 2484 "resetting!\n", seqno, 2485 sc->ale_cdata.ale_rx_seqno); 2486 return (EIO); 2487 } 2488 /* Frame received. */ 2489 sc->ale_cdata.ale_rx_seqno++; 2490 length = ALE_RX_BYTES(le32toh(rs->length)); 2491 status = le32toh(rs->flags); 2492 if ((status & ALE_RD_ERROR) != 0) { 2493 /* 2494 * We want to pass the following frames to upper 2495 * layer regardless of error status of Rx return 2496 * status. 2497 * 2498 * o IP/TCP/UDP checksum is bad. 2499 * o frame length and protocol specific length 2500 * does not match. 2501 */ 2502 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2503 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2504 ALE_RD_TRUNC)) != 0) { 2505 ale_rx_update_page(sc, &rx_page, length, &prod); 2506 continue; 2507 } 2508 } 2509 /* 2510 * m_devget(9) is major bottle-neck of ale(4)(It comes 2511 * from hardware limitation). For jumbo frames we could 2512 * get a slightly better performance if driver use 2513 * m_getjcl(9) with proper buffer size argument. However 2514 * that would make code more complicated and I don't 2515 * think users would expect good Rx performance numbers 2516 * on these low-end consumer ethernet controller. 2517 */ 2518 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2519 ETHER_ALIGN, ifp, NULL); 2520 if (m == NULL) { 2521 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2522 ale_rx_update_page(sc, &rx_page, length, &prod); 2523 continue; 2524 } 2525 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2526 (status & ALE_RD_IPV4) != 0) 2527 ale_rxcsum(sc, m, status); 2528 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2529 (status & ALE_RD_VLAN) != 0) { 2530 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2531 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2532 m->m_flags |= M_VLANTAG; 2533 } 2534 2535 /* Pass it to upper layer. */ 2536 ALE_UNLOCK(sc); 2537 if_input(ifp, m); 2538 ALE_LOCK(sc); 2539 2540 ale_rx_update_page(sc, &rx_page, length, &prod); 2541 } 2542 2543 return (count > 0 ? 0 : EAGAIN); 2544 } 2545 2546 static void 2547 ale_tick(void *arg) 2548 { 2549 struct ale_softc *sc; 2550 struct mii_data *mii; 2551 2552 sc = (struct ale_softc *)arg; 2553 2554 ALE_LOCK_ASSERT(sc); 2555 2556 mii = device_get_softc(sc->ale_miibus); 2557 mii_tick(mii); 2558 ale_stats_update(sc); 2559 /* 2560 * Reclaim Tx buffers that have been transferred. It's not 2561 * needed here but it would release allocated mbuf chains 2562 * faster and limit the maximum delay to a hz. 2563 */ 2564 ale_txeof(sc); 2565 ale_watchdog(sc); 2566 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2567 } 2568 2569 static void 2570 ale_reset(struct ale_softc *sc) 2571 { 2572 uint32_t reg; 2573 int i; 2574 2575 /* Initialize PCIe module. From Linux. */ 2576 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2577 2578 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2579 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2580 DELAY(10); 2581 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2582 break; 2583 } 2584 if (i == 0) 2585 device_printf(sc->ale_dev, "master reset timeout!\n"); 2586 2587 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2588 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2589 break; 2590 DELAY(10); 2591 } 2592 2593 if (i == 0) 2594 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2595 } 2596 2597 static void 2598 ale_init(void *xsc) 2599 { 2600 struct ale_softc *sc; 2601 2602 sc = (struct ale_softc *)xsc; 2603 ALE_LOCK(sc); 2604 ale_init_locked(sc); 2605 ALE_UNLOCK(sc); 2606 } 2607 2608 static void 2609 ale_init_locked(struct ale_softc *sc) 2610 { 2611 if_t ifp; 2612 struct mii_data *mii; 2613 uint8_t eaddr[ETHER_ADDR_LEN]; 2614 bus_addr_t paddr; 2615 uint32_t reg, rxf_hi, rxf_lo; 2616 2617 ALE_LOCK_ASSERT(sc); 2618 2619 ifp = sc->ale_ifp; 2620 mii = device_get_softc(sc->ale_miibus); 2621 2622 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2623 return; 2624 /* 2625 * Cancel any pending I/O. 2626 */ 2627 ale_stop(sc); 2628 /* 2629 * Reset the chip to a known state. 2630 */ 2631 ale_reset(sc); 2632 /* Initialize Tx descriptors, DMA memory blocks. */ 2633 ale_init_rx_pages(sc); 2634 ale_init_tx_ring(sc); 2635 2636 /* Reprogram the station address. */ 2637 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 2638 CSR_WRITE_4(sc, ALE_PAR0, 2639 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2640 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2641 /* 2642 * Clear WOL status and disable all WOL feature as WOL 2643 * would interfere Rx operation under normal environments. 2644 */ 2645 CSR_READ_4(sc, ALE_WOL_CFG); 2646 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2647 /* 2648 * Set Tx descriptor/RXF0/CMB base addresses. They share 2649 * the same high address part of DMAable region. 2650 */ 2651 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2652 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2653 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2654 CSR_WRITE_4(sc, ALE_TPD_CNT, 2655 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2656 /* Set Rx page base address, note we use single queue. */ 2657 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2658 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2659 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2660 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2661 /* Set Tx/Rx CMB addresses. */ 2662 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2663 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2664 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2665 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2666 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2667 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2668 /* Mark RXF0 is valid. */ 2669 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2670 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2671 /* 2672 * No need to initialize RFX1/RXF2/RXF3. We don't use 2673 * multi-queue yet. 2674 */ 2675 2676 /* Set Rx page size, excluding guard frame size. */ 2677 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2678 /* Tell hardware that we're ready to load DMA blocks. */ 2679 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2680 2681 /* Set Rx/Tx interrupt trigger threshold. */ 2682 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2683 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2684 /* 2685 * XXX 2686 * Set interrupt trigger timer, its purpose and relation 2687 * with interrupt moderation mechanism is not clear yet. 2688 */ 2689 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2690 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2691 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2692 2693 /* Configure interrupt moderation timer. */ 2694 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2695 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2696 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2697 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2698 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2699 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2700 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2701 reg |= MASTER_IM_RX_TIMER_ENB; 2702 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2703 reg |= MASTER_IM_TX_TIMER_ENB; 2704 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2705 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2706 2707 /* Set Maximum frame size of controller. */ 2708 if (if_getmtu(ifp) < ETHERMTU) 2709 sc->ale_max_frame_size = ETHERMTU; 2710 else 2711 sc->ale_max_frame_size = if_getmtu(ifp); 2712 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2713 ETHER_CRC_LEN; 2714 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2715 /* Configure IPG/IFG parameters. */ 2716 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2717 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2718 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2719 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2720 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2721 /* Set parameters for half-duplex media. */ 2722 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2723 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2724 HDPX_CFG_LCOL_MASK) | 2725 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2726 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2727 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2728 HDPX_CFG_ABEBT_MASK) | 2729 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2730 HDPX_CFG_JAMIPG_MASK)); 2731 2732 /* Configure Tx jumbo frame parameters. */ 2733 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2734 if (if_getmtu(ifp) < ETHERMTU) 2735 reg = sc->ale_max_frame_size; 2736 else if (if_getmtu(ifp) < 6 * 1024) 2737 reg = (sc->ale_max_frame_size * 2) / 3; 2738 else 2739 reg = sc->ale_max_frame_size / 2; 2740 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2741 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2742 TX_JUMBO_THRESH_UNIT_SHIFT); 2743 } 2744 /* Configure TxQ. */ 2745 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2746 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2747 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2748 TXQ_CFG_TPD_BURST_MASK; 2749 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2750 2751 /* Configure Rx jumbo frame & flow control parameters. */ 2752 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2753 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2754 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2755 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2756 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2757 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2758 RX_JUMBO_LKAH_MASK)); 2759 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2760 rxf_hi = (reg * 7) / 10; 2761 rxf_lo = (reg * 3)/ 10; 2762 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2763 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2764 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2765 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2766 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2767 } 2768 2769 /* Disable RSS. */ 2770 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2771 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2772 2773 /* Configure RxQ. */ 2774 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2775 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2776 2777 /* Configure DMA parameters. */ 2778 reg = 0; 2779 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2780 reg |= DMA_CFG_TXCMB_ENB; 2781 CSR_WRITE_4(sc, ALE_DMA_CFG, 2782 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2783 sc->ale_dma_rd_burst | reg | 2784 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2785 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2786 DMA_CFG_RD_DELAY_CNT_MASK) | 2787 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2788 DMA_CFG_WR_DELAY_CNT_MASK)); 2789 2790 /* 2791 * Hardware can be configured to issue SMB interrupt based 2792 * on programmed interval. Since there is a callout that is 2793 * invoked for every hz in driver we use that instead of 2794 * relying on periodic SMB interrupt. 2795 */ 2796 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2797 /* Clear MAC statistics. */ 2798 ale_stats_clear(sc); 2799 2800 /* 2801 * Configure Tx/Rx MACs. 2802 * - Auto-padding for short frames. 2803 * - Enable CRC generation. 2804 * Actual reconfiguration of MAC for resolved speed/duplex 2805 * is followed after detection of link establishment. 2806 * AR81xx always does checksum computation regardless of 2807 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2808 * cause Rx handling issue for fragmented IP datagrams due 2809 * to silicon bug. 2810 */ 2811 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2812 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2813 MAC_CFG_PREAMBLE_MASK); 2814 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2815 reg |= MAC_CFG_SPEED_10_100; 2816 else 2817 reg |= MAC_CFG_SPEED_1000; 2818 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2819 2820 /* Set up the receive filter. */ 2821 ale_rxfilter(sc); 2822 ale_rxvlan(sc); 2823 2824 /* Acknowledge all pending interrupts and clear it. */ 2825 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2826 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2827 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2828 2829 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2830 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2831 2832 sc->ale_flags &= ~ALE_FLAG_LINK; 2833 /* Switch to the current media. */ 2834 mii_mediachg(mii); 2835 2836 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2837 } 2838 2839 static void 2840 ale_stop(struct ale_softc *sc) 2841 { 2842 if_t ifp; 2843 struct ale_txdesc *txd; 2844 uint32_t reg; 2845 int i; 2846 2847 ALE_LOCK_ASSERT(sc); 2848 /* 2849 * Mark the interface down and cancel the watchdog timer. 2850 */ 2851 ifp = sc->ale_ifp; 2852 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2853 sc->ale_flags &= ~ALE_FLAG_LINK; 2854 callout_stop(&sc->ale_tick_ch); 2855 sc->ale_watchdog_timer = 0; 2856 ale_stats_update(sc); 2857 /* Disable interrupts. */ 2858 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2859 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2860 /* Disable queue processing and DMA. */ 2861 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2862 reg &= ~TXQ_CFG_ENB; 2863 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2864 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2865 reg &= ~RXQ_CFG_ENB; 2866 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2867 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2868 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2869 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2870 DELAY(1000); 2871 /* Stop Rx/Tx MACs. */ 2872 ale_stop_mac(sc); 2873 /* Disable interrupts which might be touched in taskq handler. */ 2874 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2875 2876 /* 2877 * Free TX mbufs still in the queues. 2878 */ 2879 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2880 txd = &sc->ale_cdata.ale_txdesc[i]; 2881 if (txd->tx_m != NULL) { 2882 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2883 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2884 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2885 txd->tx_dmamap); 2886 m_freem(txd->tx_m); 2887 txd->tx_m = NULL; 2888 } 2889 } 2890 } 2891 2892 static void 2893 ale_stop_mac(struct ale_softc *sc) 2894 { 2895 uint32_t reg; 2896 int i; 2897 2898 ALE_LOCK_ASSERT(sc); 2899 2900 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2901 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2902 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2903 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2904 } 2905 2906 for (i = ALE_TIMEOUT; i > 0; i--) { 2907 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2908 if (reg == 0) 2909 break; 2910 DELAY(10); 2911 } 2912 if (i == 0) 2913 device_printf(sc->ale_dev, 2914 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2915 } 2916 2917 static void 2918 ale_init_tx_ring(struct ale_softc *sc) 2919 { 2920 struct ale_txdesc *txd; 2921 int i; 2922 2923 ALE_LOCK_ASSERT(sc); 2924 2925 sc->ale_cdata.ale_tx_prod = 0; 2926 sc->ale_cdata.ale_tx_cons = 0; 2927 sc->ale_cdata.ale_tx_cnt = 0; 2928 2929 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2930 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2931 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2932 txd = &sc->ale_cdata.ale_txdesc[i]; 2933 txd->tx_m = NULL; 2934 } 2935 *sc->ale_cdata.ale_tx_cmb = 0; 2936 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2937 sc->ale_cdata.ale_tx_cmb_map, 2938 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2939 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2940 sc->ale_cdata.ale_tx_ring_map, 2941 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2942 } 2943 2944 static void 2945 ale_init_rx_pages(struct ale_softc *sc) 2946 { 2947 struct ale_rx_page *rx_page; 2948 int i; 2949 2950 ALE_LOCK_ASSERT(sc); 2951 2952 sc->ale_morework = 0; 2953 sc->ale_cdata.ale_rx_seqno = 0; 2954 sc->ale_cdata.ale_rx_curp = 0; 2955 2956 for (i = 0; i < ALE_RX_PAGES; i++) { 2957 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2958 bzero(rx_page->page_addr, sc->ale_pagesize); 2959 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2960 rx_page->cons = 0; 2961 *rx_page->cmb_addr = 0; 2962 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2963 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2964 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2965 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2966 } 2967 } 2968 2969 static void 2970 ale_rxvlan(struct ale_softc *sc) 2971 { 2972 if_t ifp; 2973 uint32_t reg; 2974 2975 ALE_LOCK_ASSERT(sc); 2976 2977 ifp = sc->ale_ifp; 2978 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2979 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2980 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2981 reg |= MAC_CFG_VLAN_TAG_STRIP; 2982 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2983 } 2984 2985 static u_int 2986 ale_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2987 { 2988 uint32_t crc, *mchash = arg; 2989 2990 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 2991 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2992 2993 return (1); 2994 } 2995 2996 static void 2997 ale_rxfilter(struct ale_softc *sc) 2998 { 2999 if_t ifp; 3000 uint32_t mchash[2]; 3001 uint32_t rxcfg; 3002 3003 ALE_LOCK_ASSERT(sc); 3004 3005 ifp = sc->ale_ifp; 3006 3007 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3008 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3009 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 3010 rxcfg |= MAC_CFG_BCAST; 3011 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3012 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 3013 rxcfg |= MAC_CFG_PROMISC; 3014 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 3015 rxcfg |= MAC_CFG_ALLMULTI; 3016 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3017 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3018 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3019 return; 3020 } 3021 3022 /* Program new filter. */ 3023 bzero(mchash, sizeof(mchash)); 3024 if_foreach_llmaddr(ifp, ale_hash_maddr, &mchash); 3025 3026 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3027 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3028 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3029 } 3030 3031 static int 3032 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3033 { 3034 int error, value; 3035 3036 if (arg1 == NULL) 3037 return (EINVAL); 3038 value = *(int *)arg1; 3039 error = sysctl_handle_int(oidp, &value, 0, req); 3040 if (error || req->newptr == NULL) 3041 return (error); 3042 if (value < low || value > high) 3043 return (EINVAL); 3044 *(int *)arg1 = value; 3045 3046 return (0); 3047 } 3048 3049 static int 3050 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3051 { 3052 return (sysctl_int_range(oidp, arg1, arg2, req, 3053 ALE_PROC_MIN, ALE_PROC_MAX)); 3054 } 3055 3056 static int 3057 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3058 { 3059 3060 return (sysctl_int_range(oidp, arg1, arg2, req, 3061 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3062 } 3063