1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2022 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _LINUXKPI_LINUX_PCI_H_ 34 #define _LINUXKPI_LINUX_PCI_H_ 35 36 #define CONFIG_PCI_MSI 37 38 #include <linux/types.h> 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/module.h> 43 #include <sys/nv.h> 44 #include <sys/pciio.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pci_private.h> 48 49 #include <machine/resource.h> 50 51 #include <linux/list.h> 52 #include <linux/dmapool.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/compiler.h> 55 #include <linux/errno.h> 56 #include <asm/atomic.h> 57 #include <asm/memtype.h> 58 #include <linux/device.h> 59 #include <linux/pci_ids.h> 60 #include <linux/pm.h> 61 62 struct pci_device_id { 63 uint32_t vendor; 64 uint32_t device; 65 uint32_t subvendor; 66 uint32_t subdevice; 67 uint32_t class; 68 uint32_t class_mask; 69 uintptr_t driver_data; 70 }; 71 72 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */ 73 #define MODULE_DEVICE_TABLE(_bus, _table) \ 74 \ 75 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \ 76 DEVMETHOD_END \ 77 }; \ 78 \ 79 static driver_t _ ## _bus ## _ ## _table ## _driver = { \ 80 "lkpi_" #_bus #_table, \ 81 _ ## _bus ## _ ## _table ## _methods, \ 82 0 \ 83 }; \ 84 \ 85 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\ 86 0, 0); \ 87 \ 88 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \ 89 _bus, lkpi_ ## _table, _table, nitems(_table) - 1) 90 91 #define PCI_ANY_ID -1U 92 93 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 94 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 95 #define PCI_FUNC(devfn) ((devfn) & 0x07) 96 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 97 98 #define PCI_VDEVICE(_vendor, _device) \ 99 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 100 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 101 #define PCI_DEVICE(_vendor, _device) \ 102 .vendor = (_vendor), .device = (_device), \ 103 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 104 105 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 106 107 #define PCI_STD_NUM_BARS 6 108 #define PCI_BASE_ADDRESS_0 PCIR_BARS 109 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64 110 #define PCI_VENDOR_ID PCIR_VENDOR 111 #define PCI_DEVICE_ID PCIR_DEVICE 112 #define PCI_COMMAND PCIR_COMMAND 113 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 114 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN 115 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 116 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 117 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 118 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 119 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 120 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 121 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 122 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 123 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 124 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 125 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 126 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 127 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 128 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 129 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 130 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 131 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 132 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 133 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 134 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 135 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 136 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE 137 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 138 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 139 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 140 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 141 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 142 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 143 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 144 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 145 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 146 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 147 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 148 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED 149 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 150 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 151 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 152 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */ 153 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */ 154 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */ 155 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */ 156 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 157 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 158 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 159 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 160 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 161 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */ 162 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */ 163 #define PCI_EXP_LNKCTL2_TLS 0x000f 164 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 165 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 166 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 167 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 168 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 169 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ 170 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 171 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 172 173 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR 174 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH 175 #define PCI_MSI_FLAGS PCIR_MSI_CTRL 176 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE 177 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL 178 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE 179 180 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 181 #define PCI_EXP_DEVSTA_TRPND 0x0020 182 183 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 184 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 185 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 186 187 enum pci_bus_speed { 188 PCI_SPEED_UNKNOWN = -1, 189 PCIE_SPEED_2_5GT, 190 PCIE_SPEED_5_0GT, 191 PCIE_SPEED_8_0GT, 192 PCIE_SPEED_16_0GT, 193 PCIE_SPEED_32_0GT, 194 PCIE_SPEED_64_0GT, 195 }; 196 197 enum pcie_link_width { 198 PCIE_LNK_WIDTH_RESRV = 0x00, 199 PCIE_LNK_X1 = 0x01, 200 PCIE_LNK_X2 = 0x02, 201 PCIE_LNK_X4 = 0x04, 202 PCIE_LNK_X8 = 0x08, 203 PCIE_LNK_X12 = 0x0c, 204 PCIE_LNK_X16 = 0x10, 205 PCIE_LNK_X32 = 0x20, 206 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 207 }; 208 209 #define PCIE_LINK_STATE_L0S 0x00000001 210 #define PCIE_LINK_STATE_L1 0x00000002 211 #define PCIE_LINK_STATE_CLKPM 0x00000004 212 213 typedef int pci_power_t; 214 215 #define PCI_D0 PCI_POWERSTATE_D0 216 #define PCI_D1 PCI_POWERSTATE_D1 217 #define PCI_D2 PCI_POWERSTATE_D2 218 #define PCI_D3hot PCI_POWERSTATE_D3 219 #define PCI_D3cold 4 220 221 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 222 223 extern const char *pci_power_names[6]; 224 225 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 226 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 227 228 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 229 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 230 231 #define PCI_L1SS_CTL1 0x8 232 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 233 234 #define PCI_IRQ_LEGACY 0x01 235 #define PCI_IRQ_MSI 0x02 236 #define PCI_IRQ_MSIX 0x04 237 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_LEGACY) 238 239 struct pci_dev; 240 241 struct pci_driver { 242 struct list_head node; 243 char *name; 244 const struct pci_device_id *id_table; 245 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 246 void (*remove)(struct pci_dev *dev); 247 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 248 int (*resume) (struct pci_dev *dev); /* Device woken up */ 249 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 250 driver_t bsddriver; 251 devclass_t bsdclass; 252 struct device_driver driver; 253 const struct pci_error_handlers *err_handler; 254 bool isdrm; 255 int bsd_probe_return; 256 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 257 const nvlist_t *pf_config); 258 void (*bsd_iov_uninit)(device_t dev); 259 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 260 const nvlist_t *vf_config); 261 }; 262 263 struct pci_bus { 264 struct pci_dev *self; 265 /* struct pci_bus *parent */ 266 int domain; 267 int number; 268 }; 269 270 extern struct list_head pci_drivers; 271 extern struct list_head pci_devices; 272 extern spinlock_t pci_lock; 273 274 #define __devexit_p(x) x 275 276 #define module_pci_driver(_driver) \ 277 \ 278 static inline int \ 279 _pci_init(void) \ 280 { \ 281 \ 282 return (linux_pci_register_driver(&_driver)); \ 283 } \ 284 \ 285 static inline void \ 286 _pci_exit(void) \ 287 { \ 288 \ 289 linux_pci_unregister_driver(&_driver); \ 290 } \ 291 \ 292 module_init(_pci_init); \ 293 module_exit(_pci_exit) 294 295 struct msi_msg { 296 uint32_t data; 297 }; 298 299 struct pci_msi_desc { 300 struct { 301 bool is_64; 302 } msi_attrib; 303 }; 304 305 struct msi_desc { 306 struct msi_msg msg; 307 struct pci_msi_desc pci; 308 }; 309 310 struct msix_entry { 311 int entry; 312 int vector; 313 }; 314 315 /* 316 * If we find drivers accessing this from multiple KPIs we may have to 317 * refcount objects of this structure. 318 */ 319 struct resource; 320 struct pci_mmio_region { 321 TAILQ_ENTRY(pci_mmio_region) next; 322 struct resource *res; 323 int rid; 324 int type; 325 }; 326 327 struct pci_dev { 328 struct device dev; 329 struct list_head links; 330 struct pci_driver *pdrv; 331 struct pci_bus *bus; 332 struct pci_dev *root; 333 pci_power_t current_state; 334 uint16_t device; 335 uint16_t vendor; 336 uint16_t subsystem_vendor; 337 uint16_t subsystem_device; 338 unsigned int irq; 339 unsigned int devfn; 340 uint32_t class; 341 uint8_t revision; 342 uint8_t msi_cap; 343 uint8_t msix_cap; 344 bool managed; /* devres "pcim_*(). */ 345 bool want_iomap_res; 346 bool msi_enabled; 347 bool msix_enabled; 348 phys_addr_t rom; 349 size_t romlen; 350 struct msi_desc **msi_desc; 351 char *path_name; 352 353 TAILQ_HEAD(, pci_mmio_region) mmio; 354 spinlock_t pcie_cap_lock; 355 }; 356 357 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name); 358 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 359 unsigned int flags); 360 bool pci_device_is_present(struct pci_dev *pdev); 361 362 int linuxkpi_pcim_enable_device(struct pci_dev *pdev); 363 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev); 364 void *linuxkpi_pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size); 365 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res); 366 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask, 367 const char *name); 368 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name); 369 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar); 370 void linuxkpi_pci_release_regions(struct pci_dev *pdev); 371 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, 372 int nreq); 373 374 /* Internal helper function(s). */ 375 struct pci_dev *lkpinew_pci_dev(device_t); 376 void lkpi_pci_devres_release(struct device *, void *); 377 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *); 378 struct msi_desc *lkpi_pci_msi_desc_alloc(int); 379 struct device *lkpi_pci_find_irq_dev(unsigned int irq); 380 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec); 381 382 static inline bool 383 dev_is_pci(struct device *dev) 384 { 385 386 return (device_get_devclass(dev->bsddev) == devclass_find("pci")); 387 } 388 389 static inline int 390 pci_resource_type(struct pci_dev *pdev, int bar) 391 { 392 struct pci_map *pm; 393 394 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 395 if (!pm) 396 return (-1); 397 398 if (PCI_BAR_IO(pm->pm_value)) 399 return (SYS_RES_IOPORT); 400 else 401 return (SYS_RES_MEMORY); 402 } 403 404 /* 405 * All drivers just seem to want to inspect the type not flags. 406 */ 407 static inline int 408 pci_resource_flags(struct pci_dev *pdev, int bar) 409 { 410 int type; 411 412 type = pci_resource_type(pdev, bar); 413 if (type < 0) 414 return (0); 415 return (1 << type); 416 } 417 418 static inline const char * 419 pci_name(struct pci_dev *d) 420 { 421 return d->path_name; 422 } 423 424 static inline void * 425 pci_get_drvdata(struct pci_dev *pdev) 426 { 427 428 return dev_get_drvdata(&pdev->dev); 429 } 430 431 static inline void 432 pci_set_drvdata(struct pci_dev *pdev, void *data) 433 { 434 435 dev_set_drvdata(&pdev->dev, data); 436 } 437 438 static inline struct pci_dev * 439 pci_dev_get(struct pci_dev *pdev) 440 { 441 442 if (pdev != NULL) 443 get_device(&pdev->dev); 444 return (pdev); 445 } 446 447 static __inline void 448 pci_dev_put(struct pci_dev *pdev) 449 { 450 451 if (pdev != NULL) 452 put_device(&pdev->dev); 453 } 454 455 static inline int 456 pci_enable_device(struct pci_dev *pdev) 457 { 458 459 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 460 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 461 return (0); 462 } 463 464 static inline void 465 pci_disable_device(struct pci_dev *pdev) 466 { 467 468 pci_disable_busmaster(pdev->dev.bsddev); 469 } 470 471 static inline int 472 pci_set_master(struct pci_dev *pdev) 473 { 474 475 pci_enable_busmaster(pdev->dev.bsddev); 476 return (0); 477 } 478 479 static inline int 480 pci_set_power_state(struct pci_dev *pdev, int state) 481 { 482 483 pci_set_powerstate(pdev->dev.bsddev, state); 484 return (0); 485 } 486 487 static inline int 488 pci_clear_master(struct pci_dev *pdev) 489 { 490 491 pci_disable_busmaster(pdev->dev.bsddev); 492 return (0); 493 } 494 495 static inline bool 496 pci_is_root_bus(struct pci_bus *pbus) 497 { 498 499 return (pbus->self == NULL); 500 } 501 502 static inline struct pci_dev * 503 pci_upstream_bridge(struct pci_dev *pdev) 504 { 505 506 if (pci_is_root_bus(pdev->bus)) 507 return (NULL); 508 509 /* 510 * If we do not have a (proper) "upstream bridge" set, e.g., we point 511 * to ourselves, try to handle this case on the fly like we do 512 * for pcie_find_root_port(). 513 */ 514 if (pdev == pdev->bus->self) { 515 device_t bridge; 516 517 bridge = device_get_parent(pdev->dev.bsddev); 518 if (bridge == NULL) 519 goto done; 520 bridge = device_get_parent(bridge); 521 if (bridge == NULL) 522 goto done; 523 if (device_get_devclass(device_get_parent(bridge)) != 524 devclass_find("pci")) 525 goto done; 526 527 /* 528 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev 529 * for it so it can be returned. 530 */ 531 pdev->bus->self = lkpinew_pci_dev(bridge); 532 } 533 done: 534 return (pdev->bus->self); 535 } 536 537 #define pci_release_region(pdev, bar) linuxkpi_pci_release_region(pdev, bar) 538 #define pci_release_regions(pdev) linuxkpi_pci_release_regions(pdev) 539 #define pci_request_regions(pdev, res_name) \ 540 linuxkpi_pci_request_regions(pdev, res_name) 541 542 static inline void 543 lkpi_pci_disable_msix(struct pci_dev *pdev) 544 { 545 546 pci_release_msi(pdev->dev.bsddev); 547 548 /* 549 * The MSIX IRQ numbers associated with this PCI device are no 550 * longer valid and might be re-assigned. Make sure 551 * lkpi_pci_find_irq_dev() does no longer see them by 552 * resetting their references to zero: 553 */ 554 pdev->dev.irq_start = 0; 555 pdev->dev.irq_end = 0; 556 pdev->msix_enabled = false; 557 } 558 /* Only for consistency. No conflict on that one. */ 559 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 560 561 static inline void 562 lkpi_pci_disable_msi(struct pci_dev *pdev) 563 { 564 565 pci_release_msi(pdev->dev.bsddev); 566 567 pdev->dev.irq_start = 0; 568 pdev->dev.irq_end = 0; 569 pdev->irq = pdev->dev.irq; 570 pdev->msi_enabled = false; 571 } 572 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 573 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 574 575 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 576 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 577 578 static inline bus_addr_t 579 pci_bus_address(struct pci_dev *pdev, int bar) 580 { 581 582 return (pci_resource_start(pdev, bar)); 583 } 584 585 #define PCI_CAP_ID_EXP PCIY_EXPRESS 586 #define PCI_CAP_ID_PCIX PCIY_PCIX 587 #define PCI_CAP_ID_AGP PCIY_AGP 588 #define PCI_CAP_ID_PM PCIY_PMG 589 590 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 591 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 592 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 593 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 594 #define PCI_EXP_LNKSTA PCIER_LINK_STA 595 596 static inline int 597 pci_find_capability(struct pci_dev *pdev, int capid) 598 { 599 int reg; 600 601 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 602 return (0); 603 return (reg); 604 } 605 606 static inline int pci_pcie_cap(struct pci_dev *dev) 607 { 608 return pci_find_capability(dev, PCI_CAP_ID_EXP); 609 } 610 611 static inline int 612 pci_find_ext_capability(struct pci_dev *pdev, int capid) 613 { 614 int reg; 615 616 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 617 return (0); 618 return (reg); 619 } 620 621 #define PCIM_PCAP_PME_SHIFT 11 622 static __inline bool 623 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 624 { 625 struct pci_devinfo *dinfo; 626 pcicfgregs *cfg; 627 628 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 629 return (false); 630 631 dinfo = device_get_ivars(pdev->dev.bsddev); 632 cfg = &dinfo->cfg; 633 634 if (cfg->pp.pp_cap == 0) 635 return (false); 636 637 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 638 return (true); 639 640 return (false); 641 } 642 643 static inline int 644 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 645 { 646 647 if (!pci_enable_aspm) 648 return (-EPERM); 649 650 return (-ENXIO); 651 } 652 653 static inline int 654 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 655 { 656 657 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 658 return (0); 659 } 660 661 static inline int 662 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 663 { 664 665 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 666 return (0); 667 } 668 669 static inline int 670 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 671 { 672 673 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 674 return (0); 675 } 676 677 static inline int 678 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 679 { 680 681 pci_write_config(pdev->dev.bsddev, where, val, 1); 682 return (0); 683 } 684 685 static inline int 686 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 687 { 688 689 pci_write_config(pdev->dev.bsddev, where, val, 2); 690 return (0); 691 } 692 693 static inline int 694 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 695 { 696 697 pci_write_config(pdev->dev.bsddev, where, val, 4); 698 return (0); 699 } 700 701 int linux_pci_register_driver(struct pci_driver *pdrv); 702 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 703 void linux_pci_unregister_driver(struct pci_driver *pdrv); 704 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 705 706 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 707 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 708 709 /* 710 * Enable msix, positive errors indicate actual number of available 711 * vectors. Negative errors are failures. 712 * 713 * NB: define added to prevent this definition of pci_enable_msix from 714 * clashing with the native FreeBSD version. 715 */ 716 #define pci_enable_msix(...) linuxkpi_pci_enable_msix(__VA_ARGS__) 717 718 #define pci_enable_msix_range(...) \ 719 linux_pci_enable_msix_range(__VA_ARGS__) 720 721 static inline int 722 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 723 int minvec, int maxvec) 724 { 725 int nvec = maxvec; 726 int rc; 727 728 if (maxvec < minvec) 729 return (-ERANGE); 730 731 do { 732 rc = pci_enable_msix(dev, entries, nvec); 733 if (rc < 0) { 734 return (rc); 735 } else if (rc > 0) { 736 if (rc < minvec) 737 return (-ENOSPC); 738 nvec = rc; 739 } 740 } while (rc); 741 return (nvec); 742 } 743 744 #define pci_enable_msi(pdev) \ 745 linux_pci_enable_msi(pdev) 746 747 static inline int 748 pci_enable_msi(struct pci_dev *pdev) 749 { 750 751 return (_lkpi_pci_enable_msi_range(pdev, 1, 1)); 752 } 753 754 static inline int 755 pci_channel_offline(struct pci_dev *pdev) 756 { 757 758 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 759 } 760 761 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 762 { 763 return -ENODEV; 764 } 765 766 static inline void pci_disable_sriov(struct pci_dev *dev) 767 { 768 } 769 770 #define pci_iomap(pdev, mmio_bar, mmio_size) \ 771 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size) 772 #define pci_iounmap(pdev, res) linuxkpi_pci_iounmap(pdev, res) 773 774 static inline void 775 lkpi_pci_save_state(struct pci_dev *pdev) 776 { 777 778 pci_save_state(pdev->dev.bsddev); 779 } 780 781 static inline void 782 lkpi_pci_restore_state(struct pci_dev *pdev) 783 { 784 785 pci_restore_state(pdev->dev.bsddev); 786 } 787 788 #define pci_save_state(dev) lkpi_pci_save_state(dev) 789 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 790 791 static inline int 792 pci_reset_function(struct pci_dev *pdev) 793 { 794 795 return (-ENOSYS); 796 } 797 798 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 799 const struct pci_device_id _table[] __devinitdata 800 801 /* XXX This should not be necessary. */ 802 #define pcix_set_mmrbc(d, v) 0 803 #define pcix_get_max_mmrbc(d) 0 804 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 805 806 #define PCI_DMA_BIDIRECTIONAL 0 807 #define PCI_DMA_TODEVICE 1 808 #define PCI_DMA_FROMDEVICE 2 809 #define PCI_DMA_NONE 3 810 811 #define pci_pool dma_pool 812 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 813 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 814 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 815 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 816 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 817 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 818 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 819 _size, _vaddr, _dma_handle) 820 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 821 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 822 _sg, _nents, (enum dma_data_direction)_dir) 823 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 824 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 825 (_ptr), (_size), (enum dma_data_direction)_dir) 826 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 827 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 828 _addr, _size, (enum dma_data_direction)_dir) 829 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 830 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 831 _sg, _nents, (enum dma_data_direction)_dir) 832 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 833 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 834 _offset, _size, (enum dma_data_direction)_dir) 835 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 836 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 837 _dma_address, _size, (enum dma_data_direction)_dir) 838 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 839 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 840 dma_mapping_error(&(_pdev)->dev, _dma_addr) 841 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 842 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 843 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 844 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 845 #define pci_unmap_addr dma_unmap_addr 846 #define pci_unmap_addr_set dma_unmap_addr_set 847 #define pci_unmap_len dma_unmap_len 848 #define pci_unmap_len_set dma_unmap_len_set 849 850 typedef unsigned int __bitwise pci_channel_state_t; 851 typedef unsigned int __bitwise pci_ers_result_t; 852 853 enum pci_channel_state { 854 pci_channel_io_normal = 1, 855 pci_channel_io_frozen = 2, 856 pci_channel_io_perm_failure = 3, 857 }; 858 859 enum pci_ers_result { 860 PCI_ERS_RESULT_NONE = 1, 861 PCI_ERS_RESULT_CAN_RECOVER = 2, 862 PCI_ERS_RESULT_NEED_RESET = 3, 863 PCI_ERS_RESULT_DISCONNECT = 4, 864 PCI_ERS_RESULT_RECOVERED = 5, 865 }; 866 867 /* PCI bus error event callbacks */ 868 struct pci_error_handlers { 869 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 870 enum pci_channel_state error); 871 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 872 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 873 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 874 void (*resume)(struct pci_dev *dev); 875 }; 876 877 /* FreeBSD does not support SRIOV - yet */ 878 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 879 { 880 return dev; 881 } 882 883 static inline bool pci_is_pcie(struct pci_dev *dev) 884 { 885 return !!pci_pcie_cap(dev); 886 } 887 888 static inline u16 pcie_flags_reg(struct pci_dev *dev) 889 { 890 int pos; 891 u16 reg16; 892 893 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 894 if (!pos) 895 return 0; 896 897 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 898 899 return reg16; 900 } 901 902 static inline int pci_pcie_type(struct pci_dev *dev) 903 { 904 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 905 } 906 907 static inline int pcie_cap_version(struct pci_dev *dev) 908 { 909 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 910 } 911 912 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 913 { 914 int type = pci_pcie_type(dev); 915 916 return pcie_cap_version(dev) > 1 || 917 type == PCI_EXP_TYPE_ROOT_PORT || 918 type == PCI_EXP_TYPE_ENDPOINT || 919 type == PCI_EXP_TYPE_LEG_END; 920 } 921 922 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 923 { 924 return true; 925 } 926 927 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 928 { 929 int type = pci_pcie_type(dev); 930 931 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 932 (type == PCI_EXP_TYPE_DOWNSTREAM && 933 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 934 } 935 936 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 937 { 938 int type = pci_pcie_type(dev); 939 940 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 941 type == PCI_EXP_TYPE_RC_EC; 942 } 943 944 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 945 { 946 if (!pci_is_pcie(dev)) 947 return false; 948 949 switch (pos) { 950 case PCI_EXP_FLAGS_TYPE: 951 return true; 952 case PCI_EXP_DEVCAP: 953 case PCI_EXP_DEVCTL: 954 case PCI_EXP_DEVSTA: 955 return pcie_cap_has_devctl(dev); 956 case PCI_EXP_LNKCAP: 957 case PCI_EXP_LNKCTL: 958 case PCI_EXP_LNKSTA: 959 return pcie_cap_has_lnkctl(dev); 960 case PCI_EXP_SLTCAP: 961 case PCI_EXP_SLTCTL: 962 case PCI_EXP_SLTSTA: 963 return pcie_cap_has_sltctl(dev); 964 case PCI_EXP_RTCTL: 965 case PCI_EXP_RTCAP: 966 case PCI_EXP_RTSTA: 967 return pcie_cap_has_rtctl(dev); 968 case PCI_EXP_DEVCAP2: 969 case PCI_EXP_DEVCTL2: 970 case PCI_EXP_LNKCAP2: 971 case PCI_EXP_LNKCTL2: 972 case PCI_EXP_LNKSTA2: 973 return pcie_cap_version(dev) > 1; 974 default: 975 return false; 976 } 977 } 978 979 static inline int 980 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 981 { 982 *dst = 0; 983 if (pos & 3) 984 return -EINVAL; 985 986 if (!pcie_capability_reg_implemented(dev, pos)) 987 return -EINVAL; 988 989 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 990 } 991 992 static inline int 993 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 994 { 995 *dst = 0; 996 if (pos & 3) 997 return -EINVAL; 998 999 if (!pcie_capability_reg_implemented(dev, pos)) 1000 return -EINVAL; 1001 1002 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1003 } 1004 1005 static inline int 1006 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1007 { 1008 if (pos & 1) 1009 return -EINVAL; 1010 1011 if (!pcie_capability_reg_implemented(dev, pos)) 1012 return 0; 1013 1014 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1015 } 1016 1017 static inline int 1018 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1019 uint16_t clear, uint16_t set) 1020 { 1021 int error; 1022 uint16_t v; 1023 1024 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1025 spin_lock(&dev->pcie_cap_lock); 1026 1027 error = pcie_capability_read_word(dev, pos, &v); 1028 if (error == 0) { 1029 v &= ~clear; 1030 v |= set; 1031 error = pcie_capability_write_word(dev, pos, v); 1032 } 1033 1034 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL) 1035 spin_unlock(&dev->pcie_cap_lock); 1036 1037 return (error); 1038 } 1039 1040 static inline int 1041 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val) 1042 { 1043 return (pcie_capability_clear_and_set_word(dev, pos, 0, val)); 1044 } 1045 1046 static inline int 1047 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val) 1048 { 1049 return (pcie_capability_clear_and_set_word(dev, pos, val, 0)); 1050 } 1051 1052 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1053 enum pci_bus_speed *speed, enum pcie_link_width *width) 1054 { 1055 *speed = PCI_SPEED_UNKNOWN; 1056 *width = PCIE_LNK_WIDTH_UNKNOWN; 1057 return (0); 1058 } 1059 1060 static inline int 1061 pci_num_vf(struct pci_dev *dev) 1062 { 1063 return (0); 1064 } 1065 1066 static inline enum pci_bus_speed 1067 pcie_get_speed_cap(struct pci_dev *dev) 1068 { 1069 device_t root; 1070 uint32_t lnkcap, lnkcap2; 1071 int error, pos; 1072 1073 root = device_get_parent(dev->dev.bsddev); 1074 if (root == NULL) 1075 return (PCI_SPEED_UNKNOWN); 1076 root = device_get_parent(root); 1077 if (root == NULL) 1078 return (PCI_SPEED_UNKNOWN); 1079 root = device_get_parent(root); 1080 if (root == NULL) 1081 return (PCI_SPEED_UNKNOWN); 1082 1083 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1084 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1085 return (PCI_SPEED_UNKNOWN); 1086 1087 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1088 return (PCI_SPEED_UNKNOWN); 1089 1090 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1091 1092 if (lnkcap2) { /* PCIe r3.0-compliant */ 1093 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1094 return (PCIE_SPEED_2_5GT); 1095 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1096 return (PCIE_SPEED_5_0GT); 1097 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1098 return (PCIE_SPEED_8_0GT); 1099 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1100 return (PCIE_SPEED_16_0GT); 1101 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) 1102 return (PCIE_SPEED_32_0GT); 1103 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB) 1104 return (PCIE_SPEED_64_0GT); 1105 } else { /* pre-r3.0 */ 1106 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1107 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1108 return (PCIE_SPEED_2_5GT); 1109 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1110 return (PCIE_SPEED_5_0GT); 1111 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1112 return (PCIE_SPEED_8_0GT); 1113 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1114 return (PCIE_SPEED_16_0GT); 1115 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB) 1116 return (PCIE_SPEED_32_0GT); 1117 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB) 1118 return (PCIE_SPEED_64_0GT); 1119 } 1120 return (PCI_SPEED_UNKNOWN); 1121 } 1122 1123 static inline enum pcie_link_width 1124 pcie_get_width_cap(struct pci_dev *dev) 1125 { 1126 uint32_t lnkcap; 1127 1128 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1129 if (lnkcap) 1130 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1131 1132 return (PCIE_LNK_WIDTH_UNKNOWN); 1133 } 1134 1135 static inline int 1136 pcie_get_mps(struct pci_dev *dev) 1137 { 1138 return (pci_get_max_payload(dev->dev.bsddev)); 1139 } 1140 1141 static inline uint32_t 1142 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1143 { 1144 1145 switch(spd) { 1146 case PCIE_SPEED_64_0GT: 1147 return (64000 * 128 / 130); 1148 case PCIE_SPEED_32_0GT: 1149 return (32000 * 128 / 130); 1150 case PCIE_SPEED_16_0GT: 1151 return (16000 * 128 / 130); 1152 case PCIE_SPEED_8_0GT: 1153 return (8000 * 128 / 130); 1154 case PCIE_SPEED_5_0GT: 1155 return (5000 * 8 / 10); 1156 case PCIE_SPEED_2_5GT: 1157 return (2500 * 8 / 10); 1158 default: 1159 return (0); 1160 } 1161 } 1162 1163 static inline uint32_t 1164 pcie_bandwidth_available(struct pci_dev *pdev, 1165 struct pci_dev **limiting, 1166 enum pci_bus_speed *speed, 1167 enum pcie_link_width *width) 1168 { 1169 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1170 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1171 1172 if (speed) 1173 *speed = nspeed; 1174 if (width) 1175 *width = nwidth; 1176 1177 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1178 } 1179 1180 static inline bool 1181 pcie_aspm_enabled(struct pci_dev *pdev) 1182 { 1183 return (false); 1184 } 1185 1186 static inline struct pci_dev * 1187 pcie_find_root_port(struct pci_dev *pdev) 1188 { 1189 device_t root; 1190 1191 if (pdev->root != NULL) 1192 return (pdev->root); 1193 1194 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1195 if (root == NULL) 1196 return (NULL); 1197 1198 pdev->root = lkpinew_pci_dev(root); 1199 return (pdev->root); 1200 } 1201 1202 /* This is needed when people rip out the device "HotPlug". */ 1203 static inline void 1204 pci_lock_rescan_remove(void) 1205 { 1206 } 1207 1208 static inline void 1209 pci_unlock_rescan_remove(void) 1210 { 1211 } 1212 1213 static __inline void 1214 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1215 { 1216 } 1217 1218 static inline int 1219 pci_rescan_bus(struct pci_bus *pbus) 1220 { 1221 device_t *devlist, parent; 1222 int devcount, error; 1223 1224 if (!device_is_attached(pbus->self->dev.bsddev)) 1225 return (0); 1226 /* pci_rescan_method() will work on the pcib (parent). */ 1227 error = BUS_RESCAN(pbus->self->dev.bsddev); 1228 if (error != 0) 1229 return (0); 1230 1231 parent = device_get_parent(pbus->self->dev.bsddev); 1232 error = device_get_children(parent, &devlist, &devcount); 1233 if (error != 0) 1234 return (0); 1235 if (devcount != 0) 1236 free(devlist, M_TEMP); 1237 1238 return (devcount); 1239 } 1240 1241 /* 1242 * The following functions can be used to attach/detach the LinuxKPI's 1243 * PCI device runtime. The pci_driver and pci_device_id pointer is 1244 * allowed to be NULL. Other pointers must be all valid. 1245 * The pci_dev structure should be zero-initialized before passed 1246 * to the linux_pci_attach_device function. 1247 */ 1248 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1249 const struct pci_device_id *, struct pci_dev *); 1250 extern int linux_pci_detach_device(struct pci_dev *); 1251 1252 static inline int 1253 pci_dev_present(const struct pci_device_id *cur) 1254 { 1255 while (cur != NULL && (cur->vendor || cur->device)) { 1256 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1257 return (1); 1258 } 1259 cur++; 1260 } 1261 return (0); 1262 } 1263 1264 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1265 unsigned int bus, unsigned int devfn); 1266 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1267 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1268 1269 static inline int 1270 pci_domain_nr(struct pci_bus *pbus) 1271 { 1272 1273 return (pbus->domain); 1274 } 1275 1276 static inline int 1277 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1278 int pos, uint32_t *val, int len) 1279 { 1280 1281 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1282 return (0); 1283 } 1284 1285 static inline int 1286 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1287 { 1288 uint32_t tmp; 1289 int ret; 1290 1291 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1292 *val = (u16)tmp; 1293 return (ret); 1294 } 1295 1296 static inline int 1297 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1298 { 1299 uint32_t tmp; 1300 int ret; 1301 1302 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1303 *val = (u8)tmp; 1304 return (ret); 1305 } 1306 1307 static inline int 1308 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1309 uint32_t val, int size) 1310 { 1311 1312 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1313 return (0); 1314 } 1315 1316 static inline int 1317 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1318 uint8_t val) 1319 { 1320 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1321 } 1322 1323 static inline int 1324 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1325 uint16_t val) 1326 { 1327 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1328 } 1329 1330 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1331 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1332 1333 /* -------------------------------------------------------------------------- */ 1334 1335 #define pcim_enable_device(pdev) linuxkpi_pcim_enable_device(pdev) 1336 #define pcim_iomap_table(pdev) linuxkpi_pcim_iomap_table(pdev) 1337 #define pcim_iomap_regions(pdev, mask, name) \ 1338 linuxkpi_pcim_iomap_regions(pdev, mask, name) 1339 1340 static inline int 1341 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1342 { 1343 uint32_t requests, req_mask; 1344 int bar, error; 1345 1346 /* Request all the BARs ("regions") we do not iomap. */ 1347 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1348 for (bar = requests = 0; requests != req_mask; bar++) { 1349 if ((req_mask & (1 << bar)) == 0) 1350 continue; 1351 error = pci_request_region(pdev, bar, name); 1352 if (error != 0 && error != -ENODEV) 1353 goto err; 1354 requests |= (1 << bar); 1355 } 1356 1357 error = pcim_iomap_regions(pdev, mask, name); 1358 if (error != 0) 1359 goto err; 1360 1361 return (0); 1362 1363 err: 1364 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1365 if ((requests & (1 << bar)) != 0) 1366 pci_release_region(pdev, bar); 1367 } 1368 1369 return (-EINVAL); 1370 } 1371 1372 /* 1373 * We cannot simply re-define pci_get_device() as we would normally do 1374 * and then hide it in linux_pci.c as too many semi-native drivers still 1375 * include linux/pci.h and run into the conflict with native PCI. Linux drivers 1376 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device(). 1377 */ 1378 static inline struct pci_dev * 1379 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev) 1380 { 1381 1382 return (lkpi_pci_get_device(vendor, device, odev)); 1383 } 1384 1385 /* This is a FreeBSD extension so we can use bus_*(). */ 1386 static inline void 1387 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1388 { 1389 pdev->want_iomap_res = true; 1390 } 1391 1392 static inline bool 1393 pci_is_thunderbolt_attached(struct pci_dev *pdev) 1394 { 1395 1396 return (false); 1397 } 1398 1399 static inline void * 1400 pci_platform_rom(struct pci_dev *pdev, size_t *size) 1401 { 1402 1403 return (NULL); 1404 } 1405 1406 static inline void 1407 pci_ignore_hotplug(struct pci_dev *pdev) 1408 { 1409 } 1410 1411 static inline const char * 1412 pci_power_name(pci_power_t state) 1413 { 1414 int pstate = state + 1; 1415 1416 if (pstate >= 0 && pstate < nitems(pci_power_names)) 1417 return (pci_power_names[pstate]); 1418 else 1419 return (pci_power_names[0]); 1420 } 1421 1422 static inline int 1423 pcie_get_readrq(struct pci_dev *dev) 1424 { 1425 u16 ctl; 1426 1427 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl)) 1428 return (-EINVAL); 1429 1430 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12)); 1431 } 1432 1433 static inline bool 1434 pci_is_enabled(struct pci_dev *pdev) 1435 { 1436 1437 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) & 1438 PCIM_CMD_BUSMASTEREN) != 0); 1439 } 1440 1441 static inline int 1442 pci_wait_for_pending_transaction(struct pci_dev *pdev) 1443 { 1444 1445 return (0); 1446 } 1447 1448 static inline int 1449 pci_assign_resource(struct pci_dev *pdev, int bar) 1450 { 1451 1452 return (0); 1453 } 1454 1455 static inline int 1456 pci_irq_vector(struct pci_dev *pdev, unsigned int vector) 1457 { 1458 1459 if (!pdev->msix_enabled && !pdev->msi_enabled) { 1460 if (vector != 0) 1461 return (-EINVAL); 1462 return (pdev->irq); 1463 } 1464 1465 if (pdev->msix_enabled || pdev->msi_enabled) { 1466 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end) 1467 return (-EINVAL); 1468 return (pdev->dev.irq_start + vector); 1469 } 1470 1471 return (-ENXIO); 1472 } 1473 1474 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1475