1*0b57cec5SDimitry Andric //===-- WebAssemblySubtarget.cpp - WebAssembly Subtarget Information ------===//
2*0b57cec5SDimitry Andric //
3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0b57cec5SDimitry Andric //
7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
8*0b57cec5SDimitry Andric ///
9*0b57cec5SDimitry Andric /// \file
10*0b57cec5SDimitry Andric /// This file implements the WebAssembly-specific subclass of
11*0b57cec5SDimitry Andric /// TargetSubtarget.
12*0b57cec5SDimitry Andric ///
13*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
14*0b57cec5SDimitry Andric 
15*0b57cec5SDimitry Andric #include "WebAssemblySubtarget.h"
16*0b57cec5SDimitry Andric #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17*0b57cec5SDimitry Andric #include "WebAssemblyInstrInfo.h"
18*0b57cec5SDimitry Andric #include "llvm/MC/TargetRegistry.h"
19*0b57cec5SDimitry Andric using namespace llvm;
20*0b57cec5SDimitry Andric 
21*0b57cec5SDimitry Andric #define DEBUG_TYPE "wasm-subtarget"
22*0b57cec5SDimitry Andric 
23*0b57cec5SDimitry Andric #define GET_SUBTARGETINFO_CTOR
24*0b57cec5SDimitry Andric #define GET_SUBTARGETINFO_TARGET_DESC
25*0b57cec5SDimitry Andric #include "WebAssemblyGenSubtargetInfo.inc"
26*0b57cec5SDimitry Andric 
27*0b57cec5SDimitry Andric WebAssemblySubtarget &
initializeSubtargetDependencies(StringRef CPU,StringRef FS)28*0b57cec5SDimitry Andric WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU,
29*0b57cec5SDimitry Andric                                                       StringRef FS) {
30*0b57cec5SDimitry Andric   // Determine default and user-specified characteristics
31*0b57cec5SDimitry Andric   LLVM_DEBUG(llvm::dbgs() << "initializeSubtargetDependencies\n");
32*0b57cec5SDimitry Andric 
33*0b57cec5SDimitry Andric   if (CPU.empty())
34*0b57cec5SDimitry Andric     CPU = "generic";
35*0b57cec5SDimitry Andric 
36*0b57cec5SDimitry Andric   ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
37*0b57cec5SDimitry Andric   return *this;
38*0b57cec5SDimitry Andric }
39*0b57cec5SDimitry Andric 
WebAssemblySubtarget(const Triple & TT,const std::string & CPU,const std::string & FS,const TargetMachine & TM)40*0b57cec5SDimitry Andric WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
41*0b57cec5SDimitry Andric                                            const std::string &CPU,
42*0b57cec5SDimitry Andric                                            const std::string &FS,
43*0b57cec5SDimitry Andric                                            const TargetMachine &TM)
44*0b57cec5SDimitry Andric     : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
45*0b57cec5SDimitry Andric       TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
46*0b57cec5SDimitry Andric       TLInfo(TM, *this) {}
47*0b57cec5SDimitry Andric 
enableAtomicExpand() const48*0b57cec5SDimitry Andric bool WebAssemblySubtarget::enableAtomicExpand() const {
49*0b57cec5SDimitry Andric   // If atomics are disabled, atomic ops are lowered instead of expanded
50*0b57cec5SDimitry Andric   return hasAtomics();
51*0b57cec5SDimitry Andric }
52*0b57cec5SDimitry Andric 
enableMachineScheduler() const53*0b57cec5SDimitry Andric bool WebAssemblySubtarget::enableMachineScheduler() const {
54*0b57cec5SDimitry Andric   // Disable the MachineScheduler for now. Even with ShouldTrackPressure set and
55*0b57cec5SDimitry Andric   // enableMachineSchedDefaultSched overridden, it appears to have an overall
56*0b57cec5SDimitry Andric   // negative effect for the kinds of register optimizations we're doing.
57*0b57cec5SDimitry Andric   return false;
58*0b57cec5SDimitry Andric }
59*0b57cec5SDimitry Andric 
useAA() const60 bool WebAssemblySubtarget::useAA() const { return true; }
61