1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AMDGPU specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "AMDGPUTargetStreamer.h"
14 #include "AMDGPUPTNote.h"
15 #include "AMDKernelCodeT.h"
16 #include "Utils/AMDGPUBaseInfo.h"
17 #include "Utils/AMDKernelCodeTUtils.h"
18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h"
19 #include "llvm/BinaryFormat/ELF.h"
20 #include "llvm/MC/MCAssembler.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCObjectWriter.h"
24 #include "llvm/MC/MCSectionELF.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/AMDGPUMetadata.h"
27 #include "llvm/Support/AMDHSAKernelDescriptor.h"
28 #include "llvm/Support/Casting.h"
29 #include "llvm/Support/FormattedStream.h"
30 #include "llvm/TargetParser/TargetParser.h"
31
32 using namespace llvm;
33 using namespace llvm::AMDGPU;
34
35 //===----------------------------------------------------------------------===//
36 // AMDGPUTargetStreamer
37 //===----------------------------------------------------------------------===//
38
EmitHSAMetadataV3(StringRef HSAMetadataString)39 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) {
40 msgpack::Document HSAMetadataDoc;
41 if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
42 return false;
43 return EmitHSAMetadata(HSAMetadataDoc, false);
44 }
45
getArchNameFromElfMach(unsigned ElfMach)46 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) {
47 AMDGPU::GPUKind AK;
48
49 // clang-format off
50 switch (ElfMach) {
51 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
52 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
53 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break;
54 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break;
55 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break;
56 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break;
57 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break;
58 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break;
59 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break;
60 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break;
61 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break;
62 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
63 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break;
64 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break;
65 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break;
66 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break;
67 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break;
68 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break;
69 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break;
70 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break;
71 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break;
72 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break;
73 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break;
74 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break;
75 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break;
76 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break;
77 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break;
78 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break;
79 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break;
80 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break;
81 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break;
82 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break;
83 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break;
84 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break;
85 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break;
86 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break;
87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break;
88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break;
89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX940: AK = GK_GFX940; break;
90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX941: AK = GK_GFX941; break;
91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX942: AK = GK_GFX942; break;
92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break;
93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break;
94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break;
95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break;
96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break;
97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break;
98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break;
99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break;
100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break;
101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break;
102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036: AK = GK_GFX1036; break;
103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100: AK = GK_GFX1100; break;
104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101: AK = GK_GFX1101; break;
105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102: AK = GK_GFX1102; break;
106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103: AK = GK_GFX1103; break;
107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150: AK = GK_GFX1150; break;
108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151: AK = GK_GFX1151; break;
109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200: AK = GK_GFX1200; break;
110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201: AK = GK_GFX1201; break;
111 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
112 default: AK = GK_NONE; break;
113 }
114 // clang-format on
115
116 StringRef GPUName = getArchNameAMDGCN(AK);
117 if (GPUName != "")
118 return GPUName;
119 return getArchNameR600(AK);
120 }
121
getElfMach(StringRef GPU)122 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) {
123 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU);
124 if (AK == AMDGPU::GPUKind::GK_NONE)
125 AK = parseArchR600(GPU);
126
127 // clang-format off
128 switch (AK) {
129 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600;
130 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630;
131 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880;
132 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670;
133 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710;
134 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730;
135 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770;
136 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR;
137 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS;
138 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER;
139 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD;
140 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO;
141 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS;
142 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS;
143 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN;
144 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS;
145 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600;
146 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601;
147 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602;
148 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700;
149 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701;
150 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702;
151 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703;
152 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704;
153 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705;
154 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801;
155 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802;
156 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803;
157 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805;
158 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810;
159 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900;
160 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902;
161 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904;
162 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906;
163 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908;
164 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909;
165 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A;
166 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C;
167 case GK_GFX940: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX940;
168 case GK_GFX941: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX941;
169 case GK_GFX942: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX942;
170 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010;
171 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011;
172 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012;
173 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013;
174 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030;
175 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031;
176 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032;
177 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033;
178 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034;
179 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035;
180 case GK_GFX1036: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036;
181 case GK_GFX1100: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100;
182 case GK_GFX1101: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101;
183 case GK_GFX1102: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102;
184 case GK_GFX1103: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103;
185 case GK_GFX1150: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150;
186 case GK_GFX1151: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151;
187 case GK_GFX1200: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200;
188 case GK_GFX1201: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201;
189 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE;
190 }
191 // clang-format on
192
193 llvm_unreachable("unknown GPU");
194 }
195
196 //===----------------------------------------------------------------------===//
197 // AMDGPUTargetAsmStreamer
198 //===----------------------------------------------------------------------===//
199
AMDGPUTargetAsmStreamer(MCStreamer & S,formatted_raw_ostream & OS)200 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S,
201 formatted_raw_ostream &OS)
202 : AMDGPUTargetStreamer(S), OS(OS) { }
203
204 // A hook for emitting stuff at the end.
205 // We use it for emitting the accumulated PAL metadata as directives.
206 // The PAL metadata is reset after it is emitted.
finish()207 void AMDGPUTargetAsmStreamer::finish() {
208 std::string S;
209 getPALMetadata()->toString(S);
210 OS << S;
211
212 // Reset the pal metadata so its data will not affect a compilation that
213 // reuses this object.
214 getPALMetadata()->reset();
215 }
216
EmitDirectiveAMDGCNTarget()217 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() {
218 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n";
219 }
220
EmitDirectiveAMDHSACodeObjectVersion(unsigned COV)221 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDHSACodeObjectVersion(
222 unsigned COV) {
223 AMDGPUTargetStreamer::EmitDirectiveAMDHSACodeObjectVersion(COV);
224 OS << "\t.amdhsa_code_object_version " << COV << '\n';
225 }
226
227 void
EmitAMDKernelCodeT(const amd_kernel_code_t & Header)228 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
229 OS << "\t.amd_kernel_code_t\n";
230 dumpAmdKernelCode(&Header, OS, "\t\t");
231 OS << "\t.end_amd_kernel_code_t\n";
232 }
233
EmitAMDGPUSymbolType(StringRef SymbolName,unsigned Type)234 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
235 unsigned Type) {
236 switch (Type) {
237 default: llvm_unreachable("Invalid AMDGPU symbol type");
238 case ELF::STT_AMDGPU_HSA_KERNEL:
239 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
240 break;
241 }
242 }
243
emitAMDGPULDS(MCSymbol * Symbol,unsigned Size,Align Alignment)244 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
245 Align Alignment) {
246 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
247 << Alignment.value() << '\n';
248 }
249
EmitISAVersion()250 bool AMDGPUTargetAsmStreamer::EmitISAVersion() {
251 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n";
252 return true;
253 }
254
EmitHSAMetadata(msgpack::Document & HSAMetadataDoc,bool Strict)255 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
256 msgpack::Document &HSAMetadataDoc, bool Strict) {
257 HSAMD::V3::MetadataVerifier Verifier(Strict);
258 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
259 return false;
260
261 std::string HSAMetadataString;
262 raw_string_ostream StrOS(HSAMetadataString);
263 HSAMetadataDoc.toYAML(StrOS);
264
265 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n';
266 OS << StrOS.str() << '\n';
267 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
268 return true;
269 }
270
EmitCodeEnd(const MCSubtargetInfo & STI)271 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
272 const uint32_t Encoded_s_code_end = 0xbf9f0000;
273 const uint32_t Encoded_s_nop = 0xbf800000;
274 uint32_t Encoded_pad = Encoded_s_code_end;
275
276 // Instruction cache line size in bytes.
277 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
278 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
279
280 // Extra padding amount in bytes to support prefetch mode 3.
281 unsigned FillSize = 3 * CacheLineSize;
282
283 if (AMDGPU::isGFX90A(STI)) {
284 Encoded_pad = Encoded_s_nop;
285 FillSize = 16 * CacheLineSize;
286 }
287
288 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
289 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
290 return true;
291 }
292
EmitAmdhsaKernelDescriptor(const MCSubtargetInfo & STI,StringRef KernelName,const amdhsa::kernel_descriptor_t & KD,uint64_t NextVGPR,uint64_t NextSGPR,bool ReserveVCC,bool ReserveFlatScr)293 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
294 const MCSubtargetInfo &STI, StringRef KernelName,
295 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
296 bool ReserveVCC, bool ReserveFlatScr) {
297 IsaVersion IVersion = getIsaVersion(STI.getCPU());
298
299 OS << "\t.amdhsa_kernel " << KernelName << '\n';
300
301 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
302 STREAM << "\t\t" << DIRECTIVE << " " \
303 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
304
305 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
306 << '\n';
307 OS << "\t\t.amdhsa_private_segment_fixed_size "
308 << KD.private_segment_fixed_size << '\n';
309 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n';
310
311 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD,
312 compute_pgm_rsrc2,
313 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT);
314
315 if (!hasArchitectedFlatScratch(STI))
316 PRINT_FIELD(
317 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
318 kernel_code_properties,
319 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
320 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
321 kernel_code_properties,
322 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
323 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
324 kernel_code_properties,
325 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
326 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
327 kernel_code_properties,
328 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
329 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
330 kernel_code_properties,
331 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
332 if (!hasArchitectedFlatScratch(STI))
333 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
334 kernel_code_properties,
335 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
336 if (hasKernargPreload(STI)) {
337 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_preload_length ", KD,
338 kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_LENGTH);
339 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_preload_offset ", KD,
340 kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_OFFSET);
341 }
342 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
343 kernel_code_properties,
344 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
345 if (IVersion.Major >= 10)
346 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD,
347 kernel_code_properties,
348 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
349 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5)
350 PRINT_FIELD(OS, ".amdhsa_uses_dynamic_stack", KD, kernel_code_properties,
351 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
352 PRINT_FIELD(OS,
353 (hasArchitectedFlatScratch(STI)
354 ? ".amdhsa_enable_private_segment"
355 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"),
356 KD, compute_pgm_rsrc2,
357 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
358 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
359 compute_pgm_rsrc2,
360 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
361 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
362 compute_pgm_rsrc2,
363 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
364 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
365 compute_pgm_rsrc2,
366 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
367 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
368 compute_pgm_rsrc2,
369 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
370 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
371 compute_pgm_rsrc2,
372 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
373
374 // These directives are required.
375 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
376 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
377
378 if (AMDGPU::isGFX90A(STI))
379 OS << "\t\t.amdhsa_accum_offset " <<
380 (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3,
381 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4
382 << '\n';
383
384 if (!ReserveVCC)
385 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
386 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI))
387 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
388
389 switch (CodeObjectVersion) {
390 default:
391 break;
392 case AMDGPU::AMDHSA_COV4:
393 case AMDGPU::AMDHSA_COV5:
394 if (getTargetID()->isXnackSupported())
395 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n';
396 break;
397 }
398
399 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
400 compute_pgm_rsrc1,
401 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
402 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
403 compute_pgm_rsrc1,
404 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
405 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
406 compute_pgm_rsrc1,
407 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
408 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
409 compute_pgm_rsrc1,
410 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
411 if (IVersion.Major < 12) {
412 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, compute_pgm_rsrc1,
413 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP);
414 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, compute_pgm_rsrc1,
415 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE);
416 }
417 if (IVersion.Major >= 9)
418 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
419 compute_pgm_rsrc1,
420 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL);
421 if (AMDGPU::isGFX90A(STI))
422 PRINT_FIELD(OS, ".amdhsa_tg_split", KD,
423 compute_pgm_rsrc3,
424 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT);
425 if (IVersion.Major >= 10) {
426 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD,
427 compute_pgm_rsrc1,
428 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE);
429 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD,
430 compute_pgm_rsrc1,
431 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED);
432 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD,
433 compute_pgm_rsrc1,
434 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS);
435 }
436 if (IVersion.Major >= 10 && IVersion.Major < 12) {
437 PRINT_FIELD(OS, ".amdhsa_shared_vgpr_count", KD, compute_pgm_rsrc3,
438 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT);
439 }
440 if (IVersion.Major >= 12)
441 PRINT_FIELD(OS, ".amdhsa_round_robin_scheduling", KD, compute_pgm_rsrc1,
442 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN);
443 PRINT_FIELD(
444 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
445 compute_pgm_rsrc2,
446 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
447 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
448 compute_pgm_rsrc2,
449 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
450 PRINT_FIELD(
451 OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
452 compute_pgm_rsrc2,
453 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
454 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
455 compute_pgm_rsrc2,
456 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
457 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
458 compute_pgm_rsrc2,
459 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
460 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
461 compute_pgm_rsrc2,
462 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
463 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
464 compute_pgm_rsrc2,
465 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
466 #undef PRINT_FIELD
467
468 OS << "\t.end_amdhsa_kernel\n";
469 }
470
471 //===----------------------------------------------------------------------===//
472 // AMDGPUTargetELFStreamer
473 //===----------------------------------------------------------------------===//
474
AMDGPUTargetELFStreamer(MCStreamer & S,const MCSubtargetInfo & STI)475 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S,
476 const MCSubtargetInfo &STI)
477 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {}
478
getStreamer()479 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
480 return static_cast<MCELFStreamer &>(Streamer);
481 }
482
483 // A hook for emitting stuff at the end.
484 // We use it for emitting the accumulated PAL metadata as a .note record.
485 // The PAL metadata is reset after it is emitted.
finish()486 void AMDGPUTargetELFStreamer::finish() {
487 MCAssembler &MCA = getStreamer().getAssembler();
488 MCA.setELFHeaderEFlags(getEFlags());
489 MCA.getWriter().setOverrideABIVersion(
490 getELFABIVersion(STI.getTargetTriple(), CodeObjectVersion));
491
492 std::string Blob;
493 const char *Vendor = getPALMetadata()->getVendor();
494 unsigned Type = getPALMetadata()->getType();
495 getPALMetadata()->toBlob(Type, Blob);
496 if (Blob.empty())
497 return;
498 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
499 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
500
501 // Reset the pal metadata so its data will not affect a compilation that
502 // reuses this object.
503 getPALMetadata()->reset();
504 }
505
EmitNote(StringRef Name,const MCExpr * DescSZ,unsigned NoteType,function_ref<void (MCELFStreamer &)> EmitDesc)506 void AMDGPUTargetELFStreamer::EmitNote(
507 StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
508 function_ref<void(MCELFStreamer &)> EmitDesc) {
509 auto &S = getStreamer();
510 auto &Context = S.getContext();
511
512 auto NameSZ = Name.size() + 1;
513
514 unsigned NoteFlags = 0;
515 // TODO Apparently, this is currently needed for OpenCL as mentioned in
516 // https://reviews.llvm.org/D74995
517 if (isHsaAbi(STI))
518 NoteFlags = ELF::SHF_ALLOC;
519
520 S.pushSection();
521 S.switchSection(
522 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
523 S.emitInt32(NameSZ); // namesz
524 S.emitValue(DescSZ, 4); // descz
525 S.emitInt32(NoteType); // type
526 S.emitBytes(Name); // name
527 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
528 EmitDesc(S); // desc
529 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
530 S.popSection();
531 }
532
getEFlags()533 unsigned AMDGPUTargetELFStreamer::getEFlags() {
534 switch (STI.getTargetTriple().getArch()) {
535 default:
536 llvm_unreachable("Unsupported Arch");
537 case Triple::r600:
538 return getEFlagsR600();
539 case Triple::amdgcn:
540 return getEFlagsAMDGCN();
541 }
542 }
543
getEFlagsR600()544 unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
545 assert(STI.getTargetTriple().getArch() == Triple::r600);
546
547 return getElfMach(STI.getCPU());
548 }
549
getEFlagsAMDGCN()550 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
551 assert(STI.getTargetTriple().getArch() == Triple::amdgcn);
552
553 switch (STI.getTargetTriple().getOS()) {
554 default:
555 // TODO: Why are some tests have "mingw" listed as OS?
556 // llvm_unreachable("Unsupported OS");
557 case Triple::UnknownOS:
558 return getEFlagsUnknownOS();
559 case Triple::AMDHSA:
560 return getEFlagsAMDHSA();
561 case Triple::AMDPAL:
562 return getEFlagsAMDPAL();
563 case Triple::Mesa3D:
564 return getEFlagsMesa3D();
565 }
566 }
567
getEFlagsUnknownOS()568 unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
569 // TODO: Why are some tests have "mingw" listed as OS?
570 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS);
571
572 return getEFlagsV3();
573 }
574
getEFlagsAMDHSA()575 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
576 assert(isHsaAbi(STI));
577
578 return getEFlagsV4();
579 }
580
getEFlagsAMDPAL()581 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
582 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL);
583
584 return getEFlagsV3();
585 }
586
getEFlagsMesa3D()587 unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
588 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D);
589
590 return getEFlagsV3();
591 }
592
getEFlagsV3()593 unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
594 unsigned EFlagsV3 = 0;
595
596 // mach.
597 EFlagsV3 |= getElfMach(STI.getCPU());
598
599 // xnack.
600 if (getTargetID()->isXnackOnOrAny())
601 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3;
602 // sramecc.
603 if (getTargetID()->isSramEccOnOrAny())
604 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3;
605
606 return EFlagsV3;
607 }
608
getEFlagsV4()609 unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
610 unsigned EFlagsV4 = 0;
611
612 // mach.
613 EFlagsV4 |= getElfMach(STI.getCPU());
614
615 // xnack.
616 switch (getTargetID()->getXnackSetting()) {
617 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported:
618 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4;
619 break;
620 case AMDGPU::IsaInfo::TargetIDSetting::Any:
621 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4;
622 break;
623 case AMDGPU::IsaInfo::TargetIDSetting::Off:
624 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4;
625 break;
626 case AMDGPU::IsaInfo::TargetIDSetting::On:
627 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4;
628 break;
629 }
630 // sramecc.
631 switch (getTargetID()->getSramEccSetting()) {
632 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported:
633 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4;
634 break;
635 case AMDGPU::IsaInfo::TargetIDSetting::Any:
636 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4;
637 break;
638 case AMDGPU::IsaInfo::TargetIDSetting::Off:
639 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4;
640 break;
641 case AMDGPU::IsaInfo::TargetIDSetting::On:
642 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4;
643 break;
644 }
645
646 return EFlagsV4;
647 }
648
EmitDirectiveAMDGCNTarget()649 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {}
650
651 void
EmitAMDKernelCodeT(const amd_kernel_code_t & Header)652 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
653
654 MCStreamer &OS = getStreamer();
655 OS.pushSection();
656 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header)));
657 OS.popSection();
658 }
659
EmitAMDGPUSymbolType(StringRef SymbolName,unsigned Type)660 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
661 unsigned Type) {
662 MCSymbolELF *Symbol = cast<MCSymbolELF>(
663 getStreamer().getContext().getOrCreateSymbol(SymbolName));
664 Symbol->setType(Type);
665 }
666
emitAMDGPULDS(MCSymbol * Symbol,unsigned Size,Align Alignment)667 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
668 Align Alignment) {
669 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
670 SymbolELF->setType(ELF::STT_OBJECT);
671
672 if (!SymbolELF->isBindingSet()) {
673 SymbolELF->setBinding(ELF::STB_GLOBAL);
674 SymbolELF->setExternal(true);
675 }
676
677 if (SymbolELF->declareCommon(Size, Alignment, true)) {
678 report_fatal_error("Symbol: " + Symbol->getName() +
679 " redeclared as different type");
680 }
681
682 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
683 SymbolELF->setSize(MCConstantExpr::create(Size, getContext()));
684 }
685
EmitISAVersion()686 bool AMDGPUTargetELFStreamer::EmitISAVersion() {
687 // Create two labels to mark the beginning and end of the desc field
688 // and a MCExpr to calculate the size of the desc field.
689 auto &Context = getContext();
690 auto *DescBegin = Context.createTempSymbol();
691 auto *DescEnd = Context.createTempSymbol();
692 auto *DescSZ = MCBinaryExpr::createSub(
693 MCSymbolRefExpr::create(DescEnd, Context),
694 MCSymbolRefExpr::create(DescBegin, Context), Context);
695
696 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME,
697 [&](MCELFStreamer &OS) {
698 OS.emitLabel(DescBegin);
699 OS.emitBytes(getTargetID()->toString());
700 OS.emitLabel(DescEnd);
701 });
702 return true;
703 }
704
EmitHSAMetadata(msgpack::Document & HSAMetadataDoc,bool Strict)705 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
706 bool Strict) {
707 HSAMD::V3::MetadataVerifier Verifier(Strict);
708 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
709 return false;
710
711 std::string HSAMetadataString;
712 HSAMetadataDoc.writeToBlob(HSAMetadataString);
713
714 // Create two labels to mark the beginning and end of the desc field
715 // and a MCExpr to calculate the size of the desc field.
716 auto &Context = getContext();
717 auto *DescBegin = Context.createTempSymbol();
718 auto *DescEnd = Context.createTempSymbol();
719 auto *DescSZ = MCBinaryExpr::createSub(
720 MCSymbolRefExpr::create(DescEnd, Context),
721 MCSymbolRefExpr::create(DescBegin, Context), Context);
722
723 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA,
724 [&](MCELFStreamer &OS) {
725 OS.emitLabel(DescBegin);
726 OS.emitBytes(HSAMetadataString);
727 OS.emitLabel(DescEnd);
728 });
729 return true;
730 }
731
EmitKernargPreloadHeader(const MCSubtargetInfo & STI)732 bool AMDGPUTargetAsmStreamer::EmitKernargPreloadHeader(
733 const MCSubtargetInfo &STI) {
734 for (int i = 0; i < 64; ++i) {
735 OS << "\ts_nop 0\n";
736 }
737 return true;
738 }
739
EmitKernargPreloadHeader(const MCSubtargetInfo & STI)740 bool AMDGPUTargetELFStreamer::EmitKernargPreloadHeader(
741 const MCSubtargetInfo &STI) {
742 const uint32_t Encoded_s_nop = 0xbf800000;
743 MCStreamer &OS = getStreamer();
744 for (int i = 0; i < 64; ++i) {
745 OS.emitInt32(Encoded_s_nop);
746 }
747 return true;
748 }
749
EmitCodeEnd(const MCSubtargetInfo & STI)750 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
751 const uint32_t Encoded_s_code_end = 0xbf9f0000;
752 const uint32_t Encoded_s_nop = 0xbf800000;
753 uint32_t Encoded_pad = Encoded_s_code_end;
754
755 // Instruction cache line size in bytes.
756 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
757 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
758
759 // Extra padding amount in bytes to support prefetch mode 3.
760 unsigned FillSize = 3 * CacheLineSize;
761
762 if (AMDGPU::isGFX90A(STI)) {
763 Encoded_pad = Encoded_s_nop;
764 FillSize = 16 * CacheLineSize;
765 }
766
767 MCStreamer &OS = getStreamer();
768 OS.pushSection();
769 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4);
770 for (unsigned I = 0; I < FillSize; I += 4)
771 OS.emitInt32(Encoded_pad);
772 OS.popSection();
773 return true;
774 }
775
EmitAmdhsaKernelDescriptor(const MCSubtargetInfo & STI,StringRef KernelName,const amdhsa::kernel_descriptor_t & KernelDescriptor,uint64_t NextVGPR,uint64_t NextSGPR,bool ReserveVCC,bool ReserveFlatScr)776 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
777 const MCSubtargetInfo &STI, StringRef KernelName,
778 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
779 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) {
780 auto &Streamer = getStreamer();
781 auto &Context = Streamer.getContext();
782
783 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
784 Context.getOrCreateSymbol(Twine(KernelName)));
785 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
786 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
787
788 // Copy kernel descriptor symbol's binding, other and visibility from the
789 // kernel code symbol.
790 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding());
791 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther());
792 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility());
793 // Kernel descriptor symbol's type and size are fixed.
794 KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
795 KernelDescriptorSymbol->setSize(
796 MCConstantExpr::create(sizeof(KernelDescriptor), Context));
797
798 // The visibility of the kernel code symbol must be protected or less to allow
799 // static relocations from the kernel descriptor to be used.
800 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
801 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
802
803 Streamer.emitLabel(KernelDescriptorSymbol);
804 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size);
805 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size);
806 Streamer.emitInt32(KernelDescriptor.kernarg_size);
807
808 for (uint8_t Res : KernelDescriptor.reserved0)
809 Streamer.emitInt8(Res);
810
811 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
812 // expression being created is:
813 // (start of kernel code) - (start of kernel descriptor)
814 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
815 Streamer.emitValue(MCBinaryExpr::createSub(
816 MCSymbolRefExpr::create(
817 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
818 MCSymbolRefExpr::create(
819 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
820 Context),
821 sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
822 for (uint8_t Res : KernelDescriptor.reserved1)
823 Streamer.emitInt8(Res);
824 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3);
825 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1);
826 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2);
827 Streamer.emitInt16(KernelDescriptor.kernel_code_properties);
828 Streamer.emitInt16(KernelDescriptor.kernarg_preload);
829 for (uint8_t Res : KernelDescriptor.reserved3)
830 Streamer.emitInt8(Res);
831 }
832