10eae32dcSDimitry Andric //===- MachineSSAContext.cpp ------------------------------------*- C++ -*-===// 20eae32dcSDimitry Andric // 30eae32dcSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40eae32dcSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50eae32dcSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60eae32dcSDimitry Andric // 70eae32dcSDimitry Andric //===----------------------------------------------------------------------===// 80eae32dcSDimitry Andric /// \file 90eae32dcSDimitry Andric /// 100eae32dcSDimitry Andric /// This file defines a specialization of the GenericSSAContext<X> 110eae32dcSDimitry Andric /// template class for Machine IR. 120eae32dcSDimitry Andric /// 130eae32dcSDimitry Andric //===----------------------------------------------------------------------===// 140eae32dcSDimitry Andric 150eae32dcSDimitry Andric #include "llvm/CodeGen/MachineSSAContext.h" 160eae32dcSDimitry Andric #include "llvm/CodeGen/MachineBasicBlock.h" 1781ad6265SDimitry Andric #include "llvm/CodeGen/MachineFunction.h" 180eae32dcSDimitry Andric #include "llvm/CodeGen/MachineInstr.h" 1981ad6265SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h" 200eae32dcSDimitry Andric #include "llvm/Support/raw_ostream.h" 210eae32dcSDimitry Andric 220eae32dcSDimitry Andric using namespace llvm; 230eae32dcSDimitry Andric 240eae32dcSDimitry Andric void MachineSSAContext::setFunction(MachineFunction &Fn) { 250eae32dcSDimitry Andric MF = &Fn; 260eae32dcSDimitry Andric RegInfo = &MF->getRegInfo(); 270eae32dcSDimitry Andric } 280eae32dcSDimitry Andric 29bdd1243dSDimitry Andric MachineBasicBlock *MachineSSAContext::getEntryBlock(MachineFunction &F) { 30bdd1243dSDimitry Andric return &F.front(); 31bdd1243dSDimitry Andric } 32bdd1243dSDimitry Andric 33bdd1243dSDimitry Andric void MachineSSAContext::appendBlockTerms( 34bdd1243dSDimitry Andric SmallVectorImpl<const MachineInstr *> &terms, 35bdd1243dSDimitry Andric const MachineBasicBlock &block) { 36bdd1243dSDimitry Andric for (auto &T : block.terminators()) 37bdd1243dSDimitry Andric terms.push_back(&T); 38bdd1243dSDimitry Andric } 39bdd1243dSDimitry Andric 40bdd1243dSDimitry Andric void MachineSSAContext::appendBlockDefs(SmallVectorImpl<Register> &defs, 41bdd1243dSDimitry Andric const MachineBasicBlock &block) { 42bdd1243dSDimitry Andric for (const MachineInstr &instr : block.instrs()) { 43*fe013be4SDimitry Andric for (const MachineOperand &op : instr.all_defs()) 44bdd1243dSDimitry Andric defs.push_back(op.getReg()); 45bdd1243dSDimitry Andric } 46bdd1243dSDimitry Andric } 47bdd1243dSDimitry Andric 48bdd1243dSDimitry Andric /// Get the defining block of a value. 49bdd1243dSDimitry Andric MachineBasicBlock *MachineSSAContext::getDefBlock(Register value) const { 50bdd1243dSDimitry Andric if (!value) 51bdd1243dSDimitry Andric return nullptr; 52bdd1243dSDimitry Andric return RegInfo->getVRegDef(value)->getParent(); 53bdd1243dSDimitry Andric } 54bdd1243dSDimitry Andric 55*fe013be4SDimitry Andric bool MachineSSAContext::isConstantOrUndefValuePhi(const MachineInstr &Phi) { 56bdd1243dSDimitry Andric return Phi.isConstantValuePHI(); 57bdd1243dSDimitry Andric } 58bdd1243dSDimitry Andric 59bdd1243dSDimitry Andric Printable MachineSSAContext::print(const MachineBasicBlock *Block) const { 60bdd1243dSDimitry Andric if (!Block) 61bdd1243dSDimitry Andric return Printable([](raw_ostream &Out) { Out << "<nullptr>"; }); 620eae32dcSDimitry Andric return Printable([Block](raw_ostream &Out) { Block->printName(Out); }); 630eae32dcSDimitry Andric } 640eae32dcSDimitry Andric 65bdd1243dSDimitry Andric Printable MachineSSAContext::print(const MachineInstr *I) const { 660eae32dcSDimitry Andric return Printable([I](raw_ostream &Out) { I->print(Out); }); 670eae32dcSDimitry Andric } 680eae32dcSDimitry Andric 690eae32dcSDimitry Andric Printable MachineSSAContext::print(Register Value) const { 700eae32dcSDimitry Andric auto *MRI = RegInfo; 710eae32dcSDimitry Andric return Printable([MRI, Value](raw_ostream &Out) { 720eae32dcSDimitry Andric Out << printReg(Value, MRI->getTargetRegisterInfo(), 0, MRI); 730eae32dcSDimitry Andric 740eae32dcSDimitry Andric if (Value) { 750eae32dcSDimitry Andric // Try to print the definition. 760eae32dcSDimitry Andric if (auto *Instr = MRI->getUniqueVRegDef(Value)) { 770eae32dcSDimitry Andric Out << ": "; 780eae32dcSDimitry Andric Instr->print(Out); 790eae32dcSDimitry Andric } 800eae32dcSDimitry Andric } 810eae32dcSDimitry Andric }); 820eae32dcSDimitry Andric } 83