1*0b57cec5SDimitry Andric //===-- LiveStacks.cpp - Live Stack Slot Analysis -------------------------===//
2*0b57cec5SDimitry Andric //
3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0b57cec5SDimitry Andric //
7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
8*0b57cec5SDimitry Andric //
9*0b57cec5SDimitry Andric // This file implements the live stack slot analysis pass. It is analogous to
10*0b57cec5SDimitry Andric // live interval analysis except it's analyzing liveness of stack slots rather
11*0b57cec5SDimitry Andric // than registers.
12*0b57cec5SDimitry Andric //
13*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
14*0b57cec5SDimitry Andric 
15*0b57cec5SDimitry Andric #include "llvm/CodeGen/LiveStacks.h"
16*0b57cec5SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h"
17*0b57cec5SDimitry Andric #include "llvm/CodeGen/TargetSubtargetInfo.h"
18*0b57cec5SDimitry Andric #include "llvm/InitializePasses.h"
19*0b57cec5SDimitry Andric using namespace llvm;
20*0b57cec5SDimitry Andric 
21*0b57cec5SDimitry Andric #define DEBUG_TYPE "livestacks"
22*0b57cec5SDimitry Andric 
23*0b57cec5SDimitry Andric char LiveStacks::ID = 0;
24*0b57cec5SDimitry Andric INITIALIZE_PASS_BEGIN(LiveStacks, DEBUG_TYPE,
25*0b57cec5SDimitry Andric                 "Live Stack Slot Analysis", false, false)
26*0b57cec5SDimitry Andric INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
27*0b57cec5SDimitry Andric INITIALIZE_PASS_END(LiveStacks, DEBUG_TYPE,
28*0b57cec5SDimitry Andric                 "Live Stack Slot Analysis", false, false)
29*0b57cec5SDimitry Andric 
30*0b57cec5SDimitry Andric char &llvm::LiveStacksID = LiveStacks::ID;
31*0b57cec5SDimitry Andric 
getAnalysisUsage(AnalysisUsage & AU) const32*0b57cec5SDimitry Andric void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
33*0b57cec5SDimitry Andric   AU.setPreservesAll();
34*0b57cec5SDimitry Andric   AU.addPreserved<SlotIndexes>();
35*0b57cec5SDimitry Andric   AU.addRequiredTransitive<SlotIndexes>();
36*0b57cec5SDimitry Andric   MachineFunctionPass::getAnalysisUsage(AU);
37*0b57cec5SDimitry Andric }
38*0b57cec5SDimitry Andric 
releaseMemory()39*0b57cec5SDimitry Andric void LiveStacks::releaseMemory() {
40*0b57cec5SDimitry Andric   // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
41*0b57cec5SDimitry Andric   VNInfoAllocator.Reset();
42*0b57cec5SDimitry Andric   S2IMap.clear();
43*0b57cec5SDimitry Andric   S2RCMap.clear();
44*0b57cec5SDimitry Andric }
45*0b57cec5SDimitry Andric 
runOnMachineFunction(MachineFunction & MF)46*0b57cec5SDimitry Andric bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
47*0b57cec5SDimitry Andric   TRI = MF.getSubtarget().getRegisterInfo();
48*0b57cec5SDimitry Andric   // FIXME: No analysis is being done right now. We are relying on the
49*0b57cec5SDimitry Andric   // register allocators to provide the information.
50*0b57cec5SDimitry Andric   return false;
51*0b57cec5SDimitry Andric }
52*0b57cec5SDimitry Andric 
53*0b57cec5SDimitry Andric LiveInterval &
getOrCreateInterval(int Slot,const TargetRegisterClass * RC)54*0b57cec5SDimitry Andric LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
55*0b57cec5SDimitry Andric   assert(Slot >= 0 && "Spill slot indice must be >= 0");
56*0b57cec5SDimitry Andric   SS2IntervalMap::iterator I = S2IMap.find(Slot);
57*0b57cec5SDimitry Andric   if (I == S2IMap.end()) {
58*0b57cec5SDimitry Andric     I = S2IMap
59*0b57cec5SDimitry Andric             .emplace(
60*0b57cec5SDimitry Andric                 std::piecewise_construct, std::forward_as_tuple(Slot),
61*0b57cec5SDimitry Andric                 std::forward_as_tuple(Register::index2StackSlot(Slot), 0.0F))
62*0b57cec5SDimitry Andric             .first;
63*0b57cec5SDimitry Andric     S2RCMap.insert(std::make_pair(Slot, RC));
64*0b57cec5SDimitry Andric   } else {
65*0b57cec5SDimitry Andric     // Use the largest common subclass register class.
66*0b57cec5SDimitry Andric     const TargetRegisterClass *OldRC = S2RCMap[Slot];
67*0b57cec5SDimitry Andric     S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
68*0b57cec5SDimitry Andric   }
69*0b57cec5SDimitry Andric   return I->second;
70*0b57cec5SDimitry Andric }
71*0b57cec5SDimitry Andric 
72*0b57cec5SDimitry Andric /// print - Implement the dump method.
print(raw_ostream & OS,const Module *) const73*0b57cec5SDimitry Andric void LiveStacks::print(raw_ostream &OS, const Module*) const {
74*0b57cec5SDimitry Andric 
75*0b57cec5SDimitry Andric   OS << "********** INTERVALS **********\n";
76*0b57cec5SDimitry Andric   for (const_iterator I = begin(), E = end(); I != E; ++I) {
77*0b57cec5SDimitry Andric     I->second.print(OS);
78*0b57cec5SDimitry Andric     int Slot = I->first;
79*0b57cec5SDimitry Andric     const TargetRegisterClass *RC = getIntervalRegClass(Slot);
80*0b57cec5SDimitry Andric     if (RC)
81*0b57cec5SDimitry Andric       OS << " [" << TRI->getRegClassName(RC) << "]\n";
82*0b57cec5SDimitry Andric     else
83*0b57cec5SDimitry Andric       OS << " [Unknown]\n";
84*0b57cec5SDimitry Andric   }
85*0b57cec5SDimitry Andric }
86*0b57cec5SDimitry Andric