1 /* $OpenBSD: regnum.h,v 1.3 1999/01/27 04:46:06 imp Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1988 University of Utah. 7 * Copyright (c) 1992, 1993 8 * The Regents of the University of California. All rights reserved. 9 * 10 * This code is derived from software contributed to Berkeley by 11 * the Systems Programming Group of the University of Utah Computer 12 * Science Department and Ralph Campbell. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Utah Hdr: reg.h 1.1 90/07/09 39 * @(#)reg.h 8.2 (Berkeley) 1/11/94 40 * JNPR: regnum.h,v 1.6 2007/08/09 11:23:32 katta 41 * $FreeBSD$ 42 */ 43 44 #ifndef _MACHINE_REGNUM_H_ 45 #define _MACHINE_REGNUM_H_ 46 47 /* 48 * Location of the saved registers relative to ZERO. 49 * This must match struct trapframe defined in frame.h exactly. 50 * This must also match regdef.h. 51 */ 52 #define ZERO 0 53 #define AST 1 54 #define V0 2 55 #define V1 3 56 #define A0 4 57 #define A1 5 58 #define A2 6 59 #define A3 7 60 #if defined(__mips_n32) || defined(__mips_n64) 61 #define A4 8 62 #define A5 9 63 #define A6 10 64 #define A7 11 65 #define T0 12 66 #define T1 13 67 #define T2 14 68 #define T3 15 69 #else 70 #define T0 8 71 #define T1 9 72 #define T2 10 73 #define T3 11 74 #define T4 12 75 #define T5 13 76 #define T6 14 77 #define T7 15 78 #endif 79 #define S0 16 80 #define S1 17 81 #define S2 18 82 #define S3 19 83 #define S4 20 84 #define S5 21 85 #define S6 22 86 #define S7 23 87 #define T8 24 88 #define T9 25 89 #define K0 26 90 #define K1 27 91 #define GP 28 92 #define SP 29 93 #define S8 30 94 #define RA 31 95 #define SR 32 96 #define PS SR /* alias for SR */ 97 #define MULLO 33 98 #define MULHI 34 99 #define BADVADDR 35 100 #define CAUSE 36 101 #define PC 37 102 /* 103 * IC is valid only on RM7K and RM9K processors. Access to this is 104 * controlled by IC_INT_REG which defined in kernel config 105 */ 106 #define IC 38 107 #define DUMMY 39 /* for 8 byte alignment */ 108 #define NUMSAVEREGS 40 109 110 /* 111 * Pseudo registers so we save a complete set of registers regardless of 112 * the ABI. See regdef.h for a more complete explanation. 113 */ 114 #if defined(__mips_n32) || defined(__mips_n64) 115 #define TA0 8 116 #define TA1 9 117 #define TA2 10 118 #define TA3 11 119 #else 120 #define TA0 12 121 #define TA1 13 122 #define TA2 14 123 #define TA3 15 124 #endif 125 126 127 /* 128 * Index of FP registers in 'struct frame', counting from the beginning 129 * of the frame (i.e., including the general registers). 130 */ 131 #define FPBASE NUMSAVEREGS 132 #define F0 (FPBASE+0) 133 #define F1 (FPBASE+1) 134 #define F2 (FPBASE+2) 135 #define F3 (FPBASE+3) 136 #define F4 (FPBASE+4) 137 #define F5 (FPBASE+5) 138 #define F6 (FPBASE+6) 139 #define F7 (FPBASE+7) 140 #define F8 (FPBASE+8) 141 #define F9 (FPBASE+9) 142 #define F10 (FPBASE+10) 143 #define F11 (FPBASE+11) 144 #define F12 (FPBASE+12) 145 #define F13 (FPBASE+13) 146 #define F14 (FPBASE+14) 147 #define F15 (FPBASE+15) 148 #define F16 (FPBASE+16) 149 #define F17 (FPBASE+17) 150 #define F18 (FPBASE+18) 151 #define F19 (FPBASE+19) 152 #define F20 (FPBASE+20) 153 #define F21 (FPBASE+21) 154 #define F22 (FPBASE+22) 155 #define F23 (FPBASE+23) 156 #define F24 (FPBASE+24) 157 #define F25 (FPBASE+25) 158 #define F26 (FPBASE+26) 159 #define F27 (FPBASE+27) 160 #define F28 (FPBASE+28) 161 #define F29 (FPBASE+29) 162 #define F30 (FPBASE+30) 163 #define F31 (FPBASE+31) 164 #define FSR (FPBASE+32) 165 #define FIR (FPBASE+33) 166 167 #define NUMFPREGS 34 168 169 #define NREGS (NUMSAVEREGS + NUMFPREGS) 170 171 /* 172 * Index of FP registers in 'struct frame', relative to the base 173 * of the FP registers in frame (i.e., *not* including the general 174 * registers). 175 */ 176 #define F0_NUM (0) 177 #define F1_NUM (1) 178 #define F2_NUM (2) 179 #define F3_NUM (3) 180 #define F4_NUM (4) 181 #define F5_NUM (5) 182 #define F6_NUM (6) 183 #define F7_NUM (7) 184 #define F8_NUM (8) 185 #define F9_NUM (9) 186 #define F10_NUM (10) 187 #define F11_NUM (11) 188 #define F12_NUM (12) 189 #define F13_NUM (13) 190 #define F14_NUM (14) 191 #define F15_NUM (15) 192 #define F16_NUM (16) 193 #define F17_NUM (17) 194 #define F18_NUM (18) 195 #define F19_NUM (19) 196 #define F20_NUM (20) 197 #define F21_NUM (21) 198 #define F22_NUM (22) 199 #define F23_NUM (23) 200 #define F24_NUM (24) 201 #define F25_NUM (25) 202 #define F26_NUM (26) 203 #define F27_NUM (27) 204 #define F28_NUM (28) 205 #define F29_NUM (29) 206 #define F30_NUM (30) 207 #define F31_NUM (31) 208 #define FSR_NUM (32) 209 #define FIR_NUM (33) 210 211 #endif /* !_MACHINE_REGNUM_H_ */ 212