1 /* $OpenBSD: mips_opcode.h,v 1.2 1999/01/27 04:46:05 imp Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)mips_opcode.h 8.1 (Berkeley) 6/10/93 35 * JNPR: mips_opcode.h,v 1.1 2006/08/07 05:38:57 katta 36 * $FreeBSD$ 37 */ 38 39 #ifndef _MACHINE_MIPS_OPCODE_H_ 40 #define _MACHINE_MIPS_OPCODE_H_ 41 42 /* 43 * Define the instruction formats and opcode values for the 44 * MIPS instruction set. 45 */ 46 #include <machine/endian.h> 47 48 /* 49 * Define the instruction formats. 50 */ 51 typedef union { 52 unsigned word; 53 54 #if BYTE_ORDER == BIG_ENDIAN 55 struct { 56 unsigned op: 6; 57 unsigned rs: 5; 58 unsigned rt: 5; 59 unsigned imm: 16; 60 } IType; 61 62 struct { 63 unsigned op: 6; 64 unsigned target: 26; 65 } JType; 66 67 struct { 68 unsigned op: 6; 69 unsigned rs: 5; 70 unsigned rt: 5; 71 unsigned rd: 5; 72 unsigned shamt: 5; 73 unsigned func: 6; 74 } RType; 75 76 struct { 77 unsigned op: 6; /* always '0x11' */ 78 unsigned : 1; /* always '1' */ 79 unsigned fmt: 4; 80 unsigned ft: 5; 81 unsigned fs: 5; 82 unsigned fd: 5; 83 unsigned func: 6; 84 } FRType; 85 #endif 86 #if BYTE_ORDER == LITTLE_ENDIAN 87 struct { 88 unsigned imm: 16; 89 unsigned rt: 5; 90 unsigned rs: 5; 91 unsigned op: 6; 92 } IType; 93 94 struct { 95 unsigned target: 26; 96 unsigned op: 6; 97 } JType; 98 99 struct { 100 unsigned func: 6; 101 unsigned shamt: 5; 102 unsigned rd: 5; 103 unsigned rt: 5; 104 unsigned rs: 5; 105 unsigned op: 6; 106 } RType; 107 108 struct { 109 unsigned func: 6; 110 unsigned fd: 5; 111 unsigned fs: 5; 112 unsigned ft: 5; 113 unsigned fmt: 4; 114 unsigned : 1; /* always '1' */ 115 unsigned op: 6; /* always '0x11' */ 116 } FRType; 117 #endif 118 } InstFmt; 119 120 /* instruction field decoding macros */ 121 #define MIPS_INST_OPCODE(val) (val >> 26) 122 #define MIPS_INST_RS(val) ((val & 0x03e00000) >> 21) 123 #define MIPS_INST_RT(val) ((val & 0x001f0000) >> 16) 124 #define MIPS_INST_IMM(val) ((val & 0x0000ffff)) 125 126 #define MIPS_INST_RD(val) ((val & 0x0000f800) >> 11) 127 #define MIPS_INST_SA(val) ((val & 0x000007c0) >> 6) 128 #define MIPS_INST_FUNC(val) (val & 0x0000003f) 129 130 #define MIPS_INST_INDEX(val) (val & 0x03ffffff) 131 132 /* 133 * the mips opcode and function table use a 3bit row and 3bit col 134 * number we define the following macro for easy transcribing 135 */ 136 137 #define MIPS_OPCODE(r, c) (((r & 0x07) << 3) | (c & 0x07)) 138 139 140 /* 141 * Values for the 'op' field. 142 */ 143 #define OP_SPECIAL 000 144 #define OP_BCOND 001 145 #define OP_J 002 146 #define OP_JAL 003 147 #define OP_BEQ 004 148 #define OP_BNE 005 149 #define OP_BLEZ 006 150 #define OP_BGTZ 007 151 152 #define OP_REGIMM OP_BCOND 153 154 #define OP_ADDI 010 155 #define OP_ADDIU 011 156 #define OP_SLTI 012 157 #define OP_SLTIU 013 158 #define OP_ANDI 014 159 #define OP_ORI 015 160 #define OP_XORI 016 161 #define OP_LUI 017 162 163 #define OP_COP0 020 164 #define OP_COP1 021 165 #define OP_COP2 022 166 #define OP_COP3 023 167 #define OP_BEQL 024 168 #define OP_BNEL 025 169 #define OP_BLEZL 026 170 #define OP_BGTZL 027 171 172 #define OP_COP1X OP_COP3 173 174 #define OP_DADDI 030 175 #define OP_DADDIU 031 176 #define OP_LDL 032 177 #define OP_LDR 033 178 179 #define OP_LB 040 180 #define OP_LH 041 181 #define OP_LWL 042 182 #define OP_LW 043 183 #define OP_LBU 044 184 #define OP_LHU 045 185 #define OP_LWR 046 186 #define OP_LWU 047 187 188 #define OP_SB 050 189 #define OP_SH 051 190 #define OP_SWL 052 191 #define OP_SW 053 192 #define OP_SDL 054 193 #define OP_SDR 055 194 #define OP_SWR 056 195 #define OP_CACHE 057 196 197 #define OP_LL 060 198 #define OP_LWC1 061 199 #define OP_LWC2 062 200 #define OP_LWC3 063 201 #define OP_LLD 064 202 #define OP_LDC1 065 203 #define OP_LDC2 066 204 #define OP_LD 067 205 206 #define OP_PREF OP_LWC3 207 208 #define OP_SC 070 209 #define OP_SWC1 071 210 #define OP_SWC2 072 211 #define OP_SWC3 073 212 #define OP_SCD 074 213 #define OP_SDC1 075 214 #define OP_SDC2 076 215 #define OP_SD 077 216 217 /* 218 * Values for the 'func' field when 'op' == OP_SPECIAL. 219 */ 220 #define OP_SLL 000 221 #define OP_MOVCI 001 222 #define OP_SRL 002 223 #define OP_SRA 003 224 #define OP_SLLV 004 225 #define OP_SRLV 006 226 #define OP_SRAV 007 227 228 #define OP_F_SLL OP_SLL 229 #define OP_F_MOVCI OP_MOVCI 230 #define OP_F_SRL OP_SRL 231 #define OP_F_SRA OP_SRA 232 #define OP_F_SLLV OP_SLLV 233 #define OP_F_SRLV OP_SRLV 234 #define OP_F_SRAV OP_SRAV 235 236 #define OP_JR 010 237 #define OP_JALR 011 238 #define OP_MOVZ 012 239 #define OP_MOVN 013 240 #define OP_SYSCALL 014 241 #define OP_BREAK 015 242 #define OP_SYNC 017 243 244 #define OP_F_JR OP_JR 245 #define OP_F_JALR OP_JALR 246 #define OP_F_MOVZ OP_MOVZ 247 #define OP_F_MOVN OP_MOVN 248 #define OP_F_SYSCALL OP_SYSCALL 249 #define OP_F_BREAK OP_BREAK 250 #define OP_F_SYNC OP_SYNC 251 252 #define OP_MFHI 020 253 #define OP_MTHI 021 254 #define OP_MFLO 022 255 #define OP_MTLO 023 256 #define OP_DSLLV 024 257 #define OP_DSRLV 026 258 #define OP_DSRAV 027 259 260 #define OP_F_MFHI OP_MFHI 261 #define OP_F_MTHI OP_MTHI 262 #define OP_F_MFLO OP_MFLO 263 #define OP_F_MTLO OP_MTLO 264 #define OP_F_DSLLV OP_DSLLV 265 #define OP_F_DSRLV OP_DSRLV 266 #define OP_F_DSRAV OP_DSRAV 267 268 #define OP_MULT 030 269 #define OP_MULTU 031 270 #define OP_DIV 032 271 #define OP_DIVU 033 272 #define OP_DMULT 034 273 #define OP_DMULTU 035 274 #define OP_DDIV 036 275 #define OP_DDIVU 037 276 277 #define OP_F_MULT OP_MULT 278 #define OP_F_MULTU OP_MULTU 279 #define OP_F_DIV OP_DIV 280 #define OP_F_DIVU OP_DIVU 281 #define OP_F_DMULT OP_DMULT 282 #define OP_F_DMULTU OP_DMULTU 283 #define OP_F_DDIV OP_DDIV 284 #define OP_F_DDIVU OP_DDIVU 285 286 #define OP_ADD 040 287 #define OP_ADDU 041 288 #define OP_SUB 042 289 #define OP_SUBU 043 290 #define OP_AND 044 291 #define OP_OR 045 292 #define OP_XOR 046 293 #define OP_NOR 047 294 295 #define OP_F_ADD OP_ADD 296 #define OP_F_ADDU OP_ADDU 297 #define OP_F_SUB OP_SUB 298 #define OP_F_SUBU OP_SUBU 299 #define OP_F_AND OP_AND 300 #define OP_F_OR OP_OR 301 #define OP_F_XOR OP_XOR 302 #define OP_F_NOR OP_NOR 303 304 #define OP_SLT 052 305 #define OP_SLTU 053 306 #define OP_DADD 054 307 #define OP_DADDU 055 308 #define OP_DSUB 056 309 #define OP_DSUBU 057 310 311 #define OP_F_SLT OP_SLT 312 #define OP_F_SLTU OP_SLTU 313 #define OP_F_DADD OP_DADD 314 #define OP_F_DADDU OP_DADDU 315 #define OP_F_DSUB OP_DSUB 316 #define OP_F_DSUBU OP_DSUBU 317 318 #define OP_TGE 060 319 #define OP_TGEU 061 320 #define OP_TLT 062 321 #define OP_TLTU 063 322 #define OP_TEQ 064 323 #define OP_TNE 066 324 325 #define OP_F_TGE OP_TGE 326 #define OP_F_TGEU OP_TGEU 327 #define OP_F_TLT OP_TLT 328 #define OP_F_TLTU OP_TLTU 329 #define OP_F_TEQ OP_TEQ 330 #define OP_F_TNE OP_TNE 331 332 #define OP_DSLL 070 333 #define OP_DSRL 072 334 #define OP_DSRA 073 335 #define OP_DSLL32 074 336 #define OP_DSRL32 076 337 #define OP_DSRA32 077 338 339 #define OP_F_DSLL OP_DSLL 340 #define OP_F_DSRL OP_DSRL 341 #define OP_F_DSRA OP_DSRA 342 #define OP_F_DSLL32 OP_DSLL32 343 #define OP_F_DSRL32 OP_DSRL32 344 #define OP_F_DSRA32 OP_DSRA32 345 346 /* 347 * The REGIMM - register immediate instructions are further 348 * decoded using this table that has 2bit row numbers, hence 349 * a need for a new helper macro. 350 */ 351 352 #define MIPS_ROP(r, c) ((r & 0x03) << 3) | (c & 0x07) 353 354 /* 355 * Values for the 'func' field when 'op' == OP_BCOND. 356 */ 357 #define OP_BLTZ 000 358 #define OP_BGEZ 001 359 #define OP_BLTZL 002 360 #define OP_BGEZL 003 361 362 #define OP_R_BLTZ OP_BLTZ 363 #define OP_R_BGEZ OP_BGEZ 364 #define OP_R_BLTZL OP_BLTZL 365 #define OP_R_BGEZL OP_BGEZL 366 367 #define OP_TGEI 010 368 #define OP_TGEIU 011 369 #define OP_TLTI 012 370 #define OP_TLTIU 013 371 #define OP_TEQI 014 372 #define OP_TNEI 016 373 374 #define OP_R_TGEI OP_TGEI 375 #define OP_R_TGEIU OP_TGEIU 376 #define OP_R_TLTI OP_TLTI 377 #define OP_R_TLTIU OP_TLTIU 378 #define OP_R_TEQI OP_TEQI 379 #define OP_R_TNEI OP_TNEI 380 381 #define OP_BLTZAL 020 382 #define OP_BGEZAL 021 383 #define OP_BLTZALL 022 384 #define OP_BGEZALL 023 385 386 #define OP_R_BLTZAL OP_BLTZAL 387 #define OP_R_BGEZAL OP_BGEZAL 388 #define OP_R_BLTZALL OP_BLTZALL 389 #define OP_R_BGEZALL OP_BGEZALL 390 391 /* 392 * Values for the 'rs' field when 'op' == OP_COPz. 393 */ 394 #define OP_MF 000 395 #define OP_DMF 001 396 #define OP_MT 004 397 #define OP_DMT 005 398 #define OP_BCx 010 399 #define OP_BCy 014 400 #define OP_CF 002 401 #define OP_CT 006 402 403 /* 404 * Values for the 'rt' field when 'op' == OP_COPz. 405 */ 406 #define COPz_BC_TF_MASK 0x01 407 #define COPz_BC_TRUE 0x01 408 #define COPz_BC_FALSE 0x00 409 #define COPz_BCL_TF_MASK 0x02 410 #define COPz_BCL_TRUE 0x02 411 #define COPz_BCL_FALSE 0x00 412 413 #endif /* !_MACHINE_MIPS_OPCODE_H_ */ 414