1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2015 Daisuke Aoyama. All rights reserved. 4 * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved. 5 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the DesignWare series USB 2.0 OTG 31 * Controller. 32 */ 33 34 /* 35 * LIMITATION: Drivers must be bound to all OUT endpoints in the 36 * active configuration for this driver to work properly. Blocking any 37 * OUT endpoint will block all OUT endpoints including the control 38 * endpoint. Usually this is not a problem. 39 */ 40 41 /* 42 * NOTE: Writing to non-existing registers appears to cause an 43 * internal reset. 44 */ 45 46 #ifdef USB_GLOBAL_INCLUDE_FILE 47 #include USB_GLOBAL_INCLUDE_FILE 48 #else 49 #include <sys/stdint.h> 50 #include <sys/stddef.h> 51 #include <sys/param.h> 52 #include <sys/queue.h> 53 #include <sys/types.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/bus.h> 57 #include <sys/module.h> 58 #include <sys/lock.h> 59 #include <sys/mutex.h> 60 #include <sys/condvar.h> 61 #include <sys/sysctl.h> 62 #include <sys/sx.h> 63 #include <sys/unistd.h> 64 #include <sys/callout.h> 65 #include <sys/malloc.h> 66 #include <sys/priv.h> 67 68 #include <dev/usb/usb.h> 69 #include <dev/usb/usbdi.h> 70 71 #define USB_DEBUG_VAR dwc_otg_debug 72 73 #include <dev/usb/usb_core.h> 74 #include <dev/usb/usb_debug.h> 75 #include <dev/usb/usb_busdma.h> 76 #include <dev/usb/usb_process.h> 77 #include <dev/usb/usb_transfer.h> 78 #include <dev/usb/usb_device.h> 79 #include <dev/usb/usb_hub.h> 80 #include <dev/usb/usb_util.h> 81 82 #include <dev/usb/usb_controller.h> 83 #include <dev/usb/usb_bus.h> 84 #endif /* USB_GLOBAL_INCLUDE_FILE */ 85 86 #include <dev/usb/controller/dwc_otg.h> 87 #include <dev/usb/controller/dwc_otgreg.h> 88 89 #define DWC_OTG_BUS2SC(bus) \ 90 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 91 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 92 93 #define DWC_OTG_PC2UDEV(pc) \ 94 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 95 96 #define DWC_OTG_MSK_GINT_ENABLED \ 97 (GINTMSK_ENUMDONEMSK | \ 98 GINTMSK_USBRSTMSK | \ 99 GINTMSK_USBSUSPMSK | \ 100 GINTMSK_IEPINTMSK | \ 101 GINTMSK_SESSREQINTMSK | \ 102 GINTMSK_RXFLVLMSK | \ 103 GINTMSK_HCHINTMSK | \ 104 GINTMSK_OTGINTMSK | \ 105 GINTMSK_PRTINTMSK) 106 107 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 108 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 109 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 110 GINTSTS_SESSREQINT) 111 112 #define DWC_OTG_PHY_ULPI 0 113 #define DWC_OTG_PHY_HSIC 1 114 #define DWC_OTG_PHY_INTERNAL 2 115 116 #ifndef DWC_OTG_PHY_DEFAULT 117 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI 118 #endif 119 120 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT; 121 122 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 123 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, 124 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2 - ULPI/HSIC/INTERNAL"); 125 126 #ifdef USB_DEBUG 127 static int dwc_otg_debug; 128 129 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN, 130 &dwc_otg_debug, 0, "DWC OTG debug level"); 131 #endif 132 133 #define DWC_OTG_INTR_ENDPT 1 134 135 /* prototypes */ 136 137 static const struct usb_bus_methods dwc_otg_bus_methods; 138 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 139 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 140 141 static dwc_otg_cmd_t dwc_otg_setup_rx; 142 static dwc_otg_cmd_t dwc_otg_data_rx; 143 static dwc_otg_cmd_t dwc_otg_data_tx; 144 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 145 146 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 147 static dwc_otg_cmd_t dwc_otg_host_data_tx; 148 static dwc_otg_cmd_t dwc_otg_host_data_rx; 149 150 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 151 static void dwc_otg_do_poll(struct usb_bus *); 152 static void dwc_otg_standard_done(struct usb_xfer *); 153 static void dwc_otg_root_intr(struct dwc_otg_softc *); 154 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 155 156 /* 157 * Here is a configuration that the chip supports. 158 */ 159 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 160 161 [0] = { 162 .max_in_frame_size = 64,/* fixed */ 163 .max_out_frame_size = 64, /* fixed */ 164 .is_simplex = 1, 165 .support_control = 1, 166 } 167 }; 168 169 static void 170 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 171 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 172 { 173 struct dwc_otg_softc *sc; 174 175 sc = DWC_OTG_BUS2SC(udev->bus); 176 177 if (ep_addr < sc->sc_dev_ep_max) 178 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 179 else 180 *ppf = NULL; 181 } 182 183 static void 184 dwc_otg_write_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, 185 uint32_t offset, uint32_t fifo, uint32_t count) 186 { 187 uint32_t temp; 188 189 /* round down length to nearest 4-bytes */ 190 temp = count & ~3; 191 192 /* check if we can write the data directly */ 193 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { 194 struct usb_page_search buf_res; 195 196 /* pre-subtract length */ 197 count -= temp; 198 199 /* iterate buffer list */ 200 do { 201 /* get current buffer pointer */ 202 usbd_get_page(pc, offset, &buf_res); 203 204 if (buf_res.length > temp) 205 buf_res.length = temp; 206 207 /* transfer data into FIFO */ 208 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 209 fifo, buf_res.buffer, buf_res.length / 4); 210 211 offset += buf_res.length; 212 fifo += buf_res.length; 213 temp -= buf_res.length; 214 } while (temp != 0); 215 } 216 217 /* check for remainder */ 218 if (count != 0) { 219 /* clear topmost word before copy */ 220 sc->sc_bounce_buffer[(count - 1) / 4] = 0; 221 222 /* copy out data */ 223 usbd_copy_out(pc, offset, 224 sc->sc_bounce_buffer, count); 225 226 /* transfer data into FIFO */ 227 bus_space_write_region_4(sc->sc_io_tag, 228 sc->sc_io_hdl, fifo, sc->sc_bounce_buffer, 229 (count + 3) / 4); 230 } 231 } 232 233 static void 234 dwc_otg_read_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, 235 uint32_t offset, uint32_t count) 236 { 237 uint32_t temp; 238 239 /* round down length to nearest 4-bytes */ 240 temp = count & ~3; 241 242 /* check if we can read the data directly */ 243 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { 244 struct usb_page_search buf_res; 245 246 /* pre-subtract length */ 247 count -= temp; 248 249 /* iterate buffer list */ 250 do { 251 /* get current buffer pointer */ 252 usbd_get_page(pc, offset, &buf_res); 253 254 if (buf_res.length > temp) 255 buf_res.length = temp; 256 257 /* transfer data from FIFO */ 258 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 259 sc->sc_current_rx_fifo, buf_res.buffer, buf_res.length / 4); 260 261 offset += buf_res.length; 262 sc->sc_current_rx_fifo += buf_res.length; 263 sc->sc_current_rx_bytes -= buf_res.length; 264 temp -= buf_res.length; 265 } while (temp != 0); 266 } 267 268 /* check for remainder */ 269 if (count != 0) { 270 /* read data into bounce buffer */ 271 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 272 sc->sc_current_rx_fifo, 273 sc->sc_bounce_buffer, (count + 3) / 4); 274 275 /* store data into proper buffer */ 276 usbd_copy_in(pc, offset, sc->sc_bounce_buffer, count); 277 278 /* round length up to nearest 4 bytes */ 279 count = (count + 3) & ~3; 280 281 /* update counters */ 282 sc->sc_current_rx_bytes -= count; 283 sc->sc_current_rx_fifo += count; 284 } 285 } 286 287 static void 288 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value) 289 { 290 uint32_t temp; 291 292 /* reset FIFO */ 293 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value); 294 295 /* wait for reset to complete */ 296 for (temp = 0; temp != 16; temp++) { 297 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL); 298 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))) 299 break; 300 } 301 } 302 303 static int 304 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 305 { 306 struct dwc_otg_profile *pf; 307 uint32_t fifo_size; 308 uint32_t fifo_regs; 309 uint32_t tx_start; 310 uint8_t x; 311 312 fifo_size = sc->sc_fifo_size; 313 314 /* 315 * NOTE: Reserved fixed size area at end of RAM, which must 316 * not be allocated to the FIFOs: 317 */ 318 fifo_regs = 4 * 16; 319 320 if (fifo_size < fifo_regs) { 321 DPRINTF("Too little FIFO\n"); 322 return (EINVAL); 323 } 324 325 /* subtract FIFO regs from total once */ 326 fifo_size -= fifo_regs; 327 328 /* split equally for IN and OUT */ 329 fifo_size /= 2; 330 331 /* Align to 4 bytes boundary (refer to PGM) */ 332 fifo_size &= ~3; 333 334 /* set global receive FIFO size */ 335 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 336 337 tx_start = fifo_size; 338 339 if (fifo_size < 64) { 340 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 341 return (EINVAL); 342 } 343 344 if (mode == DWC_MODE_HOST) { 345 346 /* reset active endpoints */ 347 sc->sc_active_rx_ep = 0; 348 349 /* split equally for periodic and non-periodic */ 350 fifo_size /= 2; 351 352 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size); 353 354 /* align to 4 bytes boundary */ 355 fifo_size &= ~3; 356 357 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 358 ((fifo_size / 4) << 16) | 359 (tx_start / 4)); 360 361 tx_start += fifo_size; 362 363 for (x = 0; x != sc->sc_host_ch_max; x++) { 364 /* enable all host interrupts */ 365 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 366 HCINT_DEFAULT_MASK); 367 } 368 369 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 370 ((fifo_size / 4) << 16) | 371 (tx_start / 4)); 372 373 /* reset host channel state */ 374 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 375 376 /* enable all host channel interrupts */ 377 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 378 (1U << sc->sc_host_ch_max) - 1U); 379 } 380 381 if (mode == DWC_MODE_DEVICE) { 382 383 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 384 (0x10 << 16) | (tx_start / 4)); 385 fifo_size -= 0x40; 386 tx_start += 0x40; 387 388 /* setup control endpoint profile */ 389 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 390 391 /* reset active endpoints */ 392 sc->sc_active_rx_ep = 1; 393 394 for (x = 1; x != sc->sc_dev_ep_max; x++) { 395 396 pf = sc->sc_hw_ep_profile + x; 397 398 pf->usb.max_out_frame_size = 1024 * 3; 399 pf->usb.is_simplex = 0; /* assume duplex */ 400 pf->usb.support_bulk = 1; 401 pf->usb.support_interrupt = 1; 402 pf->usb.support_isochronous = 1; 403 pf->usb.support_out = 1; 404 405 if (x < sc->sc_dev_in_ep_max) { 406 uint32_t limit; 407 408 limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 409 DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2, 410 DWC_OTG_TX_MAX_FIFO_SIZE); 411 412 /* see if there is enough FIFO space */ 413 if (limit <= fifo_size) { 414 pf->max_buffer = limit; 415 pf->usb.support_in = 1; 416 } else { 417 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40); 418 if (limit <= fifo_size) { 419 pf->usb.support_in = 1; 420 } else { 421 pf->usb.is_simplex = 1; 422 limit = 0; 423 } 424 } 425 /* set FIFO size */ 426 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 427 ((limit / 4) << 16) | (tx_start / 4)); 428 tx_start += limit; 429 fifo_size -= limit; 430 pf->usb.max_in_frame_size = limit; 431 } else { 432 pf->usb.is_simplex = 1; 433 } 434 435 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 436 pf->usb.max_in_frame_size, 437 pf->usb.max_out_frame_size); 438 } 439 } 440 441 /* reset RX FIFO */ 442 dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH); 443 444 if (mode != DWC_MODE_OTG) { 445 /* reset all TX FIFOs */ 446 dwc_otg_tx_fifo_reset(sc, 447 GRSTCTL_TXFIFO(0x10) | 448 GRSTCTL_TXFFLSH); 449 } else { 450 /* reset active endpoints */ 451 sc->sc_active_rx_ep = 0; 452 453 /* reset host channel state */ 454 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 455 } 456 return (0); 457 } 458 459 static uint8_t 460 dwc_otg_uses_split(struct usb_device *udev) 461 { 462 /* 463 * When a LOW or FULL speed device is connected directly to 464 * the USB port we don't use split transactions: 465 */ 466 return (udev->speed != USB_SPEED_HIGH && 467 udev->parent_hs_hub != NULL && 468 udev->parent_hs_hub->parent_hub != NULL); 469 } 470 471 static void 472 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 473 { 474 475 /* 476 * Disabled until further. Assuming that the register is already 477 * programmed correctly by the boot loader. 478 */ 479 #if 0 480 uint32_t temp; 481 482 /* setup HOST frame interval register, based on existing value */ 483 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 484 if (temp >= 10000) 485 temp /= 1000; 486 else 487 temp /= 125; 488 489 /* figure out nearest X-tal value */ 490 if (temp >= 54) 491 temp = 60; /* MHz */ 492 else if (temp >= 39) 493 temp = 48; /* MHz */ 494 else 495 temp = 30; /* MHz */ 496 497 if (sc->sc_flags.status_high_speed) 498 temp *= 125; 499 else 500 temp *= 1000; 501 502 DPRINTF("HFIR=0x%08x\n", temp); 503 504 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 505 #endif 506 } 507 508 static void 509 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 510 { 511 if (sc->sc_flags.clocks_off && 512 sc->sc_flags.port_powered) { 513 514 DPRINTFN(5, "\n"); 515 516 /* TODO - platform specific */ 517 518 sc->sc_flags.clocks_off = 0; 519 } 520 } 521 522 static void 523 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 524 { 525 if (!sc->sc_flags.clocks_off) { 526 527 DPRINTFN(5, "\n"); 528 529 /* TODO - platform specific */ 530 531 sc->sc_flags.clocks_off = 1; 532 } 533 } 534 535 static void 536 dwc_otg_pull_up(struct dwc_otg_softc *sc) 537 { 538 uint32_t temp; 539 540 /* pullup D+, if possible */ 541 542 if (!sc->sc_flags.d_pulled_up && 543 sc->sc_flags.port_powered) { 544 sc->sc_flags.d_pulled_up = 1; 545 546 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 547 temp &= ~DCTL_SFTDISCON; 548 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 549 } 550 } 551 552 static void 553 dwc_otg_pull_down(struct dwc_otg_softc *sc) 554 { 555 uint32_t temp; 556 557 /* pulldown D+, if possible */ 558 559 if (sc->sc_flags.d_pulled_up) { 560 sc->sc_flags.d_pulled_up = 0; 561 562 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 563 temp |= DCTL_SFTDISCON; 564 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 565 } 566 } 567 568 static void 569 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 570 { 571 /* In device mode we don't use the SOF interrupt */ 572 if (sc->sc_flags.status_device_mode != 0) 573 return; 574 /* Ensure the SOF interrupt is not disabled */ 575 sc->sc_needsof = 1; 576 /* Check if the SOF interrupt is already enabled */ 577 if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 578 return; 579 sc->sc_irq_mask |= GINTMSK_SOFMSK; 580 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 581 } 582 583 static void 584 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 585 { 586 if (sc->sc_flags.status_suspend) { 587 /* update status bits */ 588 sc->sc_flags.status_suspend = 0; 589 sc->sc_flags.change_suspend = 1; 590 591 if (sc->sc_flags.status_device_mode) { 592 /* 593 * Disable resume interrupt and enable suspend 594 * interrupt: 595 */ 596 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 597 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 598 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 599 } 600 601 /* complete root HUB interrupt endpoint */ 602 dwc_otg_root_intr(sc); 603 } 604 } 605 606 static void 607 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 608 { 609 if (!sc->sc_flags.status_suspend) { 610 /* update status bits */ 611 sc->sc_flags.status_suspend = 1; 612 sc->sc_flags.change_suspend = 1; 613 614 if (sc->sc_flags.status_device_mode) { 615 /* 616 * Disable suspend interrupt and enable resume 617 * interrupt: 618 */ 619 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 620 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 621 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 622 } 623 624 /* complete root HUB interrupt endpoint */ 625 dwc_otg_root_intr(sc); 626 } 627 } 628 629 static void 630 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 631 { 632 if (!sc->sc_flags.status_suspend) 633 return; 634 635 DPRINTFN(5, "Remote wakeup\n"); 636 637 if (sc->sc_flags.status_device_mode) { 638 uint32_t temp; 639 640 /* enable remote wakeup signalling */ 641 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 642 temp |= DCTL_RMTWKUPSIG; 643 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 644 645 /* Wait 8ms for remote wakeup to complete. */ 646 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 647 648 temp &= ~DCTL_RMTWKUPSIG; 649 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 650 } else { 651 /* enable USB port */ 652 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 653 654 /* wait 10ms */ 655 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 656 657 /* resume port */ 658 sc->sc_hprt_val |= HPRT_PRTRES; 659 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 660 661 /* Wait 100ms for resume signalling to complete. */ 662 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 663 664 /* clear suspend and resume */ 665 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 666 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 667 668 /* Wait 4ms */ 669 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 670 } 671 672 /* need to fake resume IRQ */ 673 dwc_otg_resume_irq(sc); 674 } 675 676 static void 677 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 678 { 679 uint32_t temp; 680 681 DPRINTFN(5, "addr=%d\n", addr); 682 683 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 684 temp &= ~DCFG_DEVADDR_SET(0x7F); 685 temp |= DCFG_DEVADDR_SET(addr); 686 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 687 } 688 689 static void 690 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 691 { 692 DPRINTFN(5, "RX status clear\n"); 693 694 /* enable RX FIFO level interrupt */ 695 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 696 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 697 698 if (sc->sc_current_rx_bytes != 0) { 699 /* need to dump remaining data */ 700 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 701 sc->sc_current_rx_fifo, sc->sc_bounce_buffer, 702 sc->sc_current_rx_bytes / 4); 703 /* clear number of active bytes to receive */ 704 sc->sc_current_rx_bytes = 0; 705 } 706 /* clear cached status */ 707 sc->sc_last_rx_status = 0; 708 } 709 710 static void 711 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 712 { 713 uint32_t hcint; 714 715 /* clear all pending interrupts */ 716 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 717 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 718 719 /* clear buffered interrupts */ 720 sc->sc_chan_state[x].hcint = 0; 721 } 722 723 static uint8_t 724 dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 725 { 726 uint32_t temp; 727 728 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 729 730 if (td->ep_type == UE_ISOCHRONOUS) { 731 /* 732 * NOTE: USB INTERRUPT transactions are executed like 733 * USB CONTROL transactions! See the setup standard 734 * chain function for more information. 735 */ 736 if (!(temp & GINTSTS_PTXFEMP)) { 737 DPRINTF("Periodic TX FIFO is not empty\n"); 738 if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) { 739 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK; 740 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 741 } 742 return (1); /* busy */ 743 } 744 } else { 745 if (!(temp & GINTSTS_NPTXFEMP)) { 746 DPRINTF("Non-periodic TX FIFO is not empty\n"); 747 if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) { 748 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK; 749 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 750 } 751 return (1); /* busy */ 752 } 753 } 754 return (0); /* ready for transmit */ 755 } 756 757 static uint8_t 758 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, 759 struct dwc_otg_td *td, uint8_t is_out) 760 { 761 uint8_t x; 762 uint8_t y; 763 uint8_t z; 764 765 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) 766 return (0); /* already allocated */ 767 768 /* check if device is suspended */ 769 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 770 return (1); /* busy - cannot transfer data */ 771 772 /* compute needed TX FIFO size */ 773 if (is_out != 0) { 774 if (dwc_otg_host_check_tx_fifo_empty(sc, td) != 0) 775 return (1); /* busy - cannot transfer data */ 776 } 777 z = td->max_packet_count; 778 for (x = y = 0; x != sc->sc_host_ch_max; x++) { 779 /* check if channel is allocated */ 780 if (sc->sc_chan_state[x].allocated != 0) 781 continue; 782 /* check if channel is still enabled */ 783 if (sc->sc_chan_state[x].wait_halted != 0) 784 continue; 785 /* store channel number */ 786 td->channel[y++] = x; 787 /* check if we got all channels */ 788 if (y == z) 789 break; 790 } 791 if (y != z) { 792 /* reset channel variable */ 793 td->channel[0] = DWC_OTG_MAX_CHANNELS; 794 td->channel[1] = DWC_OTG_MAX_CHANNELS; 795 td->channel[2] = DWC_OTG_MAX_CHANNELS; 796 /* wait a bit */ 797 dwc_otg_enable_sof_irq(sc); 798 return (1); /* busy - not enough channels */ 799 } 800 801 for (y = 0; y != z; y++) { 802 x = td->channel[y]; 803 804 /* set allocated */ 805 sc->sc_chan_state[x].allocated = 1; 806 807 /* set wait halted */ 808 sc->sc_chan_state[x].wait_halted = 1; 809 810 /* clear interrupts */ 811 dwc_otg_clear_hcint(sc, x); 812 813 DPRINTF("CH=%d HCCHAR=0x%08x " 814 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 815 816 /* set active channel */ 817 sc->sc_active_rx_ep |= (1 << x); 818 } 819 return (0); /* allocated */ 820 } 821 822 static void 823 dwc_otg_host_channel_free_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t index) 824 { 825 uint32_t hcchar; 826 uint8_t x; 827 828 if (td->channel[index] >= DWC_OTG_MAX_CHANNELS) 829 return; /* already freed */ 830 831 /* free channel */ 832 x = td->channel[index]; 833 td->channel[index] = DWC_OTG_MAX_CHANNELS; 834 835 DPRINTF("CH=%d\n", x); 836 837 /* 838 * We need to let programmed host channels run till complete 839 * else the host channel will stop functioning. 840 */ 841 sc->sc_chan_state[x].allocated = 0; 842 843 /* ack any pending messages */ 844 if (sc->sc_last_rx_status != 0 && 845 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 846 dwc_otg_common_rx_ack(sc); 847 } 848 849 /* clear active channel */ 850 sc->sc_active_rx_ep &= ~(1 << x); 851 852 /* check if already halted */ 853 if (sc->sc_chan_state[x].wait_halted == 0) 854 return; 855 856 /* disable host channel */ 857 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 858 if (hcchar & HCCHAR_CHENA) { 859 DPRINTF("Halting channel %d\n", x); 860 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 861 hcchar | HCCHAR_CHDIS); 862 /* don't write HCCHAR until the channel is halted */ 863 } else { 864 sc->sc_chan_state[x].wait_halted = 0; 865 } 866 } 867 868 static void 869 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 870 { 871 uint8_t x; 872 for (x = 0; x != td->max_packet_count; x++) 873 dwc_otg_host_channel_free_sub(sc, td, x); 874 } 875 876 static void 877 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 878 { 879 uint8_t x; 880 /* dump any pending messages */ 881 if (sc->sc_last_rx_status == 0) 882 return; 883 for (x = 0; x != td->max_packet_count; x++) { 884 if (td->channel[x] >= DWC_OTG_MAX_CHANNELS || 885 td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) 886 continue; 887 dwc_otg_common_rx_ack(sc); 888 break; 889 } 890 } 891 892 static uint8_t 893 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 894 { 895 struct usb_device_request req __aligned(4); 896 uint32_t hcint; 897 uint32_t hcchar; 898 uint8_t delta; 899 900 dwc_otg_host_dump_rx(sc, td); 901 902 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) { 903 hcint = sc->sc_chan_state[td->channel[0]].hcint; 904 905 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 906 td->channel[0], td->state, hcint, 907 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])), 908 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0]))); 909 } else { 910 hcint = 0; 911 goto check_state; 912 } 913 914 if (hcint & (HCINT_RETRY | 915 HCINT_ACK | HCINT_NYET)) { 916 /* give success bits priority over failure bits */ 917 } else if (hcint & HCINT_STALL) { 918 DPRINTF("CH=%d STALL\n", td->channel[0]); 919 td->error_stall = 1; 920 td->error_any = 1; 921 goto complete; 922 } else if (hcint & HCINT_ERRORS) { 923 DPRINTF("CH=%d ERROR\n", td->channel[0]); 924 td->errcnt++; 925 if (td->hcsplt != 0 || td->errcnt >= 3) { 926 td->error_any = 1; 927 goto complete; 928 } 929 } 930 931 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 932 HCINT_ACK | HCINT_NYET)) { 933 if (!(hcint & HCINT_ERRORS)) 934 td->errcnt = 0; 935 } 936 937 check_state: 938 switch (td->state) { 939 case DWC_CHAN_ST_START: 940 goto send_pkt; 941 942 case DWC_CHAN_ST_WAIT_ANE: 943 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 944 td->did_nak = 1; 945 td->tt_scheduled = 0; 946 goto send_pkt; 947 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 948 td->offset += td->tx_bytes; 949 td->remainder -= td->tx_bytes; 950 td->toggle = 1; 951 td->tt_scheduled = 0; 952 goto complete; 953 } 954 break; 955 956 case DWC_CHAN_ST_WAIT_S_ANE: 957 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 958 td->did_nak = 1; 959 td->tt_scheduled = 0; 960 goto send_pkt; 961 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 962 goto send_cpkt; 963 } 964 break; 965 966 case DWC_CHAN_ST_WAIT_C_ANE: 967 if (hcint & HCINT_NYET) { 968 goto send_cpkt; 969 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 970 td->did_nak = 1; 971 td->tt_scheduled = 0; 972 goto send_pkt; 973 } else if (hcint & HCINT_ACK) { 974 td->offset += td->tx_bytes; 975 td->remainder -= td->tx_bytes; 976 td->toggle = 1; 977 goto complete; 978 } 979 break; 980 981 case DWC_CHAN_ST_WAIT_C_PKT: 982 goto send_cpkt; 983 984 default: 985 break; 986 } 987 goto busy; 988 989 send_pkt: 990 /* free existing channel, if any */ 991 dwc_otg_host_channel_free(sc, td); 992 993 if (sizeof(req) != td->remainder) { 994 td->error_any = 1; 995 goto complete; 996 } 997 998 if (td->hcsplt != 0) { 999 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1000 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1001 td->state = DWC_CHAN_ST_START; 1002 goto busy; 1003 } 1004 delta = sc->sc_last_frame_num - td->tt_start_slot; 1005 if (delta > 5) { 1006 /* missed it */ 1007 td->tt_scheduled = 0; 1008 td->state = DWC_CHAN_ST_START; 1009 goto busy; 1010 } 1011 } 1012 1013 /* allocate a new channel */ 1014 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1015 td->state = DWC_CHAN_ST_START; 1016 goto busy; 1017 } 1018 1019 if (td->hcsplt != 0) { 1020 td->hcsplt &= ~HCSPLT_COMPSPLT; 1021 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1022 } else { 1023 td->state = DWC_CHAN_ST_WAIT_ANE; 1024 } 1025 1026 /* copy out control request */ 1027 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 1028 1029 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 1030 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 1031 (1 << HCTSIZ_PKTCNT_SHIFT) | 1032 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 1033 1034 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 1035 1036 hcchar = td->hcchar; 1037 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 1038 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 1039 1040 /* must enable channel before writing data to FIFO */ 1041 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 1042 1043 /* transfer data into FIFO */ 1044 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1045 DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4); 1046 1047 /* wait until next slot before trying complete split */ 1048 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1049 1050 /* store number of bytes transmitted */ 1051 td->tx_bytes = sizeof(req); 1052 goto busy; 1053 1054 send_cpkt: 1055 /* free existing channel, if any */ 1056 dwc_otg_host_channel_free(sc, td); 1057 1058 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1059 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1060 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1061 goto busy; 1062 } 1063 delta = sc->sc_last_frame_num - td->tt_start_slot; 1064 if (delta > DWC_OTG_TT_SLOT_MAX) { 1065 /* we missed the service interval */ 1066 if (td->ep_type != UE_ISOCHRONOUS) 1067 td->error_any = 1; 1068 goto complete; 1069 } 1070 /* allocate a new channel */ 1071 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1072 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1073 goto busy; 1074 } 1075 1076 /* wait until next slot before trying complete split */ 1077 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1078 1079 td->hcsplt |= HCSPLT_COMPSPLT; 1080 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1081 1082 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 1083 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 1084 1085 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 1086 1087 hcchar = td->hcchar; 1088 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 1089 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 1090 1091 /* must enable channel before writing data to FIFO */ 1092 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 1093 1094 busy: 1095 return (1); /* busy */ 1096 1097 complete: 1098 dwc_otg_host_channel_free(sc, td); 1099 return (0); /* complete */ 1100 } 1101 1102 static uint8_t 1103 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1104 { 1105 struct usb_device_request req __aligned(4); 1106 uint32_t temp; 1107 uint16_t count; 1108 1109 /* check endpoint status */ 1110 1111 if (sc->sc_last_rx_status == 0) 1112 goto not_complete; 1113 1114 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 1115 goto not_complete; 1116 1117 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1118 GRXSTSRD_STP_DATA) { 1119 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1120 GRXSTSRD_STP_COMPLETE || td->remainder != 0) { 1121 /* release FIFO */ 1122 dwc_otg_common_rx_ack(sc); 1123 goto not_complete; 1124 } 1125 /* release FIFO */ 1126 dwc_otg_common_rx_ack(sc); 1127 return (0); /* complete */ 1128 } 1129 1130 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 1131 GRXSTSRD_DPID_DATA0) { 1132 /* release FIFO */ 1133 dwc_otg_common_rx_ack(sc); 1134 goto not_complete; 1135 } 1136 1137 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 1138 1139 /* clear did stall */ 1140 td->did_stall = 0; 1141 1142 /* get the packet byte count */ 1143 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1144 1145 if (count != sizeof(req)) { 1146 DPRINTFN(0, "Unsupported SETUP packet " 1147 "length, %d bytes\n", count); 1148 /* release FIFO */ 1149 dwc_otg_common_rx_ack(sc); 1150 goto not_complete; 1151 } 1152 1153 /* read FIFO */ 1154 dwc_otg_read_fifo(sc, td->pc, 0, sizeof(req)); 1155 1156 /* copy out control request */ 1157 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 1158 1159 td->offset = sizeof(req); 1160 td->remainder = 0; 1161 1162 /* sneak peek the set address */ 1163 if ((req.bmRequestType == UT_WRITE_DEVICE) && 1164 (req.bRequest == UR_SET_ADDRESS)) { 1165 /* must write address before ZLP */ 1166 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1167 } 1168 1169 /* don't send any data by default */ 1170 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS); 1171 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS); 1172 1173 /* reset IN endpoint buffer */ 1174 dwc_otg_tx_fifo_reset(sc, 1175 GRSTCTL_TXFIFO(0) | 1176 GRSTCTL_TXFFLSH); 1177 1178 /* acknowledge RX status */ 1179 dwc_otg_common_rx_ack(sc); 1180 td->did_stall = 1; 1181 1182 not_complete: 1183 /* abort any ongoing transfer, before enabling again */ 1184 if (!td->did_stall) { 1185 td->did_stall = 1; 1186 1187 DPRINTFN(5, "stalling IN and OUT direction\n"); 1188 1189 temp = sc->sc_out_ctl[0]; 1190 1191 /* set stall after enabling endpoint */ 1192 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1193 temp | DOEPCTL_STALL); 1194 1195 temp = sc->sc_in_ctl[0]; 1196 1197 /* set stall assuming endpoint is enabled */ 1198 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1199 temp | DIEPCTL_STALL); 1200 } 1201 return (1); /* not complete */ 1202 } 1203 1204 static uint8_t 1205 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1206 { 1207 uint8_t delta; 1208 1209 delta = sc->sc_tmr_val - td->tmr_val; 1210 if (delta >= 128) 1211 return (1); /* busy */ 1212 1213 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1214 1215 /* set toggle, if any */ 1216 if (td->set_toggle) { 1217 td->set_toggle = 0; 1218 td->toggle = 1; 1219 } 1220 return (0); 1221 } 1222 1223 static uint8_t 1224 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1225 { 1226 uint8_t frame_num = (uint8_t)sc->sc_last_frame_num; 1227 1228 if (td->ep_type == UE_ISOCHRONOUS) { 1229 /* non TT isochronous traffic */ 1230 if (frame_num & (td->tmr_res - 1)) 1231 goto busy; 1232 if ((frame_num ^ td->tmr_val) & td->tmr_res) 1233 goto busy; 1234 td->tmr_val = td->tmr_res + sc->sc_last_frame_num; 1235 td->toggle = 0; 1236 return (0); 1237 } else if (td->ep_type == UE_INTERRUPT) { 1238 if (!td->tt_scheduled) 1239 goto busy; 1240 td->tt_scheduled = 0; 1241 return (0); 1242 } else if (td->did_nak != 0) { 1243 /* check if we should pause sending queries for 125us */ 1244 if (td->tmr_res == frame_num) { 1245 /* wait a bit */ 1246 dwc_otg_enable_sof_irq(sc); 1247 goto busy; 1248 } 1249 } else if (td->set_toggle) { 1250 td->set_toggle = 0; 1251 td->toggle = 1; 1252 } 1253 /* query for data one more time */ 1254 td->tmr_res = frame_num; 1255 td->did_nak = 0; 1256 return (0); 1257 busy: 1258 return (1); 1259 } 1260 1261 static uint8_t 1262 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, 1263 uint8_t channel) 1264 { 1265 uint32_t count; 1266 1267 /* check endpoint status */ 1268 if (sc->sc_last_rx_status == 0) 1269 goto busy; 1270 1271 if (channel >= DWC_OTG_MAX_CHANNELS) 1272 goto busy; 1273 1274 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1275 goto busy; 1276 1277 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1278 case GRXSTSRH_IN_DATA: 1279 1280 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1281 (int)td->state, (int)sc->sc_last_rx_status); 1282 1283 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1284 /* 1285 * When using SPLIT transactions on interrupt 1286 * endpoints, sometimes data occurs twice. 1287 */ 1288 DPRINTF("Data already received\n"); 1289 break; 1290 } 1291 1292 /* get the packet byte count */ 1293 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1294 1295 /* check for ISOCHRONOUS endpoint */ 1296 if (td->ep_type == UE_ISOCHRONOUS) { 1297 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 1298 GRXSTSRD_DPID_DATA0) { 1299 /* more data to be received */ 1300 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1301 } else { 1302 /* all data received */ 1303 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1304 /* verify the packet byte count */ 1305 if (count != td->remainder) { 1306 /* we have a short packet */ 1307 td->short_pkt = 1; 1308 td->got_short = 1; 1309 } 1310 } 1311 } else { 1312 /* verify the packet byte count */ 1313 if (count != td->max_packet_size) { 1314 if (count < td->max_packet_size) { 1315 /* we have a short packet */ 1316 td->short_pkt = 1; 1317 td->got_short = 1; 1318 } else { 1319 /* invalid USB packet */ 1320 td->error_any = 1; 1321 1322 /* release FIFO */ 1323 dwc_otg_common_rx_ack(sc); 1324 goto complete; 1325 } 1326 } 1327 td->toggle ^= 1; 1328 td->tt_scheduled = 0; 1329 } 1330 1331 /* verify the packet byte count */ 1332 if (count > td->remainder) { 1333 /* invalid USB packet */ 1334 td->error_any = 1; 1335 1336 /* release FIFO */ 1337 dwc_otg_common_rx_ack(sc); 1338 goto complete; 1339 } 1340 1341 /* read data from FIFO */ 1342 dwc_otg_read_fifo(sc, td->pc, td->offset, count); 1343 1344 td->remainder -= count; 1345 td->offset += count; 1346 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1347 break; 1348 default: 1349 break; 1350 } 1351 /* release FIFO */ 1352 dwc_otg_common_rx_ack(sc); 1353 busy: 1354 return (0); 1355 complete: 1356 return (1); 1357 } 1358 1359 static uint8_t 1360 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1361 { 1362 uint32_t hcint = 0; 1363 uint32_t hcchar; 1364 uint8_t delta; 1365 uint8_t channel; 1366 uint8_t x; 1367 1368 for (x = 0; x != td->max_packet_count; x++) { 1369 channel = td->channel[x]; 1370 if (channel >= DWC_OTG_MAX_CHANNELS) 1371 continue; 1372 hcint |= sc->sc_chan_state[channel].hcint; 1373 1374 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1375 channel, td->state, hcint, 1376 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1377 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1378 1379 /* check interrupt bits */ 1380 if (hcint & (HCINT_RETRY | 1381 HCINT_ACK | HCINT_NYET)) { 1382 /* give success bits priority over failure bits */ 1383 } else if (hcint & HCINT_STALL) { 1384 DPRINTF("CH=%d STALL\n", channel); 1385 td->error_stall = 1; 1386 td->error_any = 1; 1387 goto complete; 1388 } else if (hcint & HCINT_ERRORS) { 1389 DPRINTF("CH=%d ERROR\n", channel); 1390 td->errcnt++; 1391 if (td->hcsplt != 0 || td->errcnt >= 3) { 1392 if (td->ep_type != UE_ISOCHRONOUS) { 1393 td->error_any = 1; 1394 goto complete; 1395 } 1396 } 1397 } 1398 1399 /* check channels for data, if any */ 1400 if (dwc_otg_host_data_rx_sub(sc, td, channel)) 1401 goto complete; 1402 1403 /* refresh interrupt status */ 1404 hcint |= sc->sc_chan_state[channel].hcint; 1405 1406 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1407 HCINT_ACK | HCINT_NYET)) { 1408 if (!(hcint & HCINT_ERRORS)) 1409 td->errcnt = 0; 1410 } 1411 } 1412 1413 switch (td->state) { 1414 case DWC_CHAN_ST_START: 1415 if (td->hcsplt != 0) 1416 goto receive_spkt; 1417 else 1418 goto receive_pkt; 1419 1420 case DWC_CHAN_ST_WAIT_ANE: 1421 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1422 if (td->ep_type == UE_INTERRUPT) { 1423 /* 1424 * The USB specification does not 1425 * mandate a particular data toggle 1426 * value for USB INTERRUPT 1427 * transfers. Switch the data toggle 1428 * value to receive the packet 1429 * correctly: 1430 */ 1431 if (hcint & HCINT_DATATGLERR) { 1432 DPRINTF("Retrying packet due to " 1433 "data toggle error\n"); 1434 td->toggle ^= 1; 1435 goto receive_pkt; 1436 } 1437 } else if (td->ep_type == UE_ISOCHRONOUS) { 1438 goto complete; 1439 } 1440 td->did_nak = 1; 1441 td->tt_scheduled = 0; 1442 if (td->hcsplt != 0) 1443 goto receive_spkt; 1444 else 1445 goto receive_pkt; 1446 } else if (hcint & HCINT_NYET) { 1447 if (td->hcsplt != 0) { 1448 /* try again */ 1449 goto receive_pkt; 1450 } else { 1451 /* not a valid token for IN endpoints */ 1452 td->error_any = 1; 1453 goto complete; 1454 } 1455 } else if (hcint & HCINT_ACK) { 1456 /* wait for data - ACK arrived first */ 1457 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1458 goto busy; 1459 1460 if (td->ep_type == UE_ISOCHRONOUS) { 1461 /* check if we are complete */ 1462 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) { 1463 goto complete; 1464 } else { 1465 /* get more packets */ 1466 goto busy; 1467 } 1468 } else { 1469 /* check if we are complete */ 1470 if ((td->remainder == 0) || (td->got_short != 0)) { 1471 if (td->short_pkt) 1472 goto complete; 1473 1474 /* 1475 * Else need to receive a zero length 1476 * packet. 1477 */ 1478 } 1479 td->tt_scheduled = 0; 1480 td->did_nak = 0; 1481 if (td->hcsplt != 0) 1482 goto receive_spkt; 1483 else 1484 goto receive_pkt; 1485 } 1486 } 1487 break; 1488 1489 case DWC_CHAN_ST_WAIT_S_ANE: 1490 /* 1491 * NOTE: The DWC OTG hardware provides a fake ACK in 1492 * case of interrupt and isochronous transfers: 1493 */ 1494 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1495 td->did_nak = 1; 1496 td->tt_scheduled = 0; 1497 goto receive_spkt; 1498 } else if (hcint & HCINT_NYET) { 1499 td->tt_scheduled = 0; 1500 goto receive_spkt; 1501 } else if (hcint & HCINT_ACK) { 1502 td->did_nak = 0; 1503 goto receive_pkt; 1504 } 1505 break; 1506 1507 case DWC_CHAN_ST_WAIT_C_PKT: 1508 goto receive_pkt; 1509 1510 default: 1511 break; 1512 } 1513 goto busy; 1514 1515 receive_pkt: 1516 /* free existing channel, if any */ 1517 dwc_otg_host_channel_free(sc, td); 1518 1519 if (td->hcsplt != 0) { 1520 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1521 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1522 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1523 goto busy; 1524 } 1525 delta = sc->sc_last_frame_num - td->tt_start_slot; 1526 if (delta > DWC_OTG_TT_SLOT_MAX) { 1527 if (td->ep_type != UE_ISOCHRONOUS) { 1528 /* we missed the service interval */ 1529 td->error_any = 1; 1530 } 1531 goto complete; 1532 } 1533 /* complete split */ 1534 td->hcsplt |= HCSPLT_COMPSPLT; 1535 } else if (dwc_otg_host_rate_check(sc, td)) { 1536 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1537 goto busy; 1538 } 1539 1540 /* allocate a new channel */ 1541 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1542 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1543 goto busy; 1544 } 1545 1546 /* set toggle, if any */ 1547 if (td->set_toggle) { 1548 td->set_toggle = 0; 1549 td->toggle = 1; 1550 } 1551 1552 td->state = DWC_CHAN_ST_WAIT_ANE; 1553 1554 for (x = 0; x != td->max_packet_count; x++) { 1555 channel = td->channel[x]; 1556 1557 /* receive one packet */ 1558 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1559 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1560 (1 << HCTSIZ_PKTCNT_SHIFT) | 1561 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1562 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1563 1564 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1565 1566 hcchar = td->hcchar; 1567 hcchar |= HCCHAR_EPDIR_IN; 1568 1569 /* receive complete split ASAP */ 1570 if ((sc->sc_last_frame_num & 1) != 0 && 1571 td->ep_type == UE_ISOCHRONOUS) 1572 hcchar |= HCCHAR_ODDFRM; 1573 else 1574 hcchar &= ~HCCHAR_ODDFRM; 1575 1576 /* must enable channel before data can be received */ 1577 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1578 } 1579 /* wait until next slot before trying complete split */ 1580 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1581 1582 goto busy; 1583 1584 receive_spkt: 1585 /* free existing channel(s), if any */ 1586 dwc_otg_host_channel_free(sc, td); 1587 1588 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1589 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1590 td->state = DWC_CHAN_ST_START; 1591 goto busy; 1592 } 1593 delta = sc->sc_last_frame_num - td->tt_start_slot; 1594 if (delta > 5) { 1595 /* missed it */ 1596 td->tt_scheduled = 0; 1597 td->state = DWC_CHAN_ST_START; 1598 goto busy; 1599 } 1600 1601 /* allocate a new channel */ 1602 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1603 td->state = DWC_CHAN_ST_START; 1604 goto busy; 1605 } 1606 1607 channel = td->channel[0]; 1608 1609 td->hcsplt &= ~HCSPLT_COMPSPLT; 1610 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1611 1612 /* receive one packet */ 1613 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1614 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1615 1616 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1617 1618 /* send after next SOF event */ 1619 if ((sc->sc_last_frame_num & 1) == 0 && 1620 td->ep_type == UE_ISOCHRONOUS) 1621 td->hcchar |= HCCHAR_ODDFRM; 1622 else 1623 td->hcchar &= ~HCCHAR_ODDFRM; 1624 1625 hcchar = td->hcchar; 1626 hcchar |= HCCHAR_EPDIR_IN; 1627 1628 /* wait until next slot before trying complete split */ 1629 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1630 1631 /* must enable channel before data can be received */ 1632 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1633 busy: 1634 return (1); /* busy */ 1635 1636 complete: 1637 dwc_otg_host_channel_free(sc, td); 1638 return (0); /* complete */ 1639 } 1640 1641 static uint8_t 1642 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1643 { 1644 uint32_t temp; 1645 uint16_t count; 1646 uint8_t got_short; 1647 1648 got_short = 0; 1649 1650 /* check endpoint status */ 1651 if (sc->sc_last_rx_status == 0) 1652 goto not_complete; 1653 1654 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1655 goto not_complete; 1656 1657 /* check for SETUP packet */ 1658 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1659 GRXSTSRD_STP_DATA || 1660 (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1661 GRXSTSRD_STP_COMPLETE) { 1662 if (td->remainder == 0) { 1663 /* 1664 * We are actually complete and have 1665 * received the next SETUP 1666 */ 1667 DPRINTFN(5, "faking complete\n"); 1668 return (0); /* complete */ 1669 } 1670 /* 1671 * USB Host Aborted the transfer. 1672 */ 1673 td->error_any = 1; 1674 return (0); /* complete */ 1675 } 1676 1677 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1678 GRXSTSRD_OUT_DATA) { 1679 /* release FIFO */ 1680 dwc_otg_common_rx_ack(sc); 1681 goto not_complete; 1682 } 1683 1684 /* get the packet byte count */ 1685 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1686 1687 /* verify the packet byte count */ 1688 if (count != td->max_packet_size) { 1689 if (count < td->max_packet_size) { 1690 /* we have a short packet */ 1691 td->short_pkt = 1; 1692 got_short = 1; 1693 } else { 1694 /* invalid USB packet */ 1695 td->error_any = 1; 1696 1697 /* release FIFO */ 1698 dwc_otg_common_rx_ack(sc); 1699 return (0); /* we are complete */ 1700 } 1701 } 1702 /* verify the packet byte count */ 1703 if (count > td->remainder) { 1704 /* invalid USB packet */ 1705 td->error_any = 1; 1706 1707 /* release FIFO */ 1708 dwc_otg_common_rx_ack(sc); 1709 return (0); /* we are complete */ 1710 } 1711 1712 /* read data from FIFO */ 1713 dwc_otg_read_fifo(sc, td->pc, td->offset, count); 1714 1715 td->remainder -= count; 1716 td->offset += count; 1717 1718 /* release FIFO */ 1719 dwc_otg_common_rx_ack(sc); 1720 1721 temp = sc->sc_out_ctl[td->ep_no]; 1722 1723 /* check for isochronous mode */ 1724 if ((temp & DIEPCTL_EPTYPE_MASK) == 1725 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 1726 /* toggle odd or even frame bit */ 1727 if (temp & DIEPCTL_SETD1PID) { 1728 temp &= ~DIEPCTL_SETD1PID; 1729 temp |= DIEPCTL_SETD0PID; 1730 } else { 1731 temp &= ~DIEPCTL_SETD0PID; 1732 temp |= DIEPCTL_SETD1PID; 1733 } 1734 sc->sc_out_ctl[td->ep_no] = temp; 1735 } 1736 1737 /* check if we are complete */ 1738 if ((td->remainder == 0) || got_short) { 1739 if (td->short_pkt) { 1740 /* we are complete */ 1741 return (0); 1742 } 1743 /* else need to receive a zero length packet */ 1744 } 1745 1746 not_complete: 1747 1748 /* enable SETUP and transfer complete interrupt */ 1749 if (td->ep_no == 0) { 1750 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1751 DXEPTSIZ_SET_MULTI(3) | 1752 DXEPTSIZ_SET_NPKT(1) | 1753 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1754 } else { 1755 /* allow reception of multiple packets */ 1756 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1757 DXEPTSIZ_SET_MULTI(1) | 1758 DXEPTSIZ_SET_NPKT(4) | 1759 DXEPTSIZ_SET_NBYTES(4 * 1760 ((td->max_packet_size + 3) & ~3))); 1761 } 1762 temp = sc->sc_out_ctl[td->ep_no]; 1763 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp | 1764 DOEPCTL_EPENA | DOEPCTL_CNAK); 1765 1766 return (1); /* not complete */ 1767 } 1768 1769 static uint8_t 1770 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1771 { 1772 uint32_t count; 1773 uint32_t hcint; 1774 uint32_t hcchar; 1775 uint8_t delta; 1776 uint8_t channel; 1777 uint8_t x; 1778 1779 dwc_otg_host_dump_rx(sc, td); 1780 1781 /* check that last channel is complete */ 1782 channel = td->channel[td->npkt]; 1783 1784 if (channel < DWC_OTG_MAX_CHANNELS) { 1785 hcint = sc->sc_chan_state[channel].hcint; 1786 1787 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1788 channel, td->state, hcint, 1789 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1790 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1791 1792 if (hcint & (HCINT_RETRY | 1793 HCINT_ACK | HCINT_NYET)) { 1794 /* give success bits priority over failure bits */ 1795 } else if (hcint & HCINT_STALL) { 1796 DPRINTF("CH=%d STALL\n", channel); 1797 td->error_stall = 1; 1798 td->error_any = 1; 1799 goto complete; 1800 } else if (hcint & HCINT_ERRORS) { 1801 DPRINTF("CH=%d ERROR\n", channel); 1802 td->errcnt++; 1803 if (td->hcsplt != 0 || td->errcnt >= 3) { 1804 td->error_any = 1; 1805 goto complete; 1806 } 1807 } 1808 1809 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1810 HCINT_ACK | HCINT_NYET)) { 1811 1812 if (!(hcint & HCINT_ERRORS)) 1813 td->errcnt = 0; 1814 } 1815 } else { 1816 hcint = 0; 1817 } 1818 1819 switch (td->state) { 1820 case DWC_CHAN_ST_START: 1821 goto send_pkt; 1822 1823 case DWC_CHAN_ST_WAIT_ANE: 1824 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1825 td->did_nak = 1; 1826 td->tt_scheduled = 0; 1827 goto send_pkt; 1828 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1829 td->offset += td->tx_bytes; 1830 td->remainder -= td->tx_bytes; 1831 td->toggle ^= 1; 1832 /* check if next response will be a NAK */ 1833 if (hcint & HCINT_NYET) 1834 td->did_nak = 1; 1835 else 1836 td->did_nak = 0; 1837 td->tt_scheduled = 0; 1838 1839 /* check remainder */ 1840 if (td->remainder == 0) { 1841 if (td->short_pkt) 1842 goto complete; 1843 1844 /* 1845 * Else we need to transmit a short 1846 * packet: 1847 */ 1848 } 1849 goto send_pkt; 1850 } 1851 break; 1852 1853 case DWC_CHAN_ST_WAIT_S_ANE: 1854 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1855 td->did_nak = 1; 1856 td->tt_scheduled = 0; 1857 goto send_pkt; 1858 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1859 td->did_nak = 0; 1860 goto send_cpkt; 1861 } 1862 break; 1863 1864 case DWC_CHAN_ST_WAIT_C_ANE: 1865 if (hcint & HCINT_NYET) { 1866 goto send_cpkt; 1867 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1868 td->did_nak = 1; 1869 td->tt_scheduled = 0; 1870 goto send_pkt; 1871 } else if (hcint & HCINT_ACK) { 1872 td->offset += td->tx_bytes; 1873 td->remainder -= td->tx_bytes; 1874 td->toggle ^= 1; 1875 td->did_nak = 0; 1876 td->tt_scheduled = 0; 1877 1878 /* check remainder */ 1879 if (td->remainder == 0) { 1880 if (td->short_pkt) 1881 goto complete; 1882 1883 /* else we need to transmit a short packet */ 1884 } 1885 goto send_pkt; 1886 } 1887 break; 1888 1889 case DWC_CHAN_ST_WAIT_C_PKT: 1890 goto send_cpkt; 1891 1892 case DWC_CHAN_ST_TX_WAIT_ISOC: 1893 /* Check if ISOCHRONOUS OUT traffic is complete */ 1894 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1895 break; 1896 1897 td->offset += td->tx_bytes; 1898 td->remainder -= td->tx_bytes; 1899 goto complete; 1900 default: 1901 break; 1902 } 1903 goto busy; 1904 1905 send_pkt: 1906 /* free existing channel(s), if any */ 1907 dwc_otg_host_channel_free(sc, td); 1908 1909 if (td->hcsplt != 0) { 1910 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1911 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1912 td->state = DWC_CHAN_ST_START; 1913 goto busy; 1914 } 1915 delta = sc->sc_last_frame_num - td->tt_start_slot; 1916 if (delta > 5) { 1917 /* missed it */ 1918 td->tt_scheduled = 0; 1919 td->state = DWC_CHAN_ST_START; 1920 goto busy; 1921 } 1922 } else if (dwc_otg_host_rate_check(sc, td)) { 1923 td->state = DWC_CHAN_ST_START; 1924 goto busy; 1925 } 1926 1927 /* allocate a new channel */ 1928 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1929 td->state = DWC_CHAN_ST_START; 1930 goto busy; 1931 } 1932 1933 /* set toggle, if any */ 1934 if (td->set_toggle) { 1935 td->set_toggle = 0; 1936 td->toggle = 1; 1937 } 1938 1939 if (td->ep_type == UE_ISOCHRONOUS) { 1940 /* ISOCHRONOUS OUT transfers don't have any ACKs */ 1941 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1942 td->hcsplt &= ~HCSPLT_COMPSPLT; 1943 if (td->hcsplt != 0) { 1944 /* get maximum transfer length */ 1945 count = td->remainder; 1946 if (count > HCSPLT_XACTLEN_BURST) { 1947 DPRINTF("TT overflow\n"); 1948 td->error_any = 1; 1949 goto complete; 1950 } 1951 /* Update transaction position */ 1952 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1953 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1954 } 1955 } else if (td->hcsplt != 0) { 1956 td->hcsplt &= ~HCSPLT_COMPSPLT; 1957 /* Wait for ACK/NAK/ERR from TT */ 1958 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1959 } else { 1960 /* Wait for ACK/NAK/STALL from device */ 1961 td->state = DWC_CHAN_ST_WAIT_ANE; 1962 } 1963 1964 td->tx_bytes = 0; 1965 1966 for (x = 0; x != td->max_packet_count; x++) { 1967 uint32_t rem_bytes; 1968 1969 channel = td->channel[x]; 1970 1971 /* send one packet at a time */ 1972 count = td->max_packet_size; 1973 rem_bytes = td->remainder - td->tx_bytes; 1974 if (rem_bytes < count) { 1975 /* we have a short packet */ 1976 td->short_pkt = 1; 1977 count = rem_bytes; 1978 } 1979 if (count == rem_bytes) { 1980 /* last packet */ 1981 switch (x) { 1982 case 0: 1983 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1984 (count << HCTSIZ_XFERSIZE_SHIFT) | 1985 (1 << HCTSIZ_PKTCNT_SHIFT) | 1986 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1987 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1988 break; 1989 case 1: 1990 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1991 (count << HCTSIZ_XFERSIZE_SHIFT) | 1992 (1 << HCTSIZ_PKTCNT_SHIFT) | 1993 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1994 break; 1995 default: 1996 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1997 (count << HCTSIZ_XFERSIZE_SHIFT) | 1998 (1 << HCTSIZ_PKTCNT_SHIFT) | 1999 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 2000 break; 2001 } 2002 } else if (td->ep_type == UE_ISOCHRONOUS && 2003 td->max_packet_count > 1) { 2004 /* ISOCHRONOUS multi packet */ 2005 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2006 (count << HCTSIZ_XFERSIZE_SHIFT) | 2007 (1 << HCTSIZ_PKTCNT_SHIFT) | 2008 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 2009 } else { 2010 /* TODO: HCTSIZ_DOPNG */ 2011 /* standard BULK/INTERRUPT/CONTROL packet */ 2012 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2013 (count << HCTSIZ_XFERSIZE_SHIFT) | 2014 (1 << HCTSIZ_PKTCNT_SHIFT) | 2015 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 2016 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 2017 } 2018 2019 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 2020 2021 hcchar = td->hcchar; 2022 hcchar &= ~HCCHAR_EPDIR_IN; 2023 2024 /* send after next SOF event */ 2025 if ((sc->sc_last_frame_num & 1) == 0 && 2026 td->ep_type == UE_ISOCHRONOUS) 2027 hcchar |= HCCHAR_ODDFRM; 2028 else 2029 hcchar &= ~HCCHAR_ODDFRM; 2030 2031 /* must enable before writing data to FIFO */ 2032 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 2033 2034 if (count != 0) { 2035 /* write data into FIFO */ 2036 dwc_otg_write_fifo(sc, td->pc, td->offset + 2037 td->tx_bytes, DOTG_DFIFO(channel), count); 2038 } 2039 2040 /* store number of bytes transmitted */ 2041 td->tx_bytes += count; 2042 2043 /* store last packet index */ 2044 td->npkt = x; 2045 2046 /* check for last packet */ 2047 if (count == rem_bytes) 2048 break; 2049 } 2050 goto busy; 2051 2052 send_cpkt: 2053 /* free existing channel, if any */ 2054 dwc_otg_host_channel_free(sc, td); 2055 2056 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 2057 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 2058 td->state = DWC_CHAN_ST_WAIT_C_PKT; 2059 goto busy; 2060 } 2061 delta = sc->sc_last_frame_num - td->tt_start_slot; 2062 if (delta > DWC_OTG_TT_SLOT_MAX) { 2063 /* we missed the service interval */ 2064 if (td->ep_type != UE_ISOCHRONOUS) 2065 td->error_any = 1; 2066 goto complete; 2067 } 2068 2069 /* allocate a new channel */ 2070 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 2071 td->state = DWC_CHAN_ST_WAIT_C_PKT; 2072 goto busy; 2073 } 2074 2075 channel = td->channel[0]; 2076 2077 td->hcsplt |= HCSPLT_COMPSPLT; 2078 td->state = DWC_CHAN_ST_WAIT_C_ANE; 2079 2080 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2081 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 2082 2083 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 2084 2085 hcchar = td->hcchar; 2086 hcchar &= ~HCCHAR_EPDIR_IN; 2087 2088 /* receive complete split ASAP */ 2089 if ((sc->sc_last_frame_num & 1) != 0 && 2090 td->ep_type == UE_ISOCHRONOUS) 2091 hcchar |= HCCHAR_ODDFRM; 2092 else 2093 hcchar &= ~HCCHAR_ODDFRM; 2094 2095 /* must enable channel before data can be received */ 2096 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 2097 2098 /* wait until next slot before trying complete split */ 2099 td->tt_complete_slot = sc->sc_last_frame_num + 1; 2100 busy: 2101 return (1); /* busy */ 2102 2103 complete: 2104 dwc_otg_host_channel_free(sc, td); 2105 return (0); /* complete */ 2106 } 2107 2108 static uint8_t 2109 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2110 { 2111 uint32_t max_buffer; 2112 uint32_t count; 2113 uint32_t fifo_left; 2114 uint32_t mpkt; 2115 uint32_t temp; 2116 uint8_t to; 2117 2118 to = 3; /* don't loop forever! */ 2119 2120 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 2121 2122 repeat: 2123 /* check for for endpoint 0 data */ 2124 2125 temp = sc->sc_last_rx_status; 2126 2127 if ((td->ep_no == 0) && (temp != 0) && 2128 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2129 2130 if ((temp & GRXSTSRD_PKTSTS_MASK) != 2131 GRXSTSRD_STP_DATA && 2132 (temp & GRXSTSRD_PKTSTS_MASK) != 2133 GRXSTSRD_STP_COMPLETE) { 2134 2135 /* dump data - wrong direction */ 2136 dwc_otg_common_rx_ack(sc); 2137 } else { 2138 /* 2139 * The current transfer was cancelled 2140 * by the USB Host: 2141 */ 2142 td->error_any = 1; 2143 return (0); /* complete */ 2144 } 2145 } 2146 2147 /* fill in more TX data, if possible */ 2148 if (td->tx_bytes != 0) { 2149 2150 uint16_t cpkt; 2151 2152 /* check if packets have been transferred */ 2153 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2154 2155 /* get current packet number */ 2156 cpkt = DXEPTSIZ_GET_NPKT(temp); 2157 2158 if (cpkt >= td->npkt) { 2159 fifo_left = 0; 2160 } else { 2161 if (max_buffer != 0) { 2162 fifo_left = (td->npkt - cpkt) * 2163 td->max_packet_size; 2164 2165 if (fifo_left > max_buffer) 2166 fifo_left = max_buffer; 2167 } else { 2168 fifo_left = td->max_packet_size; 2169 } 2170 } 2171 2172 count = td->tx_bytes; 2173 if (count > fifo_left) 2174 count = fifo_left; 2175 2176 if (count != 0) { 2177 /* write data into FIFO */ 2178 dwc_otg_write_fifo(sc, td->pc, td->offset, 2179 DOTG_DFIFO(td->ep_no), count); 2180 2181 td->tx_bytes -= count; 2182 td->remainder -= count; 2183 td->offset += count; 2184 td->npkt = cpkt; 2185 } 2186 if (td->tx_bytes != 0) 2187 goto not_complete; 2188 2189 /* check remainder */ 2190 if (td->remainder == 0) { 2191 if (td->short_pkt) 2192 return (0); /* complete */ 2193 2194 /* else we need to transmit a short packet */ 2195 } 2196 } 2197 2198 if (!to--) 2199 goto not_complete; 2200 2201 /* check if not all packets have been transferred */ 2202 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2203 2204 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2205 2206 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2207 "DIEPCTL=0x%08x\n", td->ep_no, 2208 DXEPTSIZ_GET_NPKT(temp), 2209 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2210 2211 goto not_complete; 2212 } 2213 2214 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2215 2216 /* try to optimise by sending more data */ 2217 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2218 2219 /* send multiple packets at the same time */ 2220 mpkt = max_buffer / td->max_packet_size; 2221 2222 if (mpkt > 0x3FE) 2223 mpkt = 0x3FE; 2224 2225 count = td->remainder; 2226 if (count > 0x7FFFFF) 2227 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2228 2229 td->npkt = count / td->max_packet_size; 2230 2231 /* 2232 * NOTE: We could use 0x3FE instead of "mpkt" in the 2233 * check below to get more throughput, but then we 2234 * have a dependency towards non-generic chip features 2235 * to disable the TX-FIFO-EMPTY interrupts on a per 2236 * endpoint basis. Increase the maximum buffer size of 2237 * the IN endpoint to increase the performance. 2238 */ 2239 if (td->npkt > mpkt) { 2240 td->npkt = mpkt; 2241 count = td->max_packet_size * mpkt; 2242 } else if ((count == 0) || (count % td->max_packet_size)) { 2243 /* we are transmitting a short packet */ 2244 td->npkt++; 2245 td->short_pkt = 1; 2246 } 2247 } else { 2248 /* send one packet at a time */ 2249 mpkt = 1; 2250 count = td->max_packet_size; 2251 if (td->remainder < count) { 2252 /* we have a short packet */ 2253 td->short_pkt = 1; 2254 count = td->remainder; 2255 } 2256 td->npkt = 1; 2257 } 2258 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2259 DXEPTSIZ_SET_MULTI(1) | 2260 DXEPTSIZ_SET_NPKT(td->npkt) | 2261 DXEPTSIZ_SET_NBYTES(count)); 2262 2263 /* make room for buffering */ 2264 td->npkt += mpkt; 2265 2266 temp = sc->sc_in_ctl[td->ep_no]; 2267 2268 /* check for isochronous mode */ 2269 if ((temp & DIEPCTL_EPTYPE_MASK) == 2270 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 2271 /* toggle odd or even frame bit */ 2272 if (temp & DIEPCTL_SETD1PID) { 2273 temp &= ~DIEPCTL_SETD1PID; 2274 temp |= DIEPCTL_SETD0PID; 2275 } else { 2276 temp &= ~DIEPCTL_SETD0PID; 2277 temp |= DIEPCTL_SETD1PID; 2278 } 2279 sc->sc_in_ctl[td->ep_no] = temp; 2280 } 2281 2282 /* must enable before writing data to FIFO */ 2283 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2284 DIEPCTL_EPENA | DIEPCTL_CNAK); 2285 2286 td->tx_bytes = count; 2287 2288 /* check remainder */ 2289 if (td->tx_bytes == 0 && 2290 td->remainder == 0) { 2291 if (td->short_pkt) 2292 return (0); /* complete */ 2293 2294 /* else we need to transmit a short packet */ 2295 } 2296 goto repeat; 2297 2298 not_complete: 2299 return (1); /* not complete */ 2300 } 2301 2302 static uint8_t 2303 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2304 { 2305 uint32_t temp; 2306 2307 /* 2308 * If all packets are transferred we are complete: 2309 */ 2310 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2311 2312 /* check that all packets have been transferred */ 2313 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2314 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2315 goto not_complete; 2316 } 2317 return (0); 2318 2319 not_complete: 2320 2321 /* we only want to know if there is a SETUP packet or free IN packet */ 2322 2323 temp = sc->sc_last_rx_status; 2324 2325 if ((td->ep_no == 0) && (temp != 0) && 2326 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2327 2328 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2329 GRXSTSRD_STP_DATA || 2330 (temp & GRXSTSRD_PKTSTS_MASK) == 2331 GRXSTSRD_STP_COMPLETE) { 2332 DPRINTFN(5, "faking complete\n"); 2333 /* 2334 * Race condition: We are complete! 2335 */ 2336 return (0); 2337 } else { 2338 /* dump data - wrong direction */ 2339 dwc_otg_common_rx_ack(sc); 2340 } 2341 } 2342 return (1); /* not complete */ 2343 } 2344 2345 static void 2346 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2347 { 2348 struct dwc_otg_td *td; 2349 uint8_t toggle; 2350 uint8_t tmr_val; 2351 uint8_t tmr_res; 2352 2353 DPRINTFN(9, "\n"); 2354 2355 td = xfer->td_transfer_cache; 2356 if (td == NULL) 2357 return; 2358 2359 while (1) { 2360 if ((td->func) (sc, td)) { 2361 /* operation in progress */ 2362 break; 2363 } 2364 if (((void *)td) == xfer->td_transfer_last) { 2365 goto done; 2366 } 2367 if (td->error_any) { 2368 goto done; 2369 } else if (td->remainder > 0) { 2370 /* 2371 * We had a short transfer. If there is no alternate 2372 * next, stop processing ! 2373 */ 2374 if (!td->alt_next) 2375 goto done; 2376 } 2377 2378 /* 2379 * Fetch the next transfer descriptor and transfer 2380 * some flags to the next transfer descriptor 2381 */ 2382 tmr_res = td->tmr_res; 2383 tmr_val = td->tmr_val; 2384 toggle = td->toggle; 2385 td = td->obj_next; 2386 xfer->td_transfer_cache = td; 2387 td->toggle = toggle; /* transfer toggle */ 2388 td->tmr_res = tmr_res; 2389 td->tmr_val = tmr_val; 2390 } 2391 return; 2392 2393 done: 2394 xfer->td_transfer_cache = NULL; 2395 sc->sc_xfer_complete = 1; 2396 } 2397 2398 static uint8_t 2399 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2400 { 2401 struct dwc_otg_td *td; 2402 2403 DPRINTFN(9, "\n"); 2404 2405 td = xfer->td_transfer_cache; 2406 if (td == NULL) { 2407 /* compute all actual lengths */ 2408 dwc_otg_standard_done(xfer); 2409 return (1); 2410 } 2411 return (0); 2412 } 2413 2414 static void 2415 dwc_otg_timer(void *_sc) 2416 { 2417 struct dwc_otg_softc *sc = _sc; 2418 2419 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2420 2421 DPRINTF("\n"); 2422 2423 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2424 2425 /* increment timer value */ 2426 sc->sc_tmr_val++; 2427 2428 /* enable SOF interrupt, which will poll jobs */ 2429 dwc_otg_enable_sof_irq(sc); 2430 2431 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2432 2433 if (sc->sc_timer_active) { 2434 /* restart timer */ 2435 usb_callout_reset(&sc->sc_timer, 2436 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2437 &dwc_otg_timer, sc); 2438 } 2439 } 2440 2441 static void 2442 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2443 { 2444 if (sc->sc_timer_active != 0) 2445 return; 2446 2447 sc->sc_timer_active = 1; 2448 2449 /* restart timer */ 2450 usb_callout_reset(&sc->sc_timer, 2451 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2452 &dwc_otg_timer, sc); 2453 } 2454 2455 static void 2456 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2457 { 2458 if (sc->sc_timer_active == 0) 2459 return; 2460 2461 sc->sc_timer_active = 0; 2462 2463 /* stop timer */ 2464 usb_callout_stop(&sc->sc_timer); 2465 } 2466 2467 static uint16_t 2468 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) 2469 { 2470 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) 2471 pinfo->slot_index++; 2472 return (pinfo->slot_index); 2473 } 2474 2475 static uint8_t 2476 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2477 { 2478 TAILQ_HEAD(, usb_xfer) head; 2479 struct usb_xfer *xfer; 2480 struct usb_xfer *xfer_next; 2481 struct dwc_otg_td *td; 2482 uint16_t temp; 2483 uint16_t slot; 2484 2485 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2486 2487 if (sc->sc_last_frame_num == temp) 2488 return (0); 2489 2490 sc->sc_last_frame_num = temp; 2491 2492 TAILQ_INIT(&head); 2493 2494 if ((temp & 7) == 0) { 2495 2496 /* reset the schedule */ 2497 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2498 2499 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2500 td = xfer->td_transfer_cache; 2501 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2502 continue; 2503 2504 /* check for IN direction */ 2505 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2506 continue; 2507 2508 sc->sc_needsof = 1; 2509 2510 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2511 continue; 2512 2513 /* compute slot */ 2514 slot = dwc_otg_compute_isoc_rx_tt_slot( 2515 sc->sc_tt_info + td->tt_index); 2516 if (slot > 3) { 2517 /* 2518 * Not enough time to get complete 2519 * split executed. 2520 */ 2521 continue; 2522 } 2523 /* Delayed start */ 2524 td->tt_start_slot = temp + slot; 2525 td->tt_scheduled = 1; 2526 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2527 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2528 } 2529 2530 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2531 td = xfer->td_transfer_cache; 2532 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2533 continue; 2534 2535 /* check for OUT direction */ 2536 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2537 continue; 2538 2539 sc->sc_needsof = 1; 2540 2541 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2542 continue; 2543 2544 /* Start ASAP */ 2545 td->tt_start_slot = temp; 2546 td->tt_scheduled = 1; 2547 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2548 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2549 } 2550 2551 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2552 td = xfer->td_transfer_cache; 2553 if (td == NULL || td->ep_type != UE_INTERRUPT) 2554 continue; 2555 2556 if (td->tt_scheduled != 0) { 2557 sc->sc_needsof = 1; 2558 continue; 2559 } 2560 2561 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2562 continue; 2563 2564 if (td->hcsplt == 0) { 2565 sc->sc_needsof = 1; 2566 td->tt_scheduled = 1; 2567 continue; 2568 } 2569 2570 /* start ASAP */ 2571 td->tt_start_slot = temp; 2572 sc->sc_needsof = 1; 2573 td->tt_scheduled = 1; 2574 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2575 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2576 } 2577 2578 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2579 td = xfer->td_transfer_cache; 2580 if (td == NULL || 2581 td->ep_type != UE_CONTROL) { 2582 continue; 2583 } 2584 2585 sc->sc_needsof = 1; 2586 2587 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2588 continue; 2589 2590 /* start ASAP */ 2591 td->tt_start_slot = temp; 2592 td->tt_scheduled = 1; 2593 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2594 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2595 } 2596 } 2597 if ((temp & 7) < 6) { 2598 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2599 td = xfer->td_transfer_cache; 2600 if (td == NULL || 2601 td->ep_type != UE_BULK) { 2602 continue; 2603 } 2604 2605 sc->sc_needsof = 1; 2606 2607 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2608 continue; 2609 2610 /* start ASAP */ 2611 td->tt_start_slot = temp; 2612 td->tt_scheduled = 1; 2613 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2614 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2615 } 2616 } 2617 2618 /* Put TT transfers in execution order at the end */ 2619 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2620 2621 /* move all TT transfers in front, keeping the current order */ 2622 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2623 td = xfer->td_transfer_cache; 2624 if (td == NULL || td->hcsplt == 0) 2625 continue; 2626 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2627 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2628 } 2629 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2630 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2631 2632 /* put non-TT non-ISOCHRONOUS transfers last */ 2633 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2634 td = xfer->td_transfer_cache; 2635 if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS) 2636 continue; 2637 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2638 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2639 } 2640 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2641 2642 if ((temp & 7) == 0) { 2643 2644 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2645 (int)temp, (int)sc->sc_needsof); 2646 2647 /* update SOF IRQ mask */ 2648 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2649 if (sc->sc_needsof == 0) { 2650 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2651 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2652 } 2653 } else { 2654 if (sc->sc_needsof != 0) { 2655 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2656 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2657 } 2658 } 2659 2660 /* clear need SOF flag */ 2661 sc->sc_needsof = 0; 2662 } 2663 return (1); 2664 } 2665 2666 static void 2667 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2668 { 2669 struct usb_xfer *xfer; 2670 uint32_t count; 2671 uint32_t temp; 2672 uint32_t haint; 2673 uint8_t got_rx_status; 2674 uint8_t x; 2675 2676 if (sc->sc_flags.status_device_mode == 0) { 2677 /* 2678 * Update host transfer schedule, so that new 2679 * transfers can be issued: 2680 */ 2681 dwc_otg_update_host_transfer_schedule_locked(sc); 2682 } 2683 count = 0; 2684 repeat: 2685 if (++count == 16) { 2686 /* give other interrupts a chance */ 2687 DPRINTF("Yield\n"); 2688 return; 2689 } 2690 2691 /* get all host channel interrupts */ 2692 haint = DWC_OTG_READ_4(sc, DOTG_HAINT); 2693 while (1) { 2694 x = ffs(haint) - 1; 2695 if (x >= sc->sc_host_ch_max) 2696 break; 2697 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2698 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2699 temp &= ~HCINT_SOFTWARE_ONLY; 2700 sc->sc_chan_state[x].hcint |= temp; 2701 haint &= ~(1U << x); 2702 } 2703 2704 if (sc->sc_last_rx_status == 0) { 2705 2706 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2707 if (temp & GINTSTS_RXFLVL) { 2708 /* pop current status */ 2709 sc->sc_last_rx_status = 2710 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2711 } 2712 2713 if (sc->sc_last_rx_status != 0) { 2714 2715 uint8_t ep_no; 2716 2717 temp = sc->sc_last_rx_status & 2718 GRXSTSRD_PKTSTS_MASK; 2719 2720 /* non-data messages we simply skip */ 2721 if (temp != GRXSTSRD_STP_DATA && 2722 temp != GRXSTSRD_STP_COMPLETE && 2723 temp != GRXSTSRD_OUT_DATA) { 2724 /* check for halted channel */ 2725 if (temp == GRXSTSRH_HALTED) { 2726 ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status); 2727 sc->sc_chan_state[ep_no].wait_halted = 0; 2728 DPRINTFN(5, "channel halt complete ch=%u\n", ep_no); 2729 } 2730 /* store bytes and FIFO offset */ 2731 sc->sc_current_rx_bytes = 0; 2732 sc->sc_current_rx_fifo = 0; 2733 2734 /* acknowledge status */ 2735 dwc_otg_common_rx_ack(sc); 2736 goto repeat; 2737 } 2738 2739 temp = GRXSTSRD_BCNT_GET( 2740 sc->sc_last_rx_status); 2741 ep_no = GRXSTSRD_CHNUM_GET( 2742 sc->sc_last_rx_status); 2743 2744 /* store bytes and FIFO offset */ 2745 sc->sc_current_rx_bytes = (temp + 3) & ~3; 2746 sc->sc_current_rx_fifo = DOTG_DFIFO(ep_no); 2747 2748 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2749 2750 /* check if we should dump the data */ 2751 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2752 dwc_otg_common_rx_ack(sc); 2753 goto repeat; 2754 } 2755 2756 got_rx_status = 1; 2757 2758 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2759 sc->sc_last_rx_status, ep_no, 2760 (sc->sc_last_rx_status >> 15) & 3, 2761 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2762 (sc->sc_last_rx_status >> 17) & 15); 2763 } else { 2764 got_rx_status = 0; 2765 } 2766 } else { 2767 uint8_t ep_no; 2768 2769 ep_no = GRXSTSRD_CHNUM_GET( 2770 sc->sc_last_rx_status); 2771 2772 /* check if we should dump the data */ 2773 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2774 dwc_otg_common_rx_ack(sc); 2775 goto repeat; 2776 } 2777 2778 got_rx_status = 1; 2779 } 2780 2781 /* execute FIFOs */ 2782 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2783 dwc_otg_xfer_do_fifo(sc, xfer); 2784 2785 if (got_rx_status) { 2786 /* check if data was consumed */ 2787 if (sc->sc_last_rx_status == 0) 2788 goto repeat; 2789 2790 /* disable RX FIFO level interrupt */ 2791 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2792 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2793 } 2794 } 2795 2796 static void 2797 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2798 { 2799 struct usb_xfer *xfer; 2800 repeat: 2801 /* scan for completion events */ 2802 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2803 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2804 goto repeat; 2805 } 2806 } 2807 2808 static void 2809 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2810 { 2811 DPRINTFN(5, "vbus = %u\n", is_on); 2812 2813 /* 2814 * If the USB host mode is forced, then assume VBUS is always 2815 * present else rely on the input to this function: 2816 */ 2817 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2818 2819 if (!sc->sc_flags.status_vbus) { 2820 sc->sc_flags.status_vbus = 1; 2821 2822 /* complete root HUB interrupt endpoint */ 2823 2824 dwc_otg_root_intr(sc); 2825 } 2826 } else { 2827 if (sc->sc_flags.status_vbus) { 2828 sc->sc_flags.status_vbus = 0; 2829 sc->sc_flags.status_bus_reset = 0; 2830 sc->sc_flags.status_suspend = 0; 2831 sc->sc_flags.change_suspend = 0; 2832 sc->sc_flags.change_connect = 1; 2833 2834 /* complete root HUB interrupt endpoint */ 2835 2836 dwc_otg_root_intr(sc); 2837 } 2838 } 2839 } 2840 2841 int 2842 dwc_otg_filter_interrupt(void *arg) 2843 { 2844 struct dwc_otg_softc *sc = arg; 2845 int retval = FILTER_HANDLED; 2846 uint32_t status; 2847 2848 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2849 2850 /* read and clear interrupt status */ 2851 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2852 2853 /* clear interrupts we are handling here */ 2854 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2855 2856 /* check for USB state change interrupts */ 2857 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2858 retval = FILTER_SCHEDULE_THREAD; 2859 2860 /* clear FIFO empty interrupts */ 2861 if (status & sc->sc_irq_mask & 2862 (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) { 2863 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); 2864 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2865 } 2866 /* clear all IN endpoint interrupts */ 2867 if (status & GINTSTS_IEPINT) { 2868 uint32_t temp; 2869 uint8_t x; 2870 2871 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2872 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2873 if (temp & DIEPMSK_XFERCOMPLMSK) { 2874 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2875 DIEPMSK_XFERCOMPLMSK); 2876 } 2877 } 2878 } 2879 2880 /* poll FIFOs, if any */ 2881 dwc_otg_interrupt_poll_locked(sc); 2882 2883 if (sc->sc_xfer_complete != 0) 2884 retval = FILTER_SCHEDULE_THREAD; 2885 2886 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2887 2888 return (retval); 2889 } 2890 2891 void 2892 dwc_otg_interrupt(void *arg) 2893 { 2894 struct dwc_otg_softc *sc = arg; 2895 uint32_t status; 2896 2897 USB_BUS_LOCK(&sc->sc_bus); 2898 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2899 2900 /* read and clear interrupt status */ 2901 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2902 2903 /* clear interrupts we are handling here */ 2904 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2905 2906 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2907 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2908 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2909 2910 if (status & GINTSTS_USBRST) { 2911 2912 /* set correct state */ 2913 sc->sc_flags.status_device_mode = 1; 2914 sc->sc_flags.status_bus_reset = 0; 2915 sc->sc_flags.status_suspend = 0; 2916 sc->sc_flags.change_suspend = 0; 2917 sc->sc_flags.change_connect = 1; 2918 2919 /* Disable SOF interrupt */ 2920 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2921 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2922 2923 /* complete root HUB interrupt endpoint */ 2924 dwc_otg_root_intr(sc); 2925 } 2926 2927 /* check for any bus state change interrupts */ 2928 if (status & GINTSTS_ENUMDONE) { 2929 2930 uint32_t temp; 2931 2932 DPRINTFN(5, "end of reset\n"); 2933 2934 /* set correct state */ 2935 sc->sc_flags.status_device_mode = 1; 2936 sc->sc_flags.status_bus_reset = 1; 2937 sc->sc_flags.status_suspend = 0; 2938 sc->sc_flags.change_suspend = 0; 2939 sc->sc_flags.change_connect = 1; 2940 sc->sc_flags.status_low_speed = 0; 2941 sc->sc_flags.port_enabled = 1; 2942 2943 /* reset FIFOs */ 2944 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2945 2946 /* reset function address */ 2947 dwc_otg_set_address(sc, 0); 2948 2949 /* figure out enumeration speed */ 2950 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2951 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2952 sc->sc_flags.status_high_speed = 1; 2953 else 2954 sc->sc_flags.status_high_speed = 0; 2955 2956 /* 2957 * Disable resume and SOF interrupt, and enable 2958 * suspend and RX frame interrupt: 2959 */ 2960 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2961 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 2962 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2963 2964 /* complete root HUB interrupt endpoint */ 2965 dwc_otg_root_intr(sc); 2966 } 2967 2968 if (status & GINTSTS_PRTINT) { 2969 uint32_t hprt; 2970 2971 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2972 2973 /* clear change bits */ 2974 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2975 HPRT_PRTPWR | HPRT_PRTENCHNG | 2976 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2977 sc->sc_hprt_val); 2978 2979 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2980 2981 sc->sc_flags.status_device_mode = 0; 2982 2983 if (hprt & HPRT_PRTCONNSTS) 2984 sc->sc_flags.status_bus_reset = 1; 2985 else 2986 sc->sc_flags.status_bus_reset = 0; 2987 2988 if ((hprt & HPRT_PRTENCHNG) && 2989 (hprt & HPRT_PRTENA) == 0) 2990 sc->sc_flags.change_enabled = 1; 2991 2992 if (hprt & HPRT_PRTENA) 2993 sc->sc_flags.port_enabled = 1; 2994 else 2995 sc->sc_flags.port_enabled = 0; 2996 2997 if (hprt & HPRT_PRTOVRCURRCHNG) 2998 sc->sc_flags.change_over_current = 1; 2999 3000 if (hprt & HPRT_PRTOVRCURRACT) 3001 sc->sc_flags.port_over_current = 1; 3002 else 3003 sc->sc_flags.port_over_current = 0; 3004 3005 if (hprt & HPRT_PRTPWR) 3006 sc->sc_flags.port_powered = 1; 3007 else 3008 sc->sc_flags.port_powered = 0; 3009 3010 if (((hprt & HPRT_PRTSPD_MASK) 3011 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 3012 sc->sc_flags.status_low_speed = 1; 3013 else 3014 sc->sc_flags.status_low_speed = 0; 3015 3016 if (((hprt & HPRT_PRTSPD_MASK) 3017 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 3018 sc->sc_flags.status_high_speed = 1; 3019 else 3020 sc->sc_flags.status_high_speed = 0; 3021 3022 if (hprt & HPRT_PRTCONNDET) 3023 sc->sc_flags.change_connect = 1; 3024 3025 if (hprt & HPRT_PRTSUSP) 3026 dwc_otg_suspend_irq(sc); 3027 else 3028 dwc_otg_resume_irq(sc); 3029 3030 /* complete root HUB interrupt endpoint */ 3031 dwc_otg_root_intr(sc); 3032 3033 /* update host frame interval */ 3034 dwc_otg_update_host_frame_interval(sc); 3035 } 3036 3037 /* 3038 * If resume and suspend is set at the same time we interpret 3039 * that like RESUME. Resume is set when there is at least 3 3040 * milliseconds of inactivity on the USB BUS. 3041 */ 3042 if (status & GINTSTS_WKUPINT) { 3043 3044 DPRINTFN(5, "resume interrupt\n"); 3045 3046 dwc_otg_resume_irq(sc); 3047 3048 } else if (status & GINTSTS_USBSUSP) { 3049 3050 DPRINTFN(5, "suspend interrupt\n"); 3051 3052 dwc_otg_suspend_irq(sc); 3053 } 3054 /* check VBUS */ 3055 if (status & (GINTSTS_USBSUSP | 3056 GINTSTS_USBRST | 3057 GINTMSK_OTGINTMSK | 3058 GINTSTS_SESSREQINT)) { 3059 uint32_t temp; 3060 3061 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3062 3063 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 3064 3065 dwc_otg_vbus_interrupt(sc, 3066 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3067 } 3068 3069 if (sc->sc_xfer_complete != 0) { 3070 sc->sc_xfer_complete = 0; 3071 3072 /* complete FIFOs, if any */ 3073 dwc_otg_interrupt_complete_locked(sc); 3074 } 3075 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3076 USB_BUS_UNLOCK(&sc->sc_bus); 3077 } 3078 3079 static void 3080 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 3081 { 3082 struct dwc_otg_td *td; 3083 3084 /* get current Transfer Descriptor */ 3085 td = temp->td_next; 3086 temp->td = td; 3087 3088 /* prepare for next TD */ 3089 temp->td_next = td->obj_next; 3090 3091 /* fill out the Transfer Descriptor */ 3092 td->func = temp->func; 3093 td->pc = temp->pc; 3094 td->offset = temp->offset; 3095 td->remainder = temp->len; 3096 td->tx_bytes = 0; 3097 td->error_any = 0; 3098 td->error_stall = 0; 3099 td->npkt = 0; 3100 td->did_stall = temp->did_stall; 3101 td->short_pkt = temp->short_pkt; 3102 td->alt_next = temp->setup_alt_next; 3103 td->set_toggle = 0; 3104 td->got_short = 0; 3105 td->did_nak = 0; 3106 td->channel[0] = DWC_OTG_MAX_CHANNELS; 3107 td->channel[1] = DWC_OTG_MAX_CHANNELS; 3108 td->channel[2] = DWC_OTG_MAX_CHANNELS; 3109 td->state = 0; 3110 td->errcnt = 0; 3111 td->tt_scheduled = 0; 3112 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 3113 } 3114 3115 static void 3116 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 3117 { 3118 struct dwc_otg_std_temp temp; 3119 struct dwc_otg_td *td; 3120 uint32_t x; 3121 uint8_t need_sync; 3122 uint8_t is_host; 3123 3124 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 3125 xfer->address, UE_GET_ADDR(xfer->endpointno), 3126 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 3127 3128 temp.max_frame_size = xfer->max_frame_size; 3129 3130 td = xfer->td_start[0]; 3131 xfer->td_transfer_first = td; 3132 xfer->td_transfer_cache = td; 3133 3134 /* setup temp */ 3135 3136 temp.pc = NULL; 3137 temp.td = NULL; 3138 temp.td_next = xfer->td_start[0]; 3139 temp.offset = 0; 3140 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3141 xfer->flags_int.isochronous_xfr; 3142 temp.did_stall = !xfer->flags_int.control_stall; 3143 3144 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3145 3146 /* check if we should prepend a setup message */ 3147 3148 if (xfer->flags_int.control_xfr) { 3149 if (xfer->flags_int.control_hdr) { 3150 3151 if (is_host) 3152 temp.func = &dwc_otg_host_setup_tx; 3153 else 3154 temp.func = &dwc_otg_setup_rx; 3155 3156 temp.len = xfer->frlengths[0]; 3157 temp.pc = xfer->frbuffers + 0; 3158 temp.short_pkt = temp.len ? 1 : 0; 3159 3160 /* check for last frame */ 3161 if (xfer->nframes == 1) { 3162 /* no STATUS stage yet, SETUP is last */ 3163 if (xfer->flags_int.control_act) 3164 temp.setup_alt_next = 0; 3165 } 3166 3167 dwc_otg_setup_standard_chain_sub(&temp); 3168 } 3169 x = 1; 3170 } else { 3171 x = 0; 3172 } 3173 3174 if (x != xfer->nframes) { 3175 if (xfer->endpointno & UE_DIR_IN) { 3176 if (is_host) { 3177 temp.func = &dwc_otg_host_data_rx; 3178 need_sync = 0; 3179 } else { 3180 temp.func = &dwc_otg_data_tx; 3181 need_sync = 1; 3182 } 3183 } else { 3184 if (is_host) { 3185 temp.func = &dwc_otg_host_data_tx; 3186 need_sync = 0; 3187 } else { 3188 temp.func = &dwc_otg_data_rx; 3189 need_sync = 0; 3190 } 3191 } 3192 3193 /* setup "pc" pointer */ 3194 temp.pc = xfer->frbuffers + x; 3195 } else { 3196 need_sync = 0; 3197 } 3198 while (x != xfer->nframes) { 3199 3200 /* DATA0 / DATA1 message */ 3201 3202 temp.len = xfer->frlengths[x]; 3203 3204 x++; 3205 3206 if (x == xfer->nframes) { 3207 if (xfer->flags_int.control_xfr) { 3208 if (xfer->flags_int.control_act) { 3209 temp.setup_alt_next = 0; 3210 } 3211 } else { 3212 temp.setup_alt_next = 0; 3213 } 3214 } 3215 if (temp.len == 0) { 3216 3217 /* make sure that we send an USB packet */ 3218 3219 temp.short_pkt = 0; 3220 3221 } else { 3222 3223 /* regular data transfer */ 3224 3225 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3226 } 3227 3228 dwc_otg_setup_standard_chain_sub(&temp); 3229 3230 if (xfer->flags_int.isochronous_xfr) { 3231 temp.offset += temp.len; 3232 } else { 3233 /* get next Page Cache pointer */ 3234 temp.pc = xfer->frbuffers + x; 3235 } 3236 } 3237 3238 if (xfer->flags_int.control_xfr) { 3239 3240 /* always setup a valid "pc" pointer for status and sync */ 3241 temp.pc = xfer->frbuffers + 0; 3242 temp.len = 0; 3243 temp.short_pkt = 0; 3244 temp.setup_alt_next = 0; 3245 3246 /* check if we need to sync */ 3247 if (need_sync) { 3248 /* we need a SYNC point after TX */ 3249 temp.func = &dwc_otg_data_tx_sync; 3250 dwc_otg_setup_standard_chain_sub(&temp); 3251 } 3252 3253 /* check if we should append a status stage */ 3254 if (!xfer->flags_int.control_act) { 3255 3256 /* 3257 * Send a DATA1 message and invert the current 3258 * endpoint direction. 3259 */ 3260 if (xfer->endpointno & UE_DIR_IN) { 3261 if (is_host) { 3262 temp.func = &dwc_otg_host_data_tx; 3263 need_sync = 0; 3264 } else { 3265 temp.func = &dwc_otg_data_rx; 3266 need_sync = 0; 3267 } 3268 } else { 3269 if (is_host) { 3270 temp.func = &dwc_otg_host_data_rx; 3271 need_sync = 0; 3272 } else { 3273 temp.func = &dwc_otg_data_tx; 3274 need_sync = 1; 3275 } 3276 } 3277 3278 dwc_otg_setup_standard_chain_sub(&temp); 3279 3280 /* data toggle should be DATA1 */ 3281 td = temp.td; 3282 td->set_toggle = 1; 3283 3284 if (need_sync) { 3285 /* we need a SYNC point after TX */ 3286 temp.func = &dwc_otg_data_tx_sync; 3287 dwc_otg_setup_standard_chain_sub(&temp); 3288 } 3289 } 3290 } else { 3291 /* check if we need to sync */ 3292 if (need_sync) { 3293 3294 temp.pc = xfer->frbuffers + 0; 3295 temp.len = 0; 3296 temp.short_pkt = 0; 3297 temp.setup_alt_next = 0; 3298 3299 /* we need a SYNC point after TX */ 3300 temp.func = &dwc_otg_data_tx_sync; 3301 dwc_otg_setup_standard_chain_sub(&temp); 3302 } 3303 } 3304 3305 /* must have at least one frame! */ 3306 td = temp.td; 3307 xfer->td_transfer_last = td; 3308 3309 if (is_host) { 3310 3311 struct dwc_otg_softc *sc; 3312 uint32_t hcchar; 3313 uint32_t hcsplt; 3314 3315 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3316 3317 /* get first again */ 3318 td = xfer->td_transfer_first; 3319 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3320 3321 hcchar = 3322 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3323 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3324 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3325 HCCHAR_CHENA; 3326 3327 /* 3328 * We are not always able to meet the timing 3329 * requirements of the USB interrupt endpoint's 3330 * complete split token, when doing transfers going 3331 * via a transaction translator. Use the CONTROL 3332 * transfer type instead of the INTERRUPT transfer 3333 * type in general, as a means to workaround 3334 * that. This trick should work for both FULL and LOW 3335 * speed USB traffic going through a TT. For non-TT 3336 * traffic it works as well. The reason for using 3337 * CONTROL type instead of BULK is that some TTs might 3338 * reject LOW speed BULK traffic. 3339 */ 3340 if (td->ep_type == UE_INTERRUPT) 3341 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); 3342 else 3343 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3344 3345 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3346 hcchar |= HCCHAR_EPDIR_IN; 3347 3348 switch (xfer->xroot->udev->speed) { 3349 case USB_SPEED_LOW: 3350 hcchar |= HCCHAR_LSPDDEV; 3351 /* FALLTHROUGH */ 3352 case USB_SPEED_FULL: 3353 /* check if root HUB port is running High Speed */ 3354 if (dwc_otg_uses_split(xfer->xroot->udev)) { 3355 hcsplt = HCSPLT_SPLTENA | 3356 (xfer->xroot->udev->hs_port_no << 3357 HCSPLT_PRTADDR_SHIFT) | 3358 (xfer->xroot->udev->hs_hub_addr << 3359 HCSPLT_HUBADDR_SHIFT); 3360 } else { 3361 hcsplt = 0; 3362 } 3363 if (td->ep_type == UE_INTERRUPT) { 3364 uint32_t ival; 3365 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3366 if (ival == 0) 3367 ival = 1; 3368 else if (ival > 127) 3369 ival = 127; 3370 td->tmr_val = sc->sc_tmr_val + ival; 3371 td->tmr_res = ival; 3372 } else if (td->ep_type == UE_ISOCHRONOUS) { 3373 td->tmr_res = 1; 3374 td->tmr_val = sc->sc_last_frame_num; 3375 if (td->hcchar & HCCHAR_EPDIR_IN) 3376 td->tmr_val++; 3377 } else { 3378 td->tmr_val = 0; 3379 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3380 } 3381 break; 3382 case USB_SPEED_HIGH: 3383 hcsplt = 0; 3384 if (td->ep_type == UE_INTERRUPT) { 3385 uint32_t ival; 3386 hcchar |= ((xfer->max_packet_count & 3) 3387 << HCCHAR_MC_SHIFT); 3388 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3389 if (ival == 0) 3390 ival = 1; 3391 else if (ival > 127) 3392 ival = 127; 3393 td->tmr_val = sc->sc_tmr_val + ival; 3394 td->tmr_res = ival; 3395 } else if (td->ep_type == UE_ISOCHRONOUS) { 3396 hcchar |= ((xfer->max_packet_count & 3) 3397 << HCCHAR_MC_SHIFT); 3398 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3399 td->tmr_val = sc->sc_last_frame_num; 3400 if (td->hcchar & HCCHAR_EPDIR_IN) 3401 td->tmr_val += td->tmr_res; 3402 3403 } else { 3404 td->tmr_val = 0; 3405 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3406 } 3407 break; 3408 default: 3409 hcsplt = 0; 3410 td->tmr_val = 0; 3411 td->tmr_res = 0; 3412 break; 3413 } 3414 3415 /* store configuration in all TD's */ 3416 while (1) { 3417 td->hcchar = hcchar; 3418 td->hcsplt = hcsplt; 3419 3420 if (((void *)td) == xfer->td_transfer_last) 3421 break; 3422 3423 td = td->obj_next; 3424 } 3425 } 3426 } 3427 3428 static void 3429 dwc_otg_timeout(void *arg) 3430 { 3431 struct usb_xfer *xfer = arg; 3432 3433 DPRINTF("xfer=%p\n", xfer); 3434 3435 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3436 3437 /* transfer is transferred */ 3438 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3439 } 3440 3441 static void 3442 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3443 { 3444 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3445 3446 DPRINTFN(9, "\n"); 3447 3448 /* 3449 * Poll one time in device mode, which will turn on the 3450 * endpoint interrupts. Else wait for SOF interrupt in host 3451 * mode. 3452 */ 3453 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3454 3455 if (sc->sc_flags.status_device_mode != 0) { 3456 dwc_otg_xfer_do_fifo(sc, xfer); 3457 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3458 goto done; 3459 } else { 3460 struct dwc_otg_td *td = xfer->td_transfer_cache; 3461 if (td->ep_type == UE_ISOCHRONOUS && 3462 (td->hcchar & HCCHAR_EPDIR_IN) == 0) { 3463 /* 3464 * Need to start ISOCHRONOUS OUT transfer ASAP 3465 * because execution is delayed by one 125us 3466 * microframe: 3467 */ 3468 dwc_otg_xfer_do_fifo(sc, xfer); 3469 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3470 goto done; 3471 } 3472 } 3473 3474 /* put transfer on interrupt queue */ 3475 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3476 3477 /* start timeout, if any */ 3478 if (xfer->timeout != 0) { 3479 usbd_transfer_timeout_ms(xfer, 3480 &dwc_otg_timeout, xfer->timeout); 3481 } 3482 3483 if (sc->sc_flags.status_device_mode != 0) 3484 goto done; 3485 3486 /* enable SOF interrupt, if any */ 3487 dwc_otg_enable_sof_irq(sc); 3488 done: 3489 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3490 } 3491 3492 static void 3493 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3494 { 3495 DPRINTFN(9, "\n"); 3496 3497 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3498 3499 /* set port bit */ 3500 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3501 3502 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3503 sizeof(sc->sc_hub_idata)); 3504 } 3505 3506 static usb_error_t 3507 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3508 { 3509 struct dwc_otg_td *td; 3510 uint32_t len; 3511 usb_error_t error; 3512 3513 DPRINTFN(9, "\n"); 3514 3515 td = xfer->td_transfer_cache; 3516 3517 do { 3518 len = td->remainder; 3519 3520 /* store last data toggle */ 3521 xfer->endpoint->toggle_next = td->toggle; 3522 3523 if (xfer->aframes != xfer->nframes) { 3524 /* 3525 * Verify the length and subtract 3526 * the remainder from "frlengths[]": 3527 */ 3528 if (len > xfer->frlengths[xfer->aframes]) { 3529 td->error_any = 1; 3530 } else { 3531 xfer->frlengths[xfer->aframes] -= len; 3532 } 3533 } 3534 /* Check for transfer error */ 3535 if (td->error_any) { 3536 /* the transfer is finished */ 3537 error = (td->error_stall ? 3538 USB_ERR_STALLED : USB_ERR_IOERROR); 3539 td = NULL; 3540 break; 3541 } 3542 /* Check for short transfer */ 3543 if (len > 0) { 3544 if (xfer->flags_int.short_frames_ok || 3545 xfer->flags_int.isochronous_xfr) { 3546 /* follow alt next */ 3547 if (td->alt_next) { 3548 td = td->obj_next; 3549 } else { 3550 td = NULL; 3551 } 3552 } else { 3553 /* the transfer is finished */ 3554 td = NULL; 3555 } 3556 error = 0; 3557 break; 3558 } 3559 td = td->obj_next; 3560 3561 /* this USB frame is complete */ 3562 error = 0; 3563 break; 3564 3565 } while (0); 3566 3567 /* update transfer cache */ 3568 3569 xfer->td_transfer_cache = td; 3570 3571 return (error); 3572 } 3573 3574 static void 3575 dwc_otg_standard_done(struct usb_xfer *xfer) 3576 { 3577 usb_error_t err = 0; 3578 3579 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3580 xfer, xfer->endpoint); 3581 3582 /* reset scanner */ 3583 3584 xfer->td_transfer_cache = xfer->td_transfer_first; 3585 3586 if (xfer->flags_int.control_xfr) { 3587 3588 if (xfer->flags_int.control_hdr) { 3589 3590 err = dwc_otg_standard_done_sub(xfer); 3591 } 3592 xfer->aframes = 1; 3593 3594 if (xfer->td_transfer_cache == NULL) { 3595 goto done; 3596 } 3597 } 3598 while (xfer->aframes != xfer->nframes) { 3599 3600 err = dwc_otg_standard_done_sub(xfer); 3601 xfer->aframes++; 3602 3603 if (xfer->td_transfer_cache == NULL) { 3604 goto done; 3605 } 3606 } 3607 3608 if (xfer->flags_int.control_xfr && 3609 !xfer->flags_int.control_act) { 3610 3611 err = dwc_otg_standard_done_sub(xfer); 3612 } 3613 done: 3614 dwc_otg_device_done(xfer, err); 3615 } 3616 3617 /*------------------------------------------------------------------------* 3618 * dwc_otg_device_done 3619 * 3620 * NOTE: this function can be called more than one time on the 3621 * same USB transfer! 3622 *------------------------------------------------------------------------*/ 3623 static void 3624 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3625 { 3626 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3627 3628 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3629 xfer, xfer->endpoint, error); 3630 3631 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3632 3633 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3634 /* Interrupts are cleared by the interrupt handler */ 3635 } else { 3636 struct dwc_otg_td *td; 3637 3638 td = xfer->td_transfer_cache; 3639 if (td != NULL) 3640 dwc_otg_host_channel_free(sc, td); 3641 } 3642 /* dequeue transfer and start next transfer */ 3643 usbd_transfer_done(xfer, error); 3644 3645 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3646 } 3647 3648 static void 3649 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3650 { 3651 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3652 } 3653 3654 static void 3655 dwc_otg_set_stall(struct usb_device *udev, 3656 struct usb_endpoint *ep, uint8_t *did_stall) 3657 { 3658 struct dwc_otg_softc *sc; 3659 uint32_t temp; 3660 uint32_t reg; 3661 uint8_t ep_no; 3662 3663 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3664 3665 /* check mode */ 3666 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3667 /* not supported */ 3668 return; 3669 } 3670 3671 sc = DWC_OTG_BUS2SC(udev->bus); 3672 3673 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3674 3675 /* get endpoint address */ 3676 ep_no = ep->edesc->bEndpointAddress; 3677 3678 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3679 3680 if (ep_no & UE_DIR_IN) { 3681 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3682 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3683 } else { 3684 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3685 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3686 } 3687 3688 /* disable and stall endpoint */ 3689 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3690 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3691 3692 /* clear active OUT ep */ 3693 if (!(ep_no & UE_DIR_IN)) { 3694 3695 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3696 3697 if (sc->sc_last_rx_status != 0 && 3698 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3699 sc->sc_last_rx_status)) { 3700 /* dump data */ 3701 dwc_otg_common_rx_ack(sc); 3702 /* poll interrupt */ 3703 dwc_otg_interrupt_poll_locked(sc); 3704 dwc_otg_interrupt_complete_locked(sc); 3705 } 3706 } 3707 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3708 } 3709 3710 static void 3711 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3712 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3713 { 3714 uint32_t reg; 3715 uint32_t temp; 3716 3717 if (ep_type == UE_CONTROL) { 3718 /* clearing stall is not needed */ 3719 return; 3720 } 3721 3722 if (ep_dir) { 3723 reg = DOTG_DIEPCTL(ep_no); 3724 } else { 3725 reg = DOTG_DOEPCTL(ep_no); 3726 sc->sc_active_rx_ep |= (1U << ep_no); 3727 } 3728 3729 /* round up and mask away the multiplier count */ 3730 mps = (mps + 3) & 0x7FC; 3731 3732 if (ep_type == UE_BULK) { 3733 temp = DIEPCTL_EPTYPE_SET( 3734 DIEPCTL_EPTYPE_BULK) | 3735 DIEPCTL_USBACTEP; 3736 } else if (ep_type == UE_INTERRUPT) { 3737 temp = DIEPCTL_EPTYPE_SET( 3738 DIEPCTL_EPTYPE_INTERRUPT) | 3739 DIEPCTL_USBACTEP; 3740 } else { 3741 temp = DIEPCTL_EPTYPE_SET( 3742 DIEPCTL_EPTYPE_ISOC) | 3743 DIEPCTL_USBACTEP; 3744 } 3745 3746 temp |= DIEPCTL_MPS_SET(mps); 3747 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3748 3749 if (ep_dir) 3750 sc->sc_in_ctl[ep_no] = temp; 3751 else 3752 sc->sc_out_ctl[ep_no] = temp; 3753 3754 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3755 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3756 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3757 3758 /* we only reset the transmit FIFO */ 3759 if (ep_dir) { 3760 dwc_otg_tx_fifo_reset(sc, 3761 GRSTCTL_TXFIFO(ep_no) | 3762 GRSTCTL_TXFFLSH); 3763 3764 DWC_OTG_WRITE_4(sc, 3765 DOTG_DIEPTSIZ(ep_no), 0); 3766 } 3767 3768 /* poll interrupt */ 3769 dwc_otg_interrupt_poll_locked(sc); 3770 dwc_otg_interrupt_complete_locked(sc); 3771 } 3772 3773 static void 3774 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3775 { 3776 struct dwc_otg_softc *sc; 3777 struct usb_endpoint_descriptor *ed; 3778 3779 DPRINTFN(5, "endpoint=%p\n", ep); 3780 3781 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3782 3783 /* check mode */ 3784 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3785 /* not supported */ 3786 return; 3787 } 3788 /* get softc */ 3789 sc = DWC_OTG_BUS2SC(udev->bus); 3790 3791 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3792 3793 /* get endpoint descriptor */ 3794 ed = ep->edesc; 3795 3796 /* reset endpoint */ 3797 dwc_otg_clear_stall_sub_locked(sc, 3798 UGETW(ed->wMaxPacketSize), 3799 (ed->bEndpointAddress & UE_ADDR), 3800 (ed->bmAttributes & UE_XFERTYPE), 3801 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3802 3803 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3804 } 3805 3806 static void 3807 dwc_otg_device_state_change(struct usb_device *udev) 3808 { 3809 struct dwc_otg_softc *sc; 3810 uint8_t x; 3811 3812 /* check mode */ 3813 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3814 /* not supported */ 3815 return; 3816 } 3817 3818 /* get softc */ 3819 sc = DWC_OTG_BUS2SC(udev->bus); 3820 3821 /* deactivate all other endpoint but the control endpoint */ 3822 if (udev->state == USB_STATE_CONFIGURED || 3823 udev->state == USB_STATE_ADDRESSED) { 3824 3825 USB_BUS_LOCK(&sc->sc_bus); 3826 3827 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3828 3829 if (x < sc->sc_dev_in_ep_max) { 3830 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3831 DIEPCTL_EPDIS); 3832 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3833 } 3834 3835 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3836 DOEPCTL_EPDIS); 3837 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3838 } 3839 USB_BUS_UNLOCK(&sc->sc_bus); 3840 } 3841 } 3842 3843 int 3844 dwc_otg_init(struct dwc_otg_softc *sc) 3845 { 3846 uint32_t temp; 3847 3848 DPRINTF("start\n"); 3849 3850 /* set up the bus structure */ 3851 sc->sc_bus.usbrev = USB_REV_2_0; 3852 sc->sc_bus.methods = &dwc_otg_bus_methods; 3853 3854 usb_callout_init_mtx(&sc->sc_timer, 3855 &sc->sc_bus.bus_mtx, 0); 3856 3857 USB_BUS_LOCK(&sc->sc_bus); 3858 3859 /* turn on clocks */ 3860 dwc_otg_clocks_on(sc); 3861 3862 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3863 DPRINTF("Version = 0x%08x\n", temp); 3864 3865 /* disconnect */ 3866 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3867 DCTL_SFTDISCON); 3868 3869 /* wait for host to detect disconnect */ 3870 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3871 3872 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3873 GRSTCTL_CSFTRST); 3874 3875 /* wait a little bit for block to reset */ 3876 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3877 3878 switch (sc->sc_mode) { 3879 case DWC_MODE_DEVICE: 3880 temp = GUSBCFG_FORCEDEVMODE; 3881 break; 3882 case DWC_MODE_HOST: 3883 temp = GUSBCFG_FORCEHOSTMODE; 3884 break; 3885 default: 3886 temp = 0; 3887 break; 3888 } 3889 3890 /* select HSIC, ULPI or internal PHY mode */ 3891 switch (dwc_otg_phy_type) { 3892 case DWC_OTG_PHY_HSIC: 3893 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3894 GUSBCFG_PHYIF | 3895 GUSBCFG_TRD_TIM_SET(5) | temp); 3896 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3897 0x000000EC); 3898 3899 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3900 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3901 temp & ~GLPMCFG_HSIC_CONN); 3902 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3903 temp | GLPMCFG_HSIC_CONN); 3904 break; 3905 case DWC_OTG_PHY_ULPI: 3906 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3907 GUSBCFG_ULPI_UTMI_SEL | 3908 GUSBCFG_TRD_TIM_SET(5) | temp); 3909 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3910 3911 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3912 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3913 temp & ~GLPMCFG_HSIC_CONN); 3914 break; 3915 case DWC_OTG_PHY_INTERNAL: 3916 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3917 GUSBCFG_PHYSEL | 3918 GUSBCFG_TRD_TIM_SET(5) | temp); 3919 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3920 3921 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3922 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3923 temp & ~GLPMCFG_HSIC_CONN); 3924 3925 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO); 3926 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN); 3927 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN | 3928 DOTG_GGPIO_PWRDWN); 3929 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp); 3930 break; 3931 default: 3932 break; 3933 } 3934 3935 /* clear global nak */ 3936 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3937 DCTL_CGOUTNAK | 3938 DCTL_CGNPINNAK); 3939 3940 /* disable USB port */ 3941 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3942 3943 /* wait 10ms */ 3944 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3945 3946 /* enable USB port */ 3947 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3948 3949 /* wait 10ms */ 3950 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3951 3952 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3953 3954 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3955 3956 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3957 3958 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3959 3960 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3961 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3962 3963 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3964 3965 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3966 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3967 3968 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3969 3970 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3971 3972 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3973 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3974 sc->sc_host_ch_max); 3975 3976 /* setup FIFO */ 3977 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 3978 USB_BUS_UNLOCK(&sc->sc_bus); 3979 return (EINVAL); 3980 } 3981 3982 /* enable interrupts */ 3983 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3984 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3985 3986 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3987 3988 /* enable all endpoint interrupts */ 3989 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3990 if (temp & GHWCFG2_MPI) { 3991 uint8_t x; 3992 3993 DPRINTF("Disable Multi Process Interrupts\n"); 3994 3995 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3996 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0); 3997 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3998 } 3999 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0); 4000 } 4001 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 4002 DIEPMSK_XFERCOMPLMSK); 4003 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 4004 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 4005 } 4006 4007 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 4008 /* setup clocks */ 4009 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 4010 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 4011 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 4012 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 4013 } 4014 4015 /* only enable global IRQ */ 4016 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 4017 GAHBCFG_GLBLINTRMSK); 4018 4019 /* turn off clocks */ 4020 dwc_otg_clocks_off(sc); 4021 4022 /* read initial VBUS state */ 4023 4024 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 4025 4026 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 4027 4028 dwc_otg_vbus_interrupt(sc, 4029 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 4030 4031 USB_BUS_UNLOCK(&sc->sc_bus); 4032 4033 /* catch any lost interrupts */ 4034 4035 dwc_otg_do_poll(&sc->sc_bus); 4036 4037 return (0); /* success */ 4038 } 4039 4040 void 4041 dwc_otg_uninit(struct dwc_otg_softc *sc) 4042 { 4043 USB_BUS_LOCK(&sc->sc_bus); 4044 4045 /* stop host timer */ 4046 dwc_otg_timer_stop(sc); 4047 4048 /* set disconnect */ 4049 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 4050 DCTL_SFTDISCON); 4051 4052 /* turn off global IRQ */ 4053 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 4054 4055 sc->sc_flags.port_enabled = 0; 4056 sc->sc_flags.port_powered = 0; 4057 sc->sc_flags.status_vbus = 0; 4058 sc->sc_flags.status_bus_reset = 0; 4059 sc->sc_flags.status_suspend = 0; 4060 sc->sc_flags.change_suspend = 0; 4061 sc->sc_flags.change_connect = 1; 4062 4063 dwc_otg_pull_down(sc); 4064 dwc_otg_clocks_off(sc); 4065 4066 USB_BUS_UNLOCK(&sc->sc_bus); 4067 4068 usb_callout_drain(&sc->sc_timer); 4069 } 4070 4071 static void 4072 dwc_otg_suspend(struct dwc_otg_softc *sc) 4073 { 4074 return; 4075 } 4076 4077 static void 4078 dwc_otg_resume(struct dwc_otg_softc *sc) 4079 { 4080 return; 4081 } 4082 4083 static void 4084 dwc_otg_do_poll(struct usb_bus *bus) 4085 { 4086 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4087 4088 USB_BUS_LOCK(&sc->sc_bus); 4089 USB_BUS_SPIN_LOCK(&sc->sc_bus); 4090 dwc_otg_interrupt_poll_locked(sc); 4091 dwc_otg_interrupt_complete_locked(sc); 4092 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 4093 USB_BUS_UNLOCK(&sc->sc_bus); 4094 } 4095 4096 /*------------------------------------------------------------------------* 4097 * DWC OTG bulk support 4098 * DWC OTG control support 4099 * DWC OTG interrupt support 4100 *------------------------------------------------------------------------*/ 4101 static void 4102 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 4103 { 4104 } 4105 4106 static void 4107 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 4108 { 4109 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4110 } 4111 4112 static void 4113 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 4114 { 4115 } 4116 4117 static void 4118 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 4119 { 4120 /* setup TDs */ 4121 dwc_otg_setup_standard_chain(xfer); 4122 dwc_otg_start_standard_chain(xfer); 4123 } 4124 4125 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 4126 { 4127 .open = dwc_otg_device_non_isoc_open, 4128 .close = dwc_otg_device_non_isoc_close, 4129 .enter = dwc_otg_device_non_isoc_enter, 4130 .start = dwc_otg_device_non_isoc_start, 4131 }; 4132 4133 /*------------------------------------------------------------------------* 4134 * DWC OTG full speed isochronous support 4135 *------------------------------------------------------------------------*/ 4136 static void 4137 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4138 { 4139 } 4140 4141 static void 4142 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4143 { 4144 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4145 } 4146 4147 static void 4148 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4149 { 4150 } 4151 4152 static void 4153 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4154 { 4155 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4156 uint32_t temp; 4157 uint32_t msframes; 4158 uint32_t framenum; 4159 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4160 4161 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4162 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4163 4164 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4165 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4166 4167 /* get the current frame index */ 4168 framenum = (temp & HFNUM_FRNUM_MASK); 4169 } else { 4170 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4171 4172 /* get the current frame index */ 4173 framenum = DSTS_SOFFN_GET(temp); 4174 } 4175 4176 /* 4177 * Check if port is doing 8000 or 1000 frames per second: 4178 */ 4179 if (sc->sc_flags.status_high_speed) 4180 framenum /= 8; 4181 4182 framenum &= DWC_OTG_FRAME_MASK; 4183 4184 /* 4185 * Compute number of milliseconds worth of data traffic for 4186 * this USB transfer: 4187 */ 4188 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4189 msframes = ((xfer->nframes << shift) + 7) / 8; 4190 else 4191 msframes = xfer->nframes; 4192 4193 /* 4194 * check if the frame index is within the window where the frames 4195 * will be inserted 4196 */ 4197 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4198 4199 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4200 /* 4201 * If there is data underflow or the pipe queue is 4202 * empty we schedule the transfer a few frames ahead 4203 * of the current frame position. Else two isochronous 4204 * transfers might overlap. 4205 */ 4206 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4207 xfer->endpoint->is_synced = 1; 4208 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4209 } 4210 /* 4211 * compute how many milliseconds the insertion is ahead of the 4212 * current frame position: 4213 */ 4214 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4215 4216 /* 4217 * pre-compute when the isochronous transfer will be finished: 4218 */ 4219 xfer->isoc_time_complete = 4220 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4221 4222 /* setup TDs */ 4223 dwc_otg_setup_standard_chain(xfer); 4224 4225 /* compute frame number for next insertion */ 4226 xfer->endpoint->isoc_next += msframes; 4227 4228 /* start TD chain */ 4229 dwc_otg_start_standard_chain(xfer); 4230 } 4231 4232 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4233 { 4234 .open = dwc_otg_device_isoc_open, 4235 .close = dwc_otg_device_isoc_close, 4236 .enter = dwc_otg_device_isoc_enter, 4237 .start = dwc_otg_device_isoc_start, 4238 }; 4239 4240 /*------------------------------------------------------------------------* 4241 * DWC OTG root control support 4242 *------------------------------------------------------------------------* 4243 * Simulate a hardware HUB by handling all the necessary requests. 4244 *------------------------------------------------------------------------*/ 4245 4246 static const struct usb_device_descriptor dwc_otg_devd = { 4247 .bLength = sizeof(struct usb_device_descriptor), 4248 .bDescriptorType = UDESC_DEVICE, 4249 .bcdUSB = {0x00, 0x02}, 4250 .bDeviceClass = UDCLASS_HUB, 4251 .bDeviceSubClass = UDSUBCLASS_HUB, 4252 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4253 .bMaxPacketSize = 64, 4254 .bcdDevice = {0x00, 0x01}, 4255 .iManufacturer = 1, 4256 .iProduct = 2, 4257 .bNumConfigurations = 1, 4258 }; 4259 4260 static const struct dwc_otg_config_desc dwc_otg_confd = { 4261 .confd = { 4262 .bLength = sizeof(struct usb_config_descriptor), 4263 .bDescriptorType = UDESC_CONFIG, 4264 .wTotalLength[0] = sizeof(dwc_otg_confd), 4265 .bNumInterface = 1, 4266 .bConfigurationValue = 1, 4267 .iConfiguration = 0, 4268 .bmAttributes = UC_SELF_POWERED, 4269 .bMaxPower = 0, 4270 }, 4271 .ifcd = { 4272 .bLength = sizeof(struct usb_interface_descriptor), 4273 .bDescriptorType = UDESC_INTERFACE, 4274 .bNumEndpoints = 1, 4275 .bInterfaceClass = UICLASS_HUB, 4276 .bInterfaceSubClass = UISUBCLASS_HUB, 4277 .bInterfaceProtocol = 0, 4278 }, 4279 .endpd = { 4280 .bLength = sizeof(struct usb_endpoint_descriptor), 4281 .bDescriptorType = UDESC_ENDPOINT, 4282 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4283 .bmAttributes = UE_INTERRUPT, 4284 .wMaxPacketSize[0] = 8, 4285 .bInterval = 255, 4286 }, 4287 }; 4288 4289 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4290 4291 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4292 .bDescLength = sizeof(dwc_otg_hubd), 4293 .bDescriptorType = UDESC_HUB, 4294 .bNbrPorts = 1, 4295 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4296 .bPwrOn2PwrGood = 50, 4297 .bHubContrCurrent = 0, 4298 .DeviceRemovable = {0}, /* port is removable */ 4299 }; 4300 4301 #define STRING_VENDOR \ 4302 "D\0W\0C\0O\0T\0G" 4303 4304 #define STRING_PRODUCT \ 4305 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4306 4307 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4308 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4309 4310 static usb_error_t 4311 dwc_otg_roothub_exec(struct usb_device *udev, 4312 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4313 { 4314 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4315 const void *ptr; 4316 uint16_t len; 4317 uint16_t value; 4318 uint16_t index; 4319 usb_error_t err; 4320 4321 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4322 4323 /* buffer reset */ 4324 ptr = (const void *)&sc->sc_hub_temp; 4325 len = 0; 4326 err = 0; 4327 4328 value = UGETW(req->wValue); 4329 index = UGETW(req->wIndex); 4330 4331 /* demultiplex the control request */ 4332 4333 switch (req->bmRequestType) { 4334 case UT_READ_DEVICE: 4335 switch (req->bRequest) { 4336 case UR_GET_DESCRIPTOR: 4337 goto tr_handle_get_descriptor; 4338 case UR_GET_CONFIG: 4339 goto tr_handle_get_config; 4340 case UR_GET_STATUS: 4341 goto tr_handle_get_status; 4342 default: 4343 goto tr_stalled; 4344 } 4345 break; 4346 4347 case UT_WRITE_DEVICE: 4348 switch (req->bRequest) { 4349 case UR_SET_ADDRESS: 4350 goto tr_handle_set_address; 4351 case UR_SET_CONFIG: 4352 goto tr_handle_set_config; 4353 case UR_CLEAR_FEATURE: 4354 goto tr_valid; /* nop */ 4355 case UR_SET_DESCRIPTOR: 4356 goto tr_valid; /* nop */ 4357 case UR_SET_FEATURE: 4358 default: 4359 goto tr_stalled; 4360 } 4361 break; 4362 4363 case UT_WRITE_ENDPOINT: 4364 switch (req->bRequest) { 4365 case UR_CLEAR_FEATURE: 4366 switch (UGETW(req->wValue)) { 4367 case UF_ENDPOINT_HALT: 4368 goto tr_handle_clear_halt; 4369 case UF_DEVICE_REMOTE_WAKEUP: 4370 goto tr_handle_clear_wakeup; 4371 default: 4372 goto tr_stalled; 4373 } 4374 break; 4375 case UR_SET_FEATURE: 4376 switch (UGETW(req->wValue)) { 4377 case UF_ENDPOINT_HALT: 4378 goto tr_handle_set_halt; 4379 case UF_DEVICE_REMOTE_WAKEUP: 4380 goto tr_handle_set_wakeup; 4381 default: 4382 goto tr_stalled; 4383 } 4384 break; 4385 case UR_SYNCH_FRAME: 4386 goto tr_valid; /* nop */ 4387 default: 4388 goto tr_stalled; 4389 } 4390 break; 4391 4392 case UT_READ_ENDPOINT: 4393 switch (req->bRequest) { 4394 case UR_GET_STATUS: 4395 goto tr_handle_get_ep_status; 4396 default: 4397 goto tr_stalled; 4398 } 4399 break; 4400 4401 case UT_WRITE_INTERFACE: 4402 switch (req->bRequest) { 4403 case UR_SET_INTERFACE: 4404 goto tr_handle_set_interface; 4405 case UR_CLEAR_FEATURE: 4406 goto tr_valid; /* nop */ 4407 case UR_SET_FEATURE: 4408 default: 4409 goto tr_stalled; 4410 } 4411 break; 4412 4413 case UT_READ_INTERFACE: 4414 switch (req->bRequest) { 4415 case UR_GET_INTERFACE: 4416 goto tr_handle_get_interface; 4417 case UR_GET_STATUS: 4418 goto tr_handle_get_iface_status; 4419 default: 4420 goto tr_stalled; 4421 } 4422 break; 4423 4424 case UT_WRITE_CLASS_INTERFACE: 4425 case UT_WRITE_VENDOR_INTERFACE: 4426 /* XXX forward */ 4427 break; 4428 4429 case UT_READ_CLASS_INTERFACE: 4430 case UT_READ_VENDOR_INTERFACE: 4431 /* XXX forward */ 4432 break; 4433 4434 case UT_WRITE_CLASS_DEVICE: 4435 switch (req->bRequest) { 4436 case UR_CLEAR_FEATURE: 4437 goto tr_valid; 4438 case UR_SET_DESCRIPTOR: 4439 case UR_SET_FEATURE: 4440 break; 4441 default: 4442 goto tr_stalled; 4443 } 4444 break; 4445 4446 case UT_WRITE_CLASS_OTHER: 4447 switch (req->bRequest) { 4448 case UR_CLEAR_FEATURE: 4449 goto tr_handle_clear_port_feature; 4450 case UR_SET_FEATURE: 4451 goto tr_handle_set_port_feature; 4452 case UR_CLEAR_TT_BUFFER: 4453 case UR_RESET_TT: 4454 case UR_STOP_TT: 4455 goto tr_valid; 4456 4457 default: 4458 goto tr_stalled; 4459 } 4460 break; 4461 4462 case UT_READ_CLASS_OTHER: 4463 switch (req->bRequest) { 4464 case UR_GET_TT_STATE: 4465 goto tr_handle_get_tt_state; 4466 case UR_GET_STATUS: 4467 goto tr_handle_get_port_status; 4468 default: 4469 goto tr_stalled; 4470 } 4471 break; 4472 4473 case UT_READ_CLASS_DEVICE: 4474 switch (req->bRequest) { 4475 case UR_GET_DESCRIPTOR: 4476 goto tr_handle_get_class_descriptor; 4477 case UR_GET_STATUS: 4478 goto tr_handle_get_class_status; 4479 4480 default: 4481 goto tr_stalled; 4482 } 4483 break; 4484 default: 4485 goto tr_stalled; 4486 } 4487 goto tr_valid; 4488 4489 tr_handle_get_descriptor: 4490 switch (value >> 8) { 4491 case UDESC_DEVICE: 4492 if (value & 0xff) { 4493 goto tr_stalled; 4494 } 4495 len = sizeof(dwc_otg_devd); 4496 ptr = (const void *)&dwc_otg_devd; 4497 goto tr_valid; 4498 case UDESC_CONFIG: 4499 if (value & 0xff) { 4500 goto tr_stalled; 4501 } 4502 len = sizeof(dwc_otg_confd); 4503 ptr = (const void *)&dwc_otg_confd; 4504 goto tr_valid; 4505 case UDESC_STRING: 4506 switch (value & 0xff) { 4507 case 0: /* Language table */ 4508 len = sizeof(usb_string_lang_en); 4509 ptr = (const void *)&usb_string_lang_en; 4510 goto tr_valid; 4511 4512 case 1: /* Vendor */ 4513 len = sizeof(dwc_otg_vendor); 4514 ptr = (const void *)&dwc_otg_vendor; 4515 goto tr_valid; 4516 4517 case 2: /* Product */ 4518 len = sizeof(dwc_otg_product); 4519 ptr = (const void *)&dwc_otg_product; 4520 goto tr_valid; 4521 default: 4522 break; 4523 } 4524 break; 4525 default: 4526 goto tr_stalled; 4527 } 4528 goto tr_stalled; 4529 4530 tr_handle_get_config: 4531 len = 1; 4532 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4533 goto tr_valid; 4534 4535 tr_handle_get_status: 4536 len = 2; 4537 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4538 goto tr_valid; 4539 4540 tr_handle_set_address: 4541 if (value & 0xFF00) { 4542 goto tr_stalled; 4543 } 4544 sc->sc_rt_addr = value; 4545 goto tr_valid; 4546 4547 tr_handle_set_config: 4548 if (value >= 2) { 4549 goto tr_stalled; 4550 } 4551 sc->sc_conf = value; 4552 goto tr_valid; 4553 4554 tr_handle_get_interface: 4555 len = 1; 4556 sc->sc_hub_temp.wValue[0] = 0; 4557 goto tr_valid; 4558 4559 tr_handle_get_tt_state: 4560 tr_handle_get_class_status: 4561 tr_handle_get_iface_status: 4562 tr_handle_get_ep_status: 4563 len = 2; 4564 USETW(sc->sc_hub_temp.wValue, 0); 4565 goto tr_valid; 4566 4567 tr_handle_set_halt: 4568 tr_handle_set_interface: 4569 tr_handle_set_wakeup: 4570 tr_handle_clear_wakeup: 4571 tr_handle_clear_halt: 4572 goto tr_valid; 4573 4574 tr_handle_clear_port_feature: 4575 if (index != 1) 4576 goto tr_stalled; 4577 4578 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4579 4580 switch (value) { 4581 case UHF_PORT_SUSPEND: 4582 dwc_otg_wakeup_peer(sc); 4583 break; 4584 4585 case UHF_PORT_ENABLE: 4586 if (sc->sc_flags.status_device_mode == 0) { 4587 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4588 sc->sc_hprt_val | HPRT_PRTENA); 4589 } 4590 sc->sc_flags.port_enabled = 0; 4591 break; 4592 4593 case UHF_C_PORT_RESET: 4594 sc->sc_flags.change_reset = 0; 4595 break; 4596 4597 case UHF_C_PORT_ENABLE: 4598 sc->sc_flags.change_enabled = 0; 4599 break; 4600 4601 case UHF_C_PORT_OVER_CURRENT: 4602 sc->sc_flags.change_over_current = 0; 4603 break; 4604 4605 case UHF_PORT_TEST: 4606 case UHF_PORT_INDICATOR: 4607 /* nops */ 4608 break; 4609 4610 case UHF_PORT_POWER: 4611 sc->sc_flags.port_powered = 0; 4612 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4613 sc->sc_hprt_val = 0; 4614 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4615 } 4616 dwc_otg_pull_down(sc); 4617 dwc_otg_clocks_off(sc); 4618 break; 4619 4620 case UHF_C_PORT_CONNECTION: 4621 /* clear connect change flag */ 4622 sc->sc_flags.change_connect = 0; 4623 break; 4624 4625 case UHF_C_PORT_SUSPEND: 4626 sc->sc_flags.change_suspend = 0; 4627 break; 4628 4629 default: 4630 err = USB_ERR_IOERROR; 4631 goto done; 4632 } 4633 goto tr_valid; 4634 4635 tr_handle_set_port_feature: 4636 if (index != 1) { 4637 goto tr_stalled; 4638 } 4639 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4640 4641 switch (value) { 4642 case UHF_PORT_ENABLE: 4643 break; 4644 4645 case UHF_PORT_SUSPEND: 4646 if (sc->sc_flags.status_device_mode == 0) { 4647 /* set suspend BIT */ 4648 sc->sc_hprt_val |= HPRT_PRTSUSP; 4649 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4650 4651 /* generate HUB suspend event */ 4652 dwc_otg_suspend_irq(sc); 4653 } 4654 break; 4655 4656 case UHF_PORT_RESET: 4657 if (sc->sc_flags.status_device_mode == 0) { 4658 4659 DPRINTF("PORT RESET\n"); 4660 4661 /* enable PORT reset */ 4662 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4663 4664 /* Wait 62.5ms for reset to complete */ 4665 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4666 4667 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4668 4669 /* Wait 62.5ms for reset to complete */ 4670 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4671 4672 /* reset FIFOs */ 4673 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4674 4675 sc->sc_flags.change_reset = 1; 4676 } else { 4677 err = USB_ERR_IOERROR; 4678 } 4679 break; 4680 4681 case UHF_PORT_TEST: 4682 case UHF_PORT_INDICATOR: 4683 /* nops */ 4684 break; 4685 case UHF_PORT_POWER: 4686 sc->sc_flags.port_powered = 1; 4687 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4688 sc->sc_hprt_val |= HPRT_PRTPWR; 4689 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4690 } 4691 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) { 4692 /* pull up D+, if any */ 4693 dwc_otg_pull_up(sc); 4694 } 4695 break; 4696 default: 4697 err = USB_ERR_IOERROR; 4698 goto done; 4699 } 4700 goto tr_valid; 4701 4702 tr_handle_get_port_status: 4703 4704 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4705 4706 if (index != 1) 4707 goto tr_stalled; 4708 4709 if (sc->sc_flags.status_vbus) 4710 dwc_otg_clocks_on(sc); 4711 else 4712 dwc_otg_clocks_off(sc); 4713 4714 /* Select Device Side Mode */ 4715 4716 if (sc->sc_flags.status_device_mode) { 4717 value = UPS_PORT_MODE_DEVICE; 4718 dwc_otg_timer_stop(sc); 4719 } else { 4720 value = 0; 4721 dwc_otg_timer_start(sc); 4722 } 4723 4724 if (sc->sc_flags.status_high_speed) 4725 value |= UPS_HIGH_SPEED; 4726 else if (sc->sc_flags.status_low_speed) 4727 value |= UPS_LOW_SPEED; 4728 4729 if (sc->sc_flags.port_powered) 4730 value |= UPS_PORT_POWER; 4731 4732 if (sc->sc_flags.port_enabled) 4733 value |= UPS_PORT_ENABLED; 4734 4735 if (sc->sc_flags.port_over_current) 4736 value |= UPS_OVERCURRENT_INDICATOR; 4737 4738 if (sc->sc_flags.status_vbus && 4739 sc->sc_flags.status_bus_reset) 4740 value |= UPS_CURRENT_CONNECT_STATUS; 4741 4742 if (sc->sc_flags.status_suspend) 4743 value |= UPS_SUSPEND; 4744 4745 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4746 4747 value = 0; 4748 4749 if (sc->sc_flags.change_enabled) 4750 value |= UPS_C_PORT_ENABLED; 4751 if (sc->sc_flags.change_connect) 4752 value |= UPS_C_CONNECT_STATUS; 4753 if (sc->sc_flags.change_suspend) 4754 value |= UPS_C_SUSPEND; 4755 if (sc->sc_flags.change_reset) 4756 value |= UPS_C_PORT_RESET; 4757 if (sc->sc_flags.change_over_current) 4758 value |= UPS_C_OVERCURRENT_INDICATOR; 4759 4760 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4761 len = sizeof(sc->sc_hub_temp.ps); 4762 goto tr_valid; 4763 4764 tr_handle_get_class_descriptor: 4765 if (value & 0xFF) { 4766 goto tr_stalled; 4767 } 4768 ptr = (const void *)&dwc_otg_hubd; 4769 len = sizeof(dwc_otg_hubd); 4770 goto tr_valid; 4771 4772 tr_stalled: 4773 err = USB_ERR_STALLED; 4774 tr_valid: 4775 done: 4776 *plength = len; 4777 *pptr = ptr; 4778 return (err); 4779 } 4780 4781 static void 4782 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4783 { 4784 struct usb_xfer *xfer; 4785 void *last_obj; 4786 uint32_t ntd; 4787 uint32_t n; 4788 uint8_t ep_no; 4789 uint8_t ep_type; 4790 4791 xfer = parm->curr_xfer; 4792 4793 /* 4794 * NOTE: This driver does not use any of the parameters that 4795 * are computed from the following values. Just set some 4796 * reasonable dummies: 4797 */ 4798 parm->hc_max_packet_size = 0x500; 4799 parm->hc_max_packet_count = 3; 4800 parm->hc_max_frame_size = 3 * 0x500; 4801 4802 usbd_transfer_setup_sub(parm); 4803 4804 /* 4805 * compute maximum number of TDs 4806 */ 4807 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4808 4809 if (ep_type == UE_CONTROL) { 4810 4811 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4812 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4813 } else { 4814 4815 ntd = xfer->nframes + 1 /* SYNC */ ; 4816 } 4817 4818 /* 4819 * check if "usbd_transfer_setup_sub" set an error 4820 */ 4821 if (parm->err) 4822 return; 4823 4824 /* 4825 * allocate transfer descriptors 4826 */ 4827 last_obj = NULL; 4828 4829 ep_no = xfer->endpointno & UE_ADDR; 4830 4831 /* 4832 * Check for a valid endpoint profile in USB device mode: 4833 */ 4834 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4835 const struct usb_hw_ep_profile *pf; 4836 4837 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4838 4839 if (pf == NULL) { 4840 /* should not happen */ 4841 parm->err = USB_ERR_INVAL; 4842 return; 4843 } 4844 } 4845 4846 /* align data */ 4847 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4848 4849 for (n = 0; n != ntd; n++) { 4850 4851 struct dwc_otg_td *td; 4852 4853 if (parm->buf) { 4854 4855 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4856 4857 /* compute shared bandwidth resource index for TT */ 4858 if (dwc_otg_uses_split(parm->udev)) { 4859 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4860 td->tt_index = parm->udev->device_index; 4861 else 4862 td->tt_index = parm->udev->parent_hs_hub->device_index; 4863 } else { 4864 td->tt_index = parm->udev->device_index; 4865 } 4866 4867 /* init TD */ 4868 td->max_packet_size = xfer->max_packet_size; 4869 td->max_packet_count = xfer->max_packet_count; 4870 /* range check */ 4871 if (td->max_packet_count == 0 || td->max_packet_count > 3) 4872 td->max_packet_count = 1; 4873 td->ep_no = ep_no; 4874 td->ep_type = ep_type; 4875 td->obj_next = last_obj; 4876 4877 last_obj = td; 4878 } 4879 parm->size[0] += sizeof(*td); 4880 } 4881 4882 xfer->td_start[0] = last_obj; 4883 } 4884 4885 static void 4886 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4887 { 4888 return; 4889 } 4890 4891 static void 4892 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4893 struct usb_endpoint *ep) 4894 { 4895 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4896 4897 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4898 ep, udev->address, 4899 edesc->bEndpointAddress, udev->flags.usb_mode, 4900 sc->sc_rt_addr, udev->device_index); 4901 4902 if (udev->device_index != sc->sc_rt_addr) { 4903 4904 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4905 if (udev->speed != USB_SPEED_FULL && 4906 udev->speed != USB_SPEED_HIGH) { 4907 /* not supported */ 4908 return; 4909 } 4910 } else { 4911 if (udev->speed == USB_SPEED_HIGH && 4912 (edesc->wMaxPacketSize[1] & 0x18) != 0 && 4913 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) { 4914 /* not supported */ 4915 DPRINTFN(-1, "Non-isochronous high bandwidth " 4916 "endpoint not supported\n"); 4917 return; 4918 } 4919 } 4920 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4921 ep->methods = &dwc_otg_device_isoc_methods; 4922 else 4923 ep->methods = &dwc_otg_device_non_isoc_methods; 4924 } 4925 } 4926 4927 static void 4928 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4929 { 4930 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4931 4932 switch (state) { 4933 case USB_HW_POWER_SUSPEND: 4934 dwc_otg_suspend(sc); 4935 break; 4936 case USB_HW_POWER_SHUTDOWN: 4937 dwc_otg_uninit(sc); 4938 break; 4939 case USB_HW_POWER_RESUME: 4940 dwc_otg_resume(sc); 4941 break; 4942 default: 4943 break; 4944 } 4945 } 4946 4947 static void 4948 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4949 { 4950 /* DMA delay - wait until any use of memory is finished */ 4951 *pus = (2125); /* microseconds */ 4952 } 4953 4954 static void 4955 dwc_otg_device_resume(struct usb_device *udev) 4956 { 4957 DPRINTF("\n"); 4958 4959 /* poll all transfers again to restart resumed ones */ 4960 dwc_otg_do_poll(udev->bus); 4961 } 4962 4963 static void 4964 dwc_otg_device_suspend(struct usb_device *udev) 4965 { 4966 DPRINTF("\n"); 4967 } 4968 4969 static const struct usb_bus_methods dwc_otg_bus_methods = 4970 { 4971 .endpoint_init = &dwc_otg_ep_init, 4972 .xfer_setup = &dwc_otg_xfer_setup, 4973 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4974 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4975 .xfer_stall = &dwc_otg_xfer_stall, 4976 .set_stall = &dwc_otg_set_stall, 4977 .clear_stall = &dwc_otg_clear_stall, 4978 .roothub_exec = &dwc_otg_roothub_exec, 4979 .xfer_poll = &dwc_otg_do_poll, 4980 .device_state_change = &dwc_otg_device_state_change, 4981 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4982 .get_dma_delay = &dwc_otg_get_dma_delay, 4983 .device_resume = &dwc_otg_device_resume, 4984 .device_suspend = &dwc_otg_device_suspend, 4985 }; 4986