1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the AVR32 series USB Device 31 * Controller 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 #ifdef USB_GLOBAL_INCLUDE_FILE 39 #include USB_GLOBAL_INCLUDE_FILE 40 #else 41 #include <sys/stdint.h> 42 #include <sys/stddef.h> 43 #include <sys/param.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/module.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/sysctl.h> 54 #include <sys/sx.h> 55 #include <sys/unistd.h> 56 #include <sys/callout.h> 57 #include <sys/malloc.h> 58 #include <sys/priv.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 63 #define USB_DEBUG_VAR avr32dci_debug 64 65 #include <dev/usb/usb_core.h> 66 #include <dev/usb/usb_debug.h> 67 #include <dev/usb/usb_busdma.h> 68 #include <dev/usb/usb_process.h> 69 #include <dev/usb/usb_transfer.h> 70 #include <dev/usb/usb_device.h> 71 #include <dev/usb/usb_hub.h> 72 #include <dev/usb/usb_util.h> 73 74 #include <dev/usb/usb_controller.h> 75 #include <dev/usb/usb_bus.h> 76 #endif /* USB_GLOBAL_INCLUDE_FILE */ 77 78 #include <dev/usb/controller/avr32dci.h> 79 80 #define AVR32_BUS2SC(bus) \ 81 __containerof(bus, struct avr32dci_softc, sc_bus) 82 83 #define AVR32_PC2SC(pc) \ 84 AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 85 86 #ifdef USB_DEBUG 87 static int avr32dci_debug = 0; 88 89 static SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, 90 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 91 "USB AVR32 DCI"); 92 SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RWTUN, 93 &avr32dci_debug, 0, "AVR32 DCI debug level"); 94 #endif 95 96 #define AVR32_INTR_ENDPT 1 97 98 /* prototypes */ 99 100 static const struct usb_bus_methods avr32dci_bus_methods; 101 static const struct usb_pipe_methods avr32dci_device_non_isoc_methods; 102 static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods; 103 104 static avr32dci_cmd_t avr32dci_setup_rx; 105 static avr32dci_cmd_t avr32dci_data_rx; 106 static avr32dci_cmd_t avr32dci_data_tx; 107 static avr32dci_cmd_t avr32dci_data_tx_sync; 108 static void avr32dci_device_done(struct usb_xfer *, usb_error_t); 109 static void avr32dci_do_poll(struct usb_bus *); 110 static void avr32dci_standard_done(struct usb_xfer *); 111 static void avr32dci_root_intr(struct avr32dci_softc *sc); 112 113 /* 114 * Here is a list of what the chip supports: 115 */ 116 static const struct usb_hw_ep_profile 117 avr32dci_ep_profile[4] = { 118 [0] = { 119 .max_in_frame_size = 64, 120 .max_out_frame_size = 64, 121 .is_simplex = 1, 122 .support_control = 1, 123 }, 124 125 [1] = { 126 .max_in_frame_size = 512, 127 .max_out_frame_size = 512, 128 .is_simplex = 1, 129 .support_bulk = 1, 130 .support_interrupt = 1, 131 .support_isochronous = 1, 132 .support_in = 1, 133 .support_out = 1, 134 }, 135 136 [2] = { 137 .max_in_frame_size = 64, 138 .max_out_frame_size = 64, 139 .is_simplex = 1, 140 .support_bulk = 1, 141 .support_interrupt = 1, 142 .support_in = 1, 143 .support_out = 1, 144 }, 145 146 [3] = { 147 .max_in_frame_size = 1024, 148 .max_out_frame_size = 1024, 149 .is_simplex = 1, 150 .support_bulk = 1, 151 .support_interrupt = 1, 152 .support_isochronous = 1, 153 .support_in = 1, 154 .support_out = 1, 155 }, 156 }; 157 158 static void 159 avr32dci_get_hw_ep_profile(struct usb_device *udev, 160 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 161 { 162 if (ep_addr == 0) 163 *ppf = avr32dci_ep_profile; 164 else if (ep_addr < 3) 165 *ppf = avr32dci_ep_profile + 1; 166 else if (ep_addr < 5) 167 *ppf = avr32dci_ep_profile + 2; 168 else if (ep_addr < 7) 169 *ppf = avr32dci_ep_profile + 3; 170 else 171 *ppf = NULL; 172 } 173 174 static void 175 avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 176 { 177 uint32_t temp; 178 179 temp = AVR32_READ_4(sc, AVR32_CTRL); 180 temp |= set; 181 temp &= ~clear; 182 AVR32_WRITE_4(sc, AVR32_CTRL, temp); 183 } 184 185 static void 186 avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 187 { 188 uint32_t temp; 189 190 temp = AVR32_READ_4(sc, AVR32_IEN); 191 temp |= set; 192 temp &= ~clear; 193 AVR32_WRITE_4(sc, AVR32_IEN, temp); 194 } 195 196 static void 197 avr32dci_clocks_on(struct avr32dci_softc *sc) 198 { 199 if (sc->sc_flags.clocks_off && 200 sc->sc_flags.port_powered) { 201 DPRINTFN(5, "\n"); 202 203 /* turn on clocks */ 204 (sc->sc_clocks_on) (&sc->sc_bus); 205 206 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 207 208 sc->sc_flags.clocks_off = 0; 209 } 210 } 211 212 static void 213 avr32dci_clocks_off(struct avr32dci_softc *sc) 214 { 215 if (!sc->sc_flags.clocks_off) { 216 DPRINTFN(5, "\n"); 217 218 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA); 219 220 /* turn clocks off */ 221 (sc->sc_clocks_off) (&sc->sc_bus); 222 223 sc->sc_flags.clocks_off = 1; 224 } 225 } 226 227 static void 228 avr32dci_pull_up(struct avr32dci_softc *sc) 229 { 230 /* pullup D+, if possible */ 231 232 if (!sc->sc_flags.d_pulled_up && 233 sc->sc_flags.port_powered) { 234 sc->sc_flags.d_pulled_up = 1; 235 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH); 236 } 237 } 238 239 static void 240 avr32dci_pull_down(struct avr32dci_softc *sc) 241 { 242 /* pulldown D+, if possible */ 243 244 if (sc->sc_flags.d_pulled_up) { 245 sc->sc_flags.d_pulled_up = 0; 246 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 247 } 248 } 249 250 static void 251 avr32dci_wakeup_peer(struct avr32dci_softc *sc) 252 { 253 if (!sc->sc_flags.status_suspend) { 254 return; 255 } 256 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0); 257 258 /* wait 8 milliseconds */ 259 /* Wait for reset to complete. */ 260 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 261 262 /* hardware should have cleared RMWKUP bit */ 263 } 264 265 static void 266 avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr) 267 { 268 DPRINTFN(5, "addr=%d\n", addr); 269 270 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_FADDR_EN | addr, 0); 271 } 272 273 static uint8_t 274 avr32dci_setup_rx(struct avr32dci_td *td) 275 { 276 struct avr32dci_softc *sc; 277 struct usb_device_request req; 278 uint16_t count; 279 uint32_t temp; 280 281 /* get pointer to softc */ 282 sc = AVR32_PC2SC(td->pc); 283 284 /* check endpoint status */ 285 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 286 287 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 288 289 if (!(temp & AVR32_EPTSTA_RX_SETUP)) { 290 goto not_complete; 291 } 292 /* clear did stall */ 293 td->did_stall = 0; 294 /* get the packet byte count */ 295 count = AVR32_EPTSTA_BYTE_COUNT(temp); 296 297 /* verify data length */ 298 if (count != td->remainder) { 299 DPRINTFN(0, "Invalid SETUP packet " 300 "length, %d bytes\n", count); 301 goto not_complete; 302 } 303 if (count != sizeof(req)) { 304 DPRINTFN(0, "Unsupported SETUP packet " 305 "length, %d bytes\n", count); 306 goto not_complete; 307 } 308 /* receive data */ 309 memcpy(&req, sc->physdata, sizeof(req)); 310 311 /* copy data into real buffer */ 312 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 313 314 td->offset = sizeof(req); 315 td->remainder = 0; 316 317 /* sneak peek the set address */ 318 if ((req.bmRequestType == UT_WRITE_DEVICE) && 319 (req.bRequest == UR_SET_ADDRESS)) { 320 sc->sc_dv_addr = req.wValue[0] & 0x7F; 321 /* must write address before ZLP */ 322 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN | 323 AVR32_CTRL_DEV_ADDR); 324 avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0); 325 } else { 326 sc->sc_dv_addr = 0xFF; 327 } 328 329 /* clear SETUP packet interrupt */ 330 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 331 return (0); /* complete */ 332 333 not_complete: 334 if (temp & AVR32_EPTSTA_RX_SETUP) { 335 /* clear SETUP packet interrupt */ 336 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 337 } 338 /* abort any ongoing transfer */ 339 if (!td->did_stall) { 340 DPRINTFN(5, "stalling\n"); 341 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no), 342 AVR32_EPTSTA_FRCESTALL); 343 td->did_stall = 1; 344 } 345 return (1); /* not complete */ 346 } 347 348 static uint8_t 349 avr32dci_data_rx(struct avr32dci_td *td) 350 { 351 struct avr32dci_softc *sc; 352 struct usb_page_search buf_res; 353 uint16_t count; 354 uint32_t temp; 355 uint8_t to; 356 uint8_t got_short; 357 358 to = 4; /* don't loop forever! */ 359 got_short = 0; 360 361 /* get pointer to softc */ 362 sc = AVR32_PC2SC(td->pc); 363 364 repeat: 365 /* check if any of the FIFO banks have data */ 366 /* check endpoint status */ 367 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 368 369 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 370 371 if (temp & AVR32_EPTSTA_RX_SETUP) { 372 if (td->remainder == 0) { 373 /* 374 * We are actually complete and have 375 * received the next SETUP 376 */ 377 DPRINTFN(5, "faking complete\n"); 378 return (0); /* complete */ 379 } 380 /* 381 * USB Host Aborted the transfer. 382 */ 383 td->error = 1; 384 return (0); /* complete */ 385 } 386 /* check status */ 387 if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) { 388 /* no data */ 389 goto not_complete; 390 } 391 /* get the packet byte count */ 392 count = AVR32_EPTSTA_BYTE_COUNT(temp); 393 394 /* verify the packet byte count */ 395 if (count != td->max_packet_size) { 396 if (count < td->max_packet_size) { 397 /* we have a short packet */ 398 td->short_pkt = 1; 399 got_short = 1; 400 } else { 401 /* invalid USB packet */ 402 td->error = 1; 403 return (0); /* we are complete */ 404 } 405 } 406 /* verify the packet byte count */ 407 if (count > td->remainder) { 408 /* invalid USB packet */ 409 td->error = 1; 410 return (0); /* we are complete */ 411 } 412 while (count > 0) { 413 usbd_get_page(td->pc, td->offset, &buf_res); 414 415 /* get correct length */ 416 if (buf_res.length > count) { 417 buf_res.length = count; 418 } 419 /* receive data */ 420 memcpy(buf_res.buffer, sc->physdata + 421 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 422 (td->ep_no << 16) + (td->offset % td->max_packet_size), buf_res.length); 423 /* update counters */ 424 count -= buf_res.length; 425 td->offset += buf_res.length; 426 td->remainder -= buf_res.length; 427 } 428 429 /* clear OUT packet interrupt */ 430 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY); 431 432 /* check if we are complete */ 433 if ((td->remainder == 0) || got_short) { 434 if (td->short_pkt) { 435 /* we are complete */ 436 return (0); 437 } 438 /* else need to receive a zero length packet */ 439 } 440 if (--to) { 441 goto repeat; 442 } 443 not_complete: 444 return (1); /* not complete */ 445 } 446 447 static uint8_t 448 avr32dci_data_tx(struct avr32dci_td *td) 449 { 450 struct avr32dci_softc *sc; 451 struct usb_page_search buf_res; 452 uint16_t count; 453 uint8_t to; 454 uint32_t temp; 455 456 to = 4; /* don't loop forever! */ 457 458 /* get pointer to softc */ 459 sc = AVR32_PC2SC(td->pc); 460 461 repeat: 462 463 /* check endpoint status */ 464 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 465 466 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 467 468 if (temp & AVR32_EPTSTA_RX_SETUP) { 469 /* 470 * The current transfer was aborted 471 * by the USB Host 472 */ 473 td->error = 1; 474 return (0); /* complete */ 475 } 476 if (temp & AVR32_EPTSTA_TX_PK_RDY) { 477 /* cannot write any data - all banks are busy */ 478 goto not_complete; 479 } 480 count = td->max_packet_size; 481 if (td->remainder < count) { 482 /* we have a short packet */ 483 td->short_pkt = 1; 484 count = td->remainder; 485 } 486 while (count > 0) { 487 usbd_get_page(td->pc, td->offset, &buf_res); 488 489 /* get correct length */ 490 if (buf_res.length > count) { 491 buf_res.length = count; 492 } 493 /* transmit data */ 494 memcpy(sc->physdata + 495 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 496 (td->ep_no << 16) + (td->offset % td->max_packet_size), 497 buf_res.buffer, buf_res.length); 498 /* update counters */ 499 count -= buf_res.length; 500 td->offset += buf_res.length; 501 td->remainder -= buf_res.length; 502 } 503 504 /* allocate FIFO bank */ 505 AVR32_WRITE_4(sc, AVR32_EPTCTL(td->ep_no), AVR32_EPTCTL_TX_PK_RDY); 506 507 /* check remainder */ 508 if (td->remainder == 0) { 509 if (td->short_pkt) { 510 return (0); /* complete */ 511 } 512 /* else we need to transmit a short packet */ 513 } 514 if (--to) { 515 goto repeat; 516 } 517 not_complete: 518 return (1); /* not complete */ 519 } 520 521 static uint8_t 522 avr32dci_data_tx_sync(struct avr32dci_td *td) 523 { 524 struct avr32dci_softc *sc; 525 uint32_t temp; 526 527 /* get pointer to softc */ 528 sc = AVR32_PC2SC(td->pc); 529 530 /* check endpoint status */ 531 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 532 533 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 534 535 if (temp & AVR32_EPTSTA_RX_SETUP) { 536 DPRINTFN(5, "faking complete\n"); 537 /* Race condition */ 538 return (0); /* complete */ 539 } 540 /* 541 * The control endpoint has only got one bank, so if that bank 542 * is free the packet has been transferred! 543 */ 544 if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) { 545 /* cannot write any data - a bank is busy */ 546 goto not_complete; 547 } 548 if (sc->sc_dv_addr != 0xFF) { 549 /* set new address */ 550 avr32dci_set_address(sc, sc->sc_dv_addr); 551 } 552 return (0); /* complete */ 553 554 not_complete: 555 return (1); /* not complete */ 556 } 557 558 static uint8_t 559 avr32dci_xfer_do_fifo(struct usb_xfer *xfer) 560 { 561 struct avr32dci_td *td; 562 563 DPRINTFN(9, "\n"); 564 565 td = xfer->td_transfer_cache; 566 while (1) { 567 if ((td->func) (td)) { 568 /* operation in progress */ 569 break; 570 } 571 if (((void *)td) == xfer->td_transfer_last) { 572 goto done; 573 } 574 if (td->error) { 575 goto done; 576 } else if (td->remainder > 0) { 577 /* 578 * We had a short transfer. If there is no alternate 579 * next, stop processing ! 580 */ 581 if (!td->alt_next) { 582 goto done; 583 } 584 } 585 /* 586 * Fetch the next transfer descriptor and transfer 587 * some flags to the next transfer descriptor 588 */ 589 td = td->obj_next; 590 xfer->td_transfer_cache = td; 591 } 592 return (1); /* not complete */ 593 594 done: 595 /* compute all actual lengths */ 596 597 avr32dci_standard_done(xfer); 598 return (0); /* complete */ 599 } 600 601 static void 602 avr32dci_interrupt_poll(struct avr32dci_softc *sc) 603 { 604 struct usb_xfer *xfer; 605 606 repeat: 607 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 608 if (!avr32dci_xfer_do_fifo(xfer)) { 609 /* queue has been modified */ 610 goto repeat; 611 } 612 } 613 } 614 615 void 616 avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on) 617 { 618 DPRINTFN(5, "vbus = %u\n", is_on); 619 620 if (is_on) { 621 if (!sc->sc_flags.status_vbus) { 622 sc->sc_flags.status_vbus = 1; 623 624 /* complete root HUB interrupt endpoint */ 625 626 avr32dci_root_intr(sc); 627 } 628 } else { 629 if (sc->sc_flags.status_vbus) { 630 sc->sc_flags.status_vbus = 0; 631 sc->sc_flags.status_bus_reset = 0; 632 sc->sc_flags.status_suspend = 0; 633 sc->sc_flags.change_suspend = 0; 634 sc->sc_flags.change_connect = 1; 635 636 /* complete root HUB interrupt endpoint */ 637 638 avr32dci_root_intr(sc); 639 } 640 } 641 } 642 643 void 644 avr32dci_interrupt(struct avr32dci_softc *sc) 645 { 646 uint32_t status; 647 648 USB_BUS_LOCK(&sc->sc_bus); 649 650 /* read interrupt status */ 651 status = AVR32_READ_4(sc, AVR32_INTSTA); 652 653 /* clear all set interrupts */ 654 AVR32_WRITE_4(sc, AVR32_CLRINT, status); 655 656 DPRINTFN(14, "INTSTA=0x%08x\n", status); 657 658 /* check for any bus state change interrupts */ 659 if (status & AVR32_INT_ENDRESET) { 660 DPRINTFN(5, "end of reset\n"); 661 662 /* set correct state */ 663 sc->sc_flags.status_bus_reset = 1; 664 sc->sc_flags.status_suspend = 0; 665 sc->sc_flags.change_suspend = 0; 666 sc->sc_flags.change_connect = 1; 667 668 /* disable resume interrupt */ 669 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 670 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 671 672 /* complete root HUB interrupt endpoint */ 673 avr32dci_root_intr(sc); 674 } 675 /* 676 * If resume and suspend is set at the same time we interpret 677 * that like RESUME. Resume is set when there is at least 3 678 * milliseconds of inactivity on the USB BUS. 679 */ 680 if (status & AVR32_INT_WAKE_UP) { 681 DPRINTFN(5, "resume interrupt\n"); 682 683 if (sc->sc_flags.status_suspend) { 684 /* update status bits */ 685 sc->sc_flags.status_suspend = 0; 686 sc->sc_flags.change_suspend = 1; 687 688 /* disable resume interrupt */ 689 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 690 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 691 692 /* complete root HUB interrupt endpoint */ 693 avr32dci_root_intr(sc); 694 } 695 } else if (status & AVR32_INT_DET_SUSPD) { 696 DPRINTFN(5, "suspend interrupt\n"); 697 698 if (!sc->sc_flags.status_suspend) { 699 /* update status bits */ 700 sc->sc_flags.status_suspend = 1; 701 sc->sc_flags.change_suspend = 1; 702 703 /* disable suspend interrupt */ 704 avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP | 705 AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD); 706 707 /* complete root HUB interrupt endpoint */ 708 avr32dci_root_intr(sc); 709 } 710 } 711 /* check for any endpoint interrupts */ 712 if (status & -AVR32_INT_EPT_INT(0)) { 713 DPRINTFN(5, "real endpoint interrupt\n"); 714 715 avr32dci_interrupt_poll(sc); 716 } 717 USB_BUS_UNLOCK(&sc->sc_bus); 718 } 719 720 static void 721 avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp) 722 { 723 struct avr32dci_td *td; 724 725 /* get current Transfer Descriptor */ 726 td = temp->td_next; 727 temp->td = td; 728 729 /* prepare for next TD */ 730 temp->td_next = td->obj_next; 731 732 /* fill out the Transfer Descriptor */ 733 td->func = temp->func; 734 td->pc = temp->pc; 735 td->offset = temp->offset; 736 td->remainder = temp->len; 737 td->error = 0; 738 td->did_stall = temp->did_stall; 739 td->short_pkt = temp->short_pkt; 740 td->alt_next = temp->setup_alt_next; 741 } 742 743 static void 744 avr32dci_setup_standard_chain(struct usb_xfer *xfer) 745 { 746 struct avr32dci_std_temp temp; 747 struct avr32dci_softc *sc; 748 struct avr32dci_td *td; 749 uint32_t x; 750 uint8_t ep_no; 751 uint8_t need_sync; 752 753 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 754 xfer->address, UE_GET_ADDR(xfer->endpointno), 755 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 756 757 temp.max_frame_size = xfer->max_frame_size; 758 759 td = xfer->td_start[0]; 760 xfer->td_transfer_first = td; 761 xfer->td_transfer_cache = td; 762 763 /* setup temp */ 764 765 temp.pc = NULL; 766 temp.td = NULL; 767 temp.td_next = xfer->td_start[0]; 768 temp.offset = 0; 769 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 770 xfer->flags_int.isochronous_xfr; 771 temp.did_stall = !xfer->flags_int.control_stall; 772 773 sc = AVR32_BUS2SC(xfer->xroot->bus); 774 ep_no = (xfer->endpointno & UE_ADDR); 775 776 /* check if we should prepend a setup message */ 777 778 if (xfer->flags_int.control_xfr) { 779 if (xfer->flags_int.control_hdr) { 780 temp.func = &avr32dci_setup_rx; 781 temp.len = xfer->frlengths[0]; 782 temp.pc = xfer->frbuffers + 0; 783 temp.short_pkt = temp.len ? 1 : 0; 784 /* check for last frame */ 785 if (xfer->nframes == 1) { 786 /* no STATUS stage yet, SETUP is last */ 787 if (xfer->flags_int.control_act) 788 temp.setup_alt_next = 0; 789 } 790 avr32dci_setup_standard_chain_sub(&temp); 791 } 792 x = 1; 793 } else { 794 x = 0; 795 } 796 797 if (x != xfer->nframes) { 798 if (xfer->endpointno & UE_DIR_IN) { 799 temp.func = &avr32dci_data_tx; 800 need_sync = 1; 801 } else { 802 temp.func = &avr32dci_data_rx; 803 need_sync = 0; 804 } 805 806 /* setup "pc" pointer */ 807 temp.pc = xfer->frbuffers + x; 808 } else { 809 need_sync = 0; 810 } 811 while (x != xfer->nframes) { 812 /* DATA0 / DATA1 message */ 813 814 temp.len = xfer->frlengths[x]; 815 816 x++; 817 818 if (x == xfer->nframes) { 819 if (xfer->flags_int.control_xfr) { 820 if (xfer->flags_int.control_act) { 821 temp.setup_alt_next = 0; 822 } 823 } else { 824 temp.setup_alt_next = 0; 825 } 826 } 827 if (temp.len == 0) { 828 /* make sure that we send an USB packet */ 829 830 temp.short_pkt = 0; 831 832 } else { 833 /* regular data transfer */ 834 835 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 836 } 837 838 avr32dci_setup_standard_chain_sub(&temp); 839 840 if (xfer->flags_int.isochronous_xfr) { 841 temp.offset += temp.len; 842 } else { 843 /* get next Page Cache pointer */ 844 temp.pc = xfer->frbuffers + x; 845 } 846 } 847 848 if (xfer->flags_int.control_xfr) { 849 /* always setup a valid "pc" pointer for status and sync */ 850 temp.pc = xfer->frbuffers + 0; 851 temp.len = 0; 852 temp.short_pkt = 0; 853 temp.setup_alt_next = 0; 854 855 /* check if we need to sync */ 856 if (need_sync) { 857 /* we need a SYNC point after TX */ 858 temp.func = &avr32dci_data_tx_sync; 859 avr32dci_setup_standard_chain_sub(&temp); 860 } 861 /* check if we should append a status stage */ 862 if (!xfer->flags_int.control_act) { 863 /* 864 * Send a DATA1 message and invert the current 865 * endpoint direction. 866 */ 867 if (xfer->endpointno & UE_DIR_IN) { 868 temp.func = &avr32dci_data_rx; 869 need_sync = 0; 870 } else { 871 temp.func = &avr32dci_data_tx; 872 need_sync = 1; 873 } 874 875 avr32dci_setup_standard_chain_sub(&temp); 876 if (need_sync) { 877 /* we need a SYNC point after TX */ 878 temp.func = &avr32dci_data_tx_sync; 879 avr32dci_setup_standard_chain_sub(&temp); 880 } 881 } 882 } 883 /* must have at least one frame! */ 884 td = temp.td; 885 xfer->td_transfer_last = td; 886 } 887 888 static void 889 avr32dci_timeout(void *arg) 890 { 891 struct usb_xfer *xfer = arg; 892 893 DPRINTF("xfer=%p\n", xfer); 894 895 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 896 897 /* transfer is transferred */ 898 avr32dci_device_done(xfer, USB_ERR_TIMEOUT); 899 } 900 901 static void 902 avr32dci_start_standard_chain(struct usb_xfer *xfer) 903 { 904 DPRINTFN(9, "\n"); 905 906 /* poll one time - will turn on interrupts */ 907 if (avr32dci_xfer_do_fifo(xfer)) { 908 uint8_t ep_no = xfer->endpointno & UE_ADDR; 909 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 910 911 avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0); 912 913 /* put transfer on interrupt queue */ 914 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 915 916 /* start timeout, if any */ 917 if (xfer->timeout != 0) { 918 usbd_transfer_timeout_ms(xfer, 919 &avr32dci_timeout, xfer->timeout); 920 } 921 } 922 } 923 924 static void 925 avr32dci_root_intr(struct avr32dci_softc *sc) 926 { 927 DPRINTFN(9, "\n"); 928 929 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 930 931 /* set port bit */ 932 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 933 934 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 935 sizeof(sc->sc_hub_idata)); 936 } 937 938 static usb_error_t 939 avr32dci_standard_done_sub(struct usb_xfer *xfer) 940 { 941 struct avr32dci_td *td; 942 uint32_t len; 943 uint8_t error; 944 945 DPRINTFN(9, "\n"); 946 947 td = xfer->td_transfer_cache; 948 949 do { 950 len = td->remainder; 951 952 if (xfer->aframes != xfer->nframes) { 953 /* 954 * Verify the length and subtract 955 * the remainder from "frlengths[]": 956 */ 957 if (len > xfer->frlengths[xfer->aframes]) { 958 td->error = 1; 959 } else { 960 xfer->frlengths[xfer->aframes] -= len; 961 } 962 } 963 /* Check for transfer error */ 964 if (td->error) { 965 /* the transfer is finished */ 966 error = 1; 967 td = NULL; 968 break; 969 } 970 /* Check for short transfer */ 971 if (len > 0) { 972 if (xfer->flags_int.short_frames_ok || 973 xfer->flags_int.isochronous_xfr) { 974 /* follow alt next */ 975 if (td->alt_next) { 976 td = td->obj_next; 977 } else { 978 td = NULL; 979 } 980 } else { 981 /* the transfer is finished */ 982 td = NULL; 983 } 984 error = 0; 985 break; 986 } 987 td = td->obj_next; 988 989 /* this USB frame is complete */ 990 error = 0; 991 break; 992 993 } while (0); 994 995 /* update transfer cache */ 996 997 xfer->td_transfer_cache = td; 998 999 return (error ? 1000 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1001 } 1002 1003 static void 1004 avr32dci_standard_done(struct usb_xfer *xfer) 1005 { 1006 usb_error_t err = 0; 1007 1008 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1009 xfer, xfer->endpoint); 1010 1011 /* reset scanner */ 1012 1013 xfer->td_transfer_cache = xfer->td_transfer_first; 1014 1015 if (xfer->flags_int.control_xfr) { 1016 if (xfer->flags_int.control_hdr) { 1017 err = avr32dci_standard_done_sub(xfer); 1018 } 1019 xfer->aframes = 1; 1020 1021 if (xfer->td_transfer_cache == NULL) { 1022 goto done; 1023 } 1024 } 1025 while (xfer->aframes != xfer->nframes) { 1026 err = avr32dci_standard_done_sub(xfer); 1027 xfer->aframes++; 1028 1029 if (xfer->td_transfer_cache == NULL) { 1030 goto done; 1031 } 1032 } 1033 1034 if (xfer->flags_int.control_xfr && 1035 !xfer->flags_int.control_act) { 1036 err = avr32dci_standard_done_sub(xfer); 1037 } 1038 done: 1039 avr32dci_device_done(xfer, err); 1040 } 1041 1042 /*------------------------------------------------------------------------* 1043 * avr32dci_device_done 1044 * 1045 * NOTE: this function can be called more than one time on the 1046 * same USB transfer! 1047 *------------------------------------------------------------------------*/ 1048 static void 1049 avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1050 { 1051 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1052 uint8_t ep_no; 1053 1054 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1055 1056 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n", 1057 xfer, xfer->endpoint, error); 1058 1059 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1060 ep_no = (xfer->endpointno & UE_ADDR); 1061 1062 /* disable endpoint interrupt */ 1063 avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no)); 1064 1065 DPRINTFN(15, "disabled interrupts!\n"); 1066 } 1067 /* dequeue transfer and start next transfer */ 1068 usbd_transfer_done(xfer, error); 1069 } 1070 1071 static void 1072 avr32dci_xfer_stall(struct usb_xfer *xfer) 1073 { 1074 avr32dci_device_done(xfer, USB_ERR_STALLED); 1075 } 1076 1077 static void 1078 avr32dci_set_stall(struct usb_device *udev, 1079 struct usb_endpoint *pipe, uint8_t *did_stall) 1080 { 1081 struct avr32dci_softc *sc; 1082 uint8_t ep_no; 1083 1084 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1085 1086 DPRINTFN(5, "pipe=%p\n", pipe); 1087 1088 sc = AVR32_BUS2SC(udev->bus); 1089 /* get endpoint number */ 1090 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1091 /* set stall */ 1092 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1093 } 1094 1095 static void 1096 avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no, 1097 uint8_t ep_type, uint8_t ep_dir) 1098 { 1099 const struct usb_hw_ep_profile *pf; 1100 uint32_t temp; 1101 uint32_t epsize; 1102 uint8_t n; 1103 1104 if (ep_type == UE_CONTROL) { 1105 /* clearing stall is not needed */ 1106 return; 1107 } 1108 /* set endpoint reset */ 1109 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no)); 1110 1111 /* set stall */ 1112 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1113 1114 /* reset data toggle */ 1115 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ); 1116 1117 /* clear stall */ 1118 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1119 1120 if (ep_type == UE_BULK) { 1121 temp = AVR32_EPTCFG_TYPE_BULK; 1122 } else if (ep_type == UE_INTERRUPT) { 1123 temp = AVR32_EPTCFG_TYPE_INTR; 1124 } else { 1125 temp = AVR32_EPTCFG_TYPE_ISOC | 1126 AVR32_EPTCFG_NB_TRANS(1); 1127 } 1128 if (ep_dir & UE_DIR_IN) { 1129 temp |= AVR32_EPTCFG_EPDIR_IN; 1130 } 1131 avr32dci_get_hw_ep_profile(NULL, &pf, ep_no); 1132 1133 /* compute endpoint size (use maximum) */ 1134 epsize = pf->max_in_frame_size | pf->max_out_frame_size; 1135 n = 0; 1136 while ((epsize /= 2)) 1137 n++; 1138 temp |= AVR32_EPTCFG_EPSIZE(n); 1139 1140 /* use the maximum number of banks supported */ 1141 if (ep_no < 1) 1142 temp |= AVR32_EPTCFG_NBANK(1); 1143 else if (ep_no < 3) 1144 temp |= AVR32_EPTCFG_NBANK(2); 1145 else 1146 temp |= AVR32_EPTCFG_NBANK(3); 1147 1148 AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp); 1149 1150 temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no)); 1151 1152 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1153 device_printf(sc->sc_bus.bdev, "Chip rejected configuration\n"); 1154 } else { 1155 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no), 1156 AVR32_EPTCTL_EPT_ENABL); 1157 } 1158 } 1159 1160 static void 1161 avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *pipe) 1162 { 1163 struct avr32dci_softc *sc; 1164 struct usb_endpoint_descriptor *ed; 1165 1166 DPRINTFN(5, "pipe=%p\n", pipe); 1167 1168 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1169 1170 /* check mode */ 1171 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1172 /* not supported */ 1173 return; 1174 } 1175 /* get softc */ 1176 sc = AVR32_BUS2SC(udev->bus); 1177 1178 /* get endpoint descriptor */ 1179 ed = pipe->edesc; 1180 1181 /* reset endpoint */ 1182 avr32dci_clear_stall_sub(sc, 1183 (ed->bEndpointAddress & UE_ADDR), 1184 (ed->bmAttributes & UE_XFERTYPE), 1185 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1186 } 1187 1188 usb_error_t 1189 avr32dci_init(struct avr32dci_softc *sc) 1190 { 1191 uint8_t n; 1192 1193 DPRINTF("start\n"); 1194 1195 /* set up the bus structure */ 1196 sc->sc_bus.usbrev = USB_REV_1_1; 1197 sc->sc_bus.methods = &avr32dci_bus_methods; 1198 1199 USB_BUS_LOCK(&sc->sc_bus); 1200 1201 /* make sure USB is enabled */ 1202 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 1203 1204 /* turn on clocks */ 1205 (sc->sc_clocks_on) (&sc->sc_bus); 1206 1207 /* make sure device is re-enumerated */ 1208 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 1209 1210 /* wait a little for things to stabilise */ 1211 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1212 1213 /* disable interrupts */ 1214 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1215 1216 /* enable interrupts */ 1217 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 1218 AVR32_INT_ENDRESET, 0); 1219 1220 /* reset all endpoints */ 1221 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); 1222 1223 /* disable all endpoints */ 1224 for (n = 0; n != AVR32_EP_MAX; n++) { 1225 /* disable endpoint */ 1226 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1227 } 1228 1229 /* turn off clocks */ 1230 1231 avr32dci_clocks_off(sc); 1232 1233 USB_BUS_UNLOCK(&sc->sc_bus); 1234 1235 /* catch any lost interrupts */ 1236 1237 avr32dci_do_poll(&sc->sc_bus); 1238 1239 return (0); /* success */ 1240 } 1241 1242 void 1243 avr32dci_uninit(struct avr32dci_softc *sc) 1244 { 1245 uint8_t n; 1246 1247 USB_BUS_LOCK(&sc->sc_bus); 1248 1249 /* turn on clocks */ 1250 (sc->sc_clocks_on) (&sc->sc_bus); 1251 1252 /* disable interrupts */ 1253 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1254 1255 /* reset all endpoints */ 1256 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); 1257 1258 /* disable all endpoints */ 1259 for (n = 0; n != AVR32_EP_MAX; n++) { 1260 /* disable endpoint */ 1261 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1262 } 1263 1264 sc->sc_flags.port_powered = 0; 1265 sc->sc_flags.status_vbus = 0; 1266 sc->sc_flags.status_bus_reset = 0; 1267 sc->sc_flags.status_suspend = 0; 1268 sc->sc_flags.change_suspend = 0; 1269 sc->sc_flags.change_connect = 1; 1270 1271 avr32dci_pull_down(sc); 1272 avr32dci_clocks_off(sc); 1273 1274 USB_BUS_UNLOCK(&sc->sc_bus); 1275 } 1276 1277 static void 1278 avr32dci_suspend(struct avr32dci_softc *sc) 1279 { 1280 /* TODO */ 1281 } 1282 1283 static void 1284 avr32dci_resume(struct avr32dci_softc *sc) 1285 { 1286 /* TODO */ 1287 } 1288 1289 static void 1290 avr32dci_do_poll(struct usb_bus *bus) 1291 { 1292 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 1293 1294 USB_BUS_LOCK(&sc->sc_bus); 1295 avr32dci_interrupt_poll(sc); 1296 USB_BUS_UNLOCK(&sc->sc_bus); 1297 } 1298 1299 /*------------------------------------------------------------------------* 1300 * avr32dci bulk support 1301 * avr32dci control support 1302 * avr32dci interrupt support 1303 *------------------------------------------------------------------------*/ 1304 static void 1305 avr32dci_device_non_isoc_open(struct usb_xfer *xfer) 1306 { 1307 return; 1308 } 1309 1310 static void 1311 avr32dci_device_non_isoc_close(struct usb_xfer *xfer) 1312 { 1313 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1314 } 1315 1316 static void 1317 avr32dci_device_non_isoc_enter(struct usb_xfer *xfer) 1318 { 1319 return; 1320 } 1321 1322 static void 1323 avr32dci_device_non_isoc_start(struct usb_xfer *xfer) 1324 { 1325 /* setup TDs */ 1326 avr32dci_setup_standard_chain(xfer); 1327 avr32dci_start_standard_chain(xfer); 1328 } 1329 1330 static const struct usb_pipe_methods avr32dci_device_non_isoc_methods = 1331 { 1332 .open = avr32dci_device_non_isoc_open, 1333 .close = avr32dci_device_non_isoc_close, 1334 .enter = avr32dci_device_non_isoc_enter, 1335 .start = avr32dci_device_non_isoc_start, 1336 }; 1337 1338 /*------------------------------------------------------------------------* 1339 * avr32dci full speed isochronous support 1340 *------------------------------------------------------------------------*/ 1341 static void 1342 avr32dci_device_isoc_fs_open(struct usb_xfer *xfer) 1343 { 1344 return; 1345 } 1346 1347 static void 1348 avr32dci_device_isoc_fs_close(struct usb_xfer *xfer) 1349 { 1350 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1351 } 1352 1353 static void 1354 avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1355 { 1356 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1357 uint32_t temp; 1358 uint32_t nframes; 1359 uint8_t ep_no; 1360 1361 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1362 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1363 1364 /* get the current frame index */ 1365 ep_no = xfer->endpointno & UE_ADDR; 1366 nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8); 1367 1368 nframes &= AVR32_FRAME_MASK; 1369 1370 /* 1371 * check if the frame index is within the window where the frames 1372 * will be inserted 1373 */ 1374 temp = (nframes - xfer->endpoint->isoc_next) & AVR32_FRAME_MASK; 1375 1376 if ((xfer->endpoint->is_synced == 0) || 1377 (temp < xfer->nframes)) { 1378 /* 1379 * If there is data underflow or the pipe queue is 1380 * empty we schedule the transfer a few frames ahead 1381 * of the current frame position. Else two isochronous 1382 * transfers might overlap. 1383 */ 1384 xfer->endpoint->isoc_next = (nframes + 3) & AVR32_FRAME_MASK; 1385 xfer->endpoint->is_synced = 1; 1386 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1387 } 1388 /* 1389 * compute how many milliseconds the insertion is ahead of the 1390 * current frame position: 1391 */ 1392 temp = (xfer->endpoint->isoc_next - nframes) & AVR32_FRAME_MASK; 1393 1394 /* 1395 * pre-compute when the isochronous transfer will be finished: 1396 */ 1397 xfer->isoc_time_complete = 1398 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1399 xfer->nframes; 1400 1401 /* compute frame number for next insertion */ 1402 xfer->endpoint->isoc_next += xfer->nframes; 1403 1404 /* setup TDs */ 1405 avr32dci_setup_standard_chain(xfer); 1406 } 1407 1408 static void 1409 avr32dci_device_isoc_fs_start(struct usb_xfer *xfer) 1410 { 1411 /* start TD chain */ 1412 avr32dci_start_standard_chain(xfer); 1413 } 1414 1415 static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods = 1416 { 1417 .open = avr32dci_device_isoc_fs_open, 1418 .close = avr32dci_device_isoc_fs_close, 1419 .enter = avr32dci_device_isoc_fs_enter, 1420 .start = avr32dci_device_isoc_fs_start, 1421 }; 1422 1423 /*------------------------------------------------------------------------* 1424 * avr32dci root control support 1425 *------------------------------------------------------------------------* 1426 * Simulate a hardware HUB by handling all the necessary requests. 1427 *------------------------------------------------------------------------*/ 1428 1429 static const struct usb_device_descriptor avr32dci_devd = { 1430 .bLength = sizeof(struct usb_device_descriptor), 1431 .bDescriptorType = UDESC_DEVICE, 1432 .bcdUSB = {0x00, 0x02}, 1433 .bDeviceClass = UDCLASS_HUB, 1434 .bDeviceSubClass = UDSUBCLASS_HUB, 1435 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1436 .bMaxPacketSize = 64, 1437 .bcdDevice = {0x00, 0x01}, 1438 .iManufacturer = 1, 1439 .iProduct = 2, 1440 .bNumConfigurations = 1, 1441 }; 1442 1443 static const struct usb_device_qualifier avr32dci_odevd = { 1444 .bLength = sizeof(struct usb_device_qualifier), 1445 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1446 .bcdUSB = {0x00, 0x02}, 1447 .bDeviceClass = UDCLASS_HUB, 1448 .bDeviceSubClass = UDSUBCLASS_HUB, 1449 .bDeviceProtocol = UDPROTO_FSHUB, 1450 .bMaxPacketSize0 = 0, 1451 .bNumConfigurations = 0, 1452 }; 1453 1454 static const struct avr32dci_config_desc avr32dci_confd = { 1455 .confd = { 1456 .bLength = sizeof(struct usb_config_descriptor), 1457 .bDescriptorType = UDESC_CONFIG, 1458 .wTotalLength[0] = sizeof(avr32dci_confd), 1459 .bNumInterface = 1, 1460 .bConfigurationValue = 1, 1461 .iConfiguration = 0, 1462 .bmAttributes = UC_SELF_POWERED, 1463 .bMaxPower = 0, 1464 }, 1465 .ifcd = { 1466 .bLength = sizeof(struct usb_interface_descriptor), 1467 .bDescriptorType = UDESC_INTERFACE, 1468 .bNumEndpoints = 1, 1469 .bInterfaceClass = UICLASS_HUB, 1470 .bInterfaceSubClass = UISUBCLASS_HUB, 1471 .bInterfaceProtocol = 0, 1472 }, 1473 .endpd = { 1474 .bLength = sizeof(struct usb_endpoint_descriptor), 1475 .bDescriptorType = UDESC_ENDPOINT, 1476 .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT), 1477 .bmAttributes = UE_INTERRUPT, 1478 .wMaxPacketSize[0] = 8, 1479 .bInterval = 255, 1480 }, 1481 }; 1482 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1483 1484 static const struct usb_hub_descriptor_min avr32dci_hubd = { 1485 .bDescLength = sizeof(avr32dci_hubd), 1486 .bDescriptorType = UDESC_HUB, 1487 .bNbrPorts = 1, 1488 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1489 .bPwrOn2PwrGood = 50, 1490 .bHubContrCurrent = 0, 1491 .DeviceRemovable = {0}, /* port is removable */ 1492 }; 1493 1494 #define STRING_VENDOR \ 1495 "A\0V\0R\0003\0002" 1496 1497 #define STRING_PRODUCT \ 1498 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1499 1500 USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor); 1501 USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product); 1502 1503 static usb_error_t 1504 avr32dci_roothub_exec(struct usb_device *udev, 1505 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1506 { 1507 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 1508 const void *ptr; 1509 uint16_t len; 1510 uint16_t value; 1511 uint16_t index; 1512 uint32_t temp; 1513 usb_error_t err; 1514 1515 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1516 1517 /* buffer reset */ 1518 ptr = (const void *)&sc->sc_hub_temp; 1519 len = 0; 1520 err = 0; 1521 1522 value = UGETW(req->wValue); 1523 index = UGETW(req->wIndex); 1524 1525 /* demultiplex the control request */ 1526 1527 switch (req->bmRequestType) { 1528 case UT_READ_DEVICE: 1529 switch (req->bRequest) { 1530 case UR_GET_DESCRIPTOR: 1531 goto tr_handle_get_descriptor; 1532 case UR_GET_CONFIG: 1533 goto tr_handle_get_config; 1534 case UR_GET_STATUS: 1535 goto tr_handle_get_status; 1536 default: 1537 goto tr_stalled; 1538 } 1539 break; 1540 1541 case UT_WRITE_DEVICE: 1542 switch (req->bRequest) { 1543 case UR_SET_ADDRESS: 1544 goto tr_handle_set_address; 1545 case UR_SET_CONFIG: 1546 goto tr_handle_set_config; 1547 case UR_CLEAR_FEATURE: 1548 goto tr_valid; /* nop */ 1549 case UR_SET_DESCRIPTOR: 1550 goto tr_valid; /* nop */ 1551 case UR_SET_FEATURE: 1552 default: 1553 goto tr_stalled; 1554 } 1555 break; 1556 1557 case UT_WRITE_ENDPOINT: 1558 switch (req->bRequest) { 1559 case UR_CLEAR_FEATURE: 1560 switch (UGETW(req->wValue)) { 1561 case UF_ENDPOINT_HALT: 1562 goto tr_handle_clear_halt; 1563 case UF_DEVICE_REMOTE_WAKEUP: 1564 goto tr_handle_clear_wakeup; 1565 default: 1566 goto tr_stalled; 1567 } 1568 break; 1569 case UR_SET_FEATURE: 1570 switch (UGETW(req->wValue)) { 1571 case UF_ENDPOINT_HALT: 1572 goto tr_handle_set_halt; 1573 case UF_DEVICE_REMOTE_WAKEUP: 1574 goto tr_handle_set_wakeup; 1575 default: 1576 goto tr_stalled; 1577 } 1578 break; 1579 case UR_SYNCH_FRAME: 1580 goto tr_valid; /* nop */ 1581 default: 1582 goto tr_stalled; 1583 } 1584 break; 1585 1586 case UT_READ_ENDPOINT: 1587 switch (req->bRequest) { 1588 case UR_GET_STATUS: 1589 goto tr_handle_get_ep_status; 1590 default: 1591 goto tr_stalled; 1592 } 1593 break; 1594 1595 case UT_WRITE_INTERFACE: 1596 switch (req->bRequest) { 1597 case UR_SET_INTERFACE: 1598 goto tr_handle_set_interface; 1599 case UR_CLEAR_FEATURE: 1600 goto tr_valid; /* nop */ 1601 case UR_SET_FEATURE: 1602 default: 1603 goto tr_stalled; 1604 } 1605 break; 1606 1607 case UT_READ_INTERFACE: 1608 switch (req->bRequest) { 1609 case UR_GET_INTERFACE: 1610 goto tr_handle_get_interface; 1611 case UR_GET_STATUS: 1612 goto tr_handle_get_iface_status; 1613 default: 1614 goto tr_stalled; 1615 } 1616 break; 1617 1618 case UT_WRITE_CLASS_INTERFACE: 1619 case UT_WRITE_VENDOR_INTERFACE: 1620 /* XXX forward */ 1621 break; 1622 1623 case UT_READ_CLASS_INTERFACE: 1624 case UT_READ_VENDOR_INTERFACE: 1625 /* XXX forward */ 1626 break; 1627 1628 case UT_WRITE_CLASS_DEVICE: 1629 switch (req->bRequest) { 1630 case UR_CLEAR_FEATURE: 1631 goto tr_valid; 1632 case UR_SET_DESCRIPTOR: 1633 case UR_SET_FEATURE: 1634 break; 1635 default: 1636 goto tr_stalled; 1637 } 1638 break; 1639 1640 case UT_WRITE_CLASS_OTHER: 1641 switch (req->bRequest) { 1642 case UR_CLEAR_FEATURE: 1643 goto tr_handle_clear_port_feature; 1644 case UR_SET_FEATURE: 1645 goto tr_handle_set_port_feature; 1646 case UR_CLEAR_TT_BUFFER: 1647 case UR_RESET_TT: 1648 case UR_STOP_TT: 1649 goto tr_valid; 1650 1651 default: 1652 goto tr_stalled; 1653 } 1654 break; 1655 1656 case UT_READ_CLASS_OTHER: 1657 switch (req->bRequest) { 1658 case UR_GET_TT_STATE: 1659 goto tr_handle_get_tt_state; 1660 case UR_GET_STATUS: 1661 goto tr_handle_get_port_status; 1662 default: 1663 goto tr_stalled; 1664 } 1665 break; 1666 1667 case UT_READ_CLASS_DEVICE: 1668 switch (req->bRequest) { 1669 case UR_GET_DESCRIPTOR: 1670 goto tr_handle_get_class_descriptor; 1671 case UR_GET_STATUS: 1672 goto tr_handle_get_class_status; 1673 1674 default: 1675 goto tr_stalled; 1676 } 1677 break; 1678 default: 1679 goto tr_stalled; 1680 } 1681 goto tr_valid; 1682 1683 tr_handle_get_descriptor: 1684 switch (value >> 8) { 1685 case UDESC_DEVICE: 1686 if (value & 0xff) { 1687 goto tr_stalled; 1688 } 1689 len = sizeof(avr32dci_devd); 1690 ptr = (const void *)&avr32dci_devd; 1691 goto tr_valid; 1692 case UDESC_CONFIG: 1693 if (value & 0xff) { 1694 goto tr_stalled; 1695 } 1696 len = sizeof(avr32dci_confd); 1697 ptr = (const void *)&avr32dci_confd; 1698 goto tr_valid; 1699 case UDESC_STRING: 1700 switch (value & 0xff) { 1701 case 0: /* Language table */ 1702 len = sizeof(usb_string_lang_en); 1703 ptr = (const void *)&usb_string_lang_en; 1704 goto tr_valid; 1705 1706 case 1: /* Vendor */ 1707 len = sizeof(avr32dci_vendor); 1708 ptr = (const void *)&avr32dci_vendor; 1709 goto tr_valid; 1710 1711 case 2: /* Product */ 1712 len = sizeof(avr32dci_product); 1713 ptr = (const void *)&avr32dci_product; 1714 goto tr_valid; 1715 default: 1716 break; 1717 } 1718 break; 1719 default: 1720 goto tr_stalled; 1721 } 1722 goto tr_stalled; 1723 1724 tr_handle_get_config: 1725 len = 1; 1726 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1727 goto tr_valid; 1728 1729 tr_handle_get_status: 1730 len = 2; 1731 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1732 goto tr_valid; 1733 1734 tr_handle_set_address: 1735 if (value & 0xFF00) { 1736 goto tr_stalled; 1737 } 1738 sc->sc_rt_addr = value; 1739 goto tr_valid; 1740 1741 tr_handle_set_config: 1742 if (value >= 2) { 1743 goto tr_stalled; 1744 } 1745 sc->sc_conf = value; 1746 goto tr_valid; 1747 1748 tr_handle_get_interface: 1749 len = 1; 1750 sc->sc_hub_temp.wValue[0] = 0; 1751 goto tr_valid; 1752 1753 tr_handle_get_tt_state: 1754 tr_handle_get_class_status: 1755 tr_handle_get_iface_status: 1756 tr_handle_get_ep_status: 1757 len = 2; 1758 USETW(sc->sc_hub_temp.wValue, 0); 1759 goto tr_valid; 1760 1761 tr_handle_set_halt: 1762 tr_handle_set_interface: 1763 tr_handle_set_wakeup: 1764 tr_handle_clear_wakeup: 1765 tr_handle_clear_halt: 1766 goto tr_valid; 1767 1768 tr_handle_clear_port_feature: 1769 if (index != 1) { 1770 goto tr_stalled; 1771 } 1772 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1773 1774 switch (value) { 1775 case UHF_PORT_SUSPEND: 1776 avr32dci_wakeup_peer(sc); 1777 break; 1778 1779 case UHF_PORT_ENABLE: 1780 sc->sc_flags.port_enabled = 0; 1781 break; 1782 1783 case UHF_PORT_TEST: 1784 case UHF_PORT_INDICATOR: 1785 case UHF_C_PORT_ENABLE: 1786 case UHF_C_PORT_OVER_CURRENT: 1787 case UHF_C_PORT_RESET: 1788 /* nops */ 1789 break; 1790 case UHF_PORT_POWER: 1791 sc->sc_flags.port_powered = 0; 1792 avr32dci_pull_down(sc); 1793 avr32dci_clocks_off(sc); 1794 break; 1795 case UHF_C_PORT_CONNECTION: 1796 /* clear connect change flag */ 1797 sc->sc_flags.change_connect = 0; 1798 1799 if (!sc->sc_flags.status_bus_reset) { 1800 /* we are not connected */ 1801 break; 1802 } 1803 /* configure the control endpoint */ 1804 /* set endpoint reset */ 1805 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0)); 1806 1807 /* set stall */ 1808 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL); 1809 1810 /* reset data toggle */ 1811 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ); 1812 1813 /* clear stall */ 1814 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL); 1815 1816 /* configure */ 1817 AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CTRL | 1818 AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6)); 1819 1820 temp = AVR32_READ_4(sc, AVR32_EPTCFG(0)); 1821 1822 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1823 device_printf(sc->sc_bus.bdev, 1824 "Chip rejected configuration\n"); 1825 } else { 1826 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0), 1827 AVR32_EPTCTL_EPT_ENABL); 1828 } 1829 break; 1830 case UHF_C_PORT_SUSPEND: 1831 sc->sc_flags.change_suspend = 0; 1832 break; 1833 default: 1834 err = USB_ERR_IOERROR; 1835 goto done; 1836 } 1837 goto tr_valid; 1838 1839 tr_handle_set_port_feature: 1840 if (index != 1) { 1841 goto tr_stalled; 1842 } 1843 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1844 1845 switch (value) { 1846 case UHF_PORT_ENABLE: 1847 sc->sc_flags.port_enabled = 1; 1848 break; 1849 case UHF_PORT_SUSPEND: 1850 case UHF_PORT_RESET: 1851 case UHF_PORT_TEST: 1852 case UHF_PORT_INDICATOR: 1853 /* nops */ 1854 break; 1855 case UHF_PORT_POWER: 1856 sc->sc_flags.port_powered = 1; 1857 break; 1858 default: 1859 err = USB_ERR_IOERROR; 1860 goto done; 1861 } 1862 goto tr_valid; 1863 1864 tr_handle_get_port_status: 1865 1866 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1867 1868 if (index != 1) { 1869 goto tr_stalled; 1870 } 1871 if (sc->sc_flags.status_vbus) { 1872 avr32dci_clocks_on(sc); 1873 avr32dci_pull_up(sc); 1874 } else { 1875 avr32dci_pull_down(sc); 1876 avr32dci_clocks_off(sc); 1877 } 1878 1879 /* Select Device Side Mode */ 1880 1881 value = UPS_PORT_MODE_DEVICE; 1882 1883 /* Check for High Speed */ 1884 if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED) 1885 value |= UPS_HIGH_SPEED; 1886 1887 if (sc->sc_flags.port_powered) { 1888 value |= UPS_PORT_POWER; 1889 } 1890 if (sc->sc_flags.port_enabled) { 1891 value |= UPS_PORT_ENABLED; 1892 } 1893 if (sc->sc_flags.status_vbus && 1894 sc->sc_flags.status_bus_reset) { 1895 value |= UPS_CURRENT_CONNECT_STATUS; 1896 } 1897 if (sc->sc_flags.status_suspend) { 1898 value |= UPS_SUSPEND; 1899 } 1900 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1901 1902 value = 0; 1903 1904 if (sc->sc_flags.change_connect) { 1905 value |= UPS_C_CONNECT_STATUS; 1906 } 1907 if (sc->sc_flags.change_suspend) { 1908 value |= UPS_C_SUSPEND; 1909 } 1910 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1911 len = sizeof(sc->sc_hub_temp.ps); 1912 goto tr_valid; 1913 1914 tr_handle_get_class_descriptor: 1915 if (value & 0xFF) { 1916 goto tr_stalled; 1917 } 1918 ptr = (const void *)&avr32dci_hubd; 1919 len = sizeof(avr32dci_hubd); 1920 goto tr_valid; 1921 1922 tr_stalled: 1923 err = USB_ERR_STALLED; 1924 tr_valid: 1925 done: 1926 *plength = len; 1927 *pptr = ptr; 1928 return (err); 1929 } 1930 1931 static void 1932 avr32dci_xfer_setup(struct usb_setup_params *parm) 1933 { 1934 const struct usb_hw_ep_profile *pf; 1935 struct avr32dci_softc *sc; 1936 struct usb_xfer *xfer; 1937 void *last_obj; 1938 uint32_t ntd; 1939 uint32_t n; 1940 uint8_t ep_no; 1941 1942 sc = AVR32_BUS2SC(parm->udev->bus); 1943 xfer = parm->curr_xfer; 1944 1945 /* 1946 * NOTE: This driver does not use any of the parameters that 1947 * are computed from the following values. Just set some 1948 * reasonable dummies: 1949 */ 1950 parm->hc_max_packet_size = 0x400; 1951 parm->hc_max_packet_count = 1; 1952 parm->hc_max_frame_size = 0x400; 1953 1954 usbd_transfer_setup_sub(parm); 1955 1956 /* 1957 * compute maximum number of TDs 1958 */ 1959 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 1960 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 1961 + 1 /* SYNC 2 */ ; 1962 } else { 1963 ntd = xfer->nframes + 1 /* SYNC */ ; 1964 } 1965 1966 /* 1967 * check if "usbd_transfer_setup_sub" set an error 1968 */ 1969 if (parm->err) 1970 return; 1971 1972 /* 1973 * allocate transfer descriptors 1974 */ 1975 last_obj = NULL; 1976 1977 /* 1978 * get profile stuff 1979 */ 1980 ep_no = xfer->endpointno & UE_ADDR; 1981 avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 1982 1983 if (pf == NULL) { 1984 /* should not happen */ 1985 parm->err = USB_ERR_INVAL; 1986 return; 1987 } 1988 /* align data */ 1989 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 1990 1991 for (n = 0; n != ntd; n++) { 1992 struct avr32dci_td *td; 1993 1994 if (parm->buf) { 1995 uint32_t temp; 1996 1997 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 1998 1999 /* init TD */ 2000 td->max_packet_size = xfer->max_packet_size; 2001 td->ep_no = ep_no; 2002 temp = pf->max_in_frame_size | pf->max_out_frame_size; 2003 td->bank_shift = 0; 2004 while ((temp /= 2)) 2005 td->bank_shift++; 2006 if (pf->support_multi_buffer) { 2007 td->support_multi_buffer = 1; 2008 } 2009 td->obj_next = last_obj; 2010 2011 last_obj = td; 2012 } 2013 parm->size[0] += sizeof(*td); 2014 } 2015 2016 xfer->td_start[0] = last_obj; 2017 } 2018 2019 static void 2020 avr32dci_xfer_unsetup(struct usb_xfer *xfer) 2021 { 2022 return; 2023 } 2024 2025 static void 2026 avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2027 struct usb_endpoint *pipe) 2028 { 2029 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 2030 2031 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2032 pipe, udev->address, 2033 edesc->bEndpointAddress, udev->flags.usb_mode, 2034 sc->sc_rt_addr, udev->device_index); 2035 2036 if (udev->device_index != sc->sc_rt_addr) { 2037 if ((udev->speed != USB_SPEED_FULL) && 2038 (udev->speed != USB_SPEED_HIGH)) { 2039 /* not supported */ 2040 return; 2041 } 2042 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2043 pipe->methods = &avr32dci_device_isoc_fs_methods; 2044 else 2045 pipe->methods = &avr32dci_device_non_isoc_methods; 2046 } 2047 } 2048 2049 static void 2050 avr32dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2051 { 2052 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 2053 2054 switch (state) { 2055 case USB_HW_POWER_SUSPEND: 2056 avr32dci_suspend(sc); 2057 break; 2058 case USB_HW_POWER_SHUTDOWN: 2059 avr32dci_uninit(sc); 2060 break; 2061 case USB_HW_POWER_RESUME: 2062 avr32dci_resume(sc); 2063 break; 2064 default: 2065 break; 2066 } 2067 } 2068 2069 static const struct usb_bus_methods avr32dci_bus_methods = 2070 { 2071 .endpoint_init = &avr32dci_ep_init, 2072 .xfer_setup = &avr32dci_xfer_setup, 2073 .xfer_unsetup = &avr32dci_xfer_unsetup, 2074 .get_hw_ep_profile = &avr32dci_get_hw_ep_profile, 2075 .xfer_stall = &avr32dci_xfer_stall, 2076 .set_stall = &avr32dci_set_stall, 2077 .clear_stall = &avr32dci_clear_stall, 2078 .roothub_exec = &avr32dci_roothub_exec, 2079 .xfer_poll = &avr32dci_do_poll, 2080 .set_hw_power_sleep = &avr32dci_set_hw_power_sleep, 2081 }; 2082