127d5dc18SMarcel Moolenaar /* 227d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 327d5dc18SMarcel Moolenaar * All rights reserved. 427d5dc18SMarcel Moolenaar * 527d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 627d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 727d5dc18SMarcel Moolenaar * are met: 827d5dc18SMarcel Moolenaar * 927d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1027d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1127d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1327d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1427d5dc18SMarcel Moolenaar * 1527d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1627d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1727d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1827d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1927d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2027d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2127d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2227d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2327d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2427d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2527d5dc18SMarcel Moolenaar */ 2627d5dc18SMarcel Moolenaar 2727d5dc18SMarcel Moolenaar #include <sys/cdefs.h> 2827d5dc18SMarcel Moolenaar __FBSDID("$FreeBSD$"); 2927d5dc18SMarcel Moolenaar 3027d5dc18SMarcel Moolenaar #ifndef KLD_MODULE 3127d5dc18SMarcel Moolenaar #include "opt_comconsole.h" 3227d5dc18SMarcel Moolenaar #include "opt_ddb.h" 3327d5dc18SMarcel Moolenaar #endif 3427d5dc18SMarcel Moolenaar 3527d5dc18SMarcel Moolenaar #include <sys/param.h> 3627d5dc18SMarcel Moolenaar #include <sys/systm.h> 3727d5dc18SMarcel Moolenaar #include <sys/bus.h> 3827d5dc18SMarcel Moolenaar #include <sys/conf.h> 3927d5dc18SMarcel Moolenaar #include <sys/cons.h> 4027d5dc18SMarcel Moolenaar #include <sys/fcntl.h> 4127d5dc18SMarcel Moolenaar #include <sys/interrupt.h> 4227d5dc18SMarcel Moolenaar #include <sys/kernel.h> 4327d5dc18SMarcel Moolenaar #include <sys/malloc.h> 4427d5dc18SMarcel Moolenaar #include <sys/queue.h> 4527d5dc18SMarcel Moolenaar #include <sys/reboot.h> 4627d5dc18SMarcel Moolenaar #include <machine/bus.h> 4727d5dc18SMarcel Moolenaar #include <sys/rman.h> 4827d5dc18SMarcel Moolenaar #include <sys/termios.h> 4927d5dc18SMarcel Moolenaar #include <sys/tty.h> 5027d5dc18SMarcel Moolenaar #include <machine/resource.h> 5127d5dc18SMarcel Moolenaar #include <machine/stdarg.h> 5227d5dc18SMarcel Moolenaar 5327d5dc18SMarcel Moolenaar #include <ddb/ddb.h> 5427d5dc18SMarcel Moolenaar 5527d5dc18SMarcel Moolenaar #include <dev/uart/uart.h> 5627d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h> 5727d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h> 5827d5dc18SMarcel Moolenaar 5927d5dc18SMarcel Moolenaar #include "uart_if.h" 6027d5dc18SMarcel Moolenaar 6127d5dc18SMarcel Moolenaar devclass_t uart_devclass; 6227d5dc18SMarcel Moolenaar char uart_driver_name[] = "uart"; 6327d5dc18SMarcel Moolenaar 6427d5dc18SMarcel Moolenaar SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs = 6527d5dc18SMarcel Moolenaar SLIST_HEAD_INITIALIZER(uart_sysdevs); 6627d5dc18SMarcel Moolenaar 6727d5dc18SMarcel Moolenaar MALLOC_DEFINE(M_UART, "UART", "UART driver"); 6827d5dc18SMarcel Moolenaar 6927d5dc18SMarcel Moolenaar void 7027d5dc18SMarcel Moolenaar uart_add_sysdev(struct uart_devinfo *di) 7127d5dc18SMarcel Moolenaar { 7227d5dc18SMarcel Moolenaar SLIST_INSERT_HEAD(&uart_sysdevs, di, next); 7327d5dc18SMarcel Moolenaar } 7427d5dc18SMarcel Moolenaar 7527d5dc18SMarcel Moolenaar /* 7627d5dc18SMarcel Moolenaar * A break condition has been detected. We treat the break condition as 7727d5dc18SMarcel Moolenaar * a special case that should not happen during normal operation. When 7827d5dc18SMarcel Moolenaar * the break condition is to be passed to higher levels in the form of 7927d5dc18SMarcel Moolenaar * a NUL character, we really want the break to be in the right place in 8027d5dc18SMarcel Moolenaar * the input stream. The overhead to achieve that is not in relation to 8127d5dc18SMarcel Moolenaar * the exceptional nature of the break condition, so we permit ourselves 8227d5dc18SMarcel Moolenaar * to be sloppy. 8327d5dc18SMarcel Moolenaar */ 8427d5dc18SMarcel Moolenaar static void 8527d5dc18SMarcel Moolenaar uart_intr_break(struct uart_softc *sc) 8627d5dc18SMarcel Moolenaar { 8727d5dc18SMarcel Moolenaar 8827d5dc18SMarcel Moolenaar #if defined(DDB) && defined(BREAK_TO_DEBUGGER) 8927d5dc18SMarcel Moolenaar if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { 9027d5dc18SMarcel Moolenaar breakpoint(); 9127d5dc18SMarcel Moolenaar return; 9227d5dc18SMarcel Moolenaar } 9327d5dc18SMarcel Moolenaar #endif 9427d5dc18SMarcel Moolenaar if (sc->sc_opened) 9527d5dc18SMarcel Moolenaar atomic_set_32(&sc->sc_ttypend, UART_IPEND_BREAK); 9627d5dc18SMarcel Moolenaar } 9727d5dc18SMarcel Moolenaar 9827d5dc18SMarcel Moolenaar /* 9927d5dc18SMarcel Moolenaar * Handle a receiver overrun situation. We lost at least 1 byte in the 10027d5dc18SMarcel Moolenaar * input stream and it's our job to contain the situation. We grab as 10127d5dc18SMarcel Moolenaar * much of the data we can, but otherwise flush the receiver FIFO to 10227d5dc18SMarcel Moolenaar * create some breathing room. The net effect is that we avoid the 10327d5dc18SMarcel Moolenaar * overrun condition to happen for the next X characters, where X is 10427d5dc18SMarcel Moolenaar * related to the FIFO size at the cost of loosing data right away. 10527d5dc18SMarcel Moolenaar * So, instead of having multiple overrun interrupts in close proximity 10627d5dc18SMarcel Moolenaar * to each other and possibly pessimizing UART interrupt latency for 10727d5dc18SMarcel Moolenaar * other UARTs in a multiport configuration, we create a longer segment 10827d5dc18SMarcel Moolenaar * of missing characters by freeing up the FIFO. 10927d5dc18SMarcel Moolenaar * Each overrun condition is marked in the input buffer by a token. The 11027d5dc18SMarcel Moolenaar * token represents the loss of at least one, but possible more bytes in 11127d5dc18SMarcel Moolenaar * the input stream. 11227d5dc18SMarcel Moolenaar */ 11327d5dc18SMarcel Moolenaar static void 11427d5dc18SMarcel Moolenaar uart_intr_overrun(struct uart_softc *sc) 11527d5dc18SMarcel Moolenaar { 11627d5dc18SMarcel Moolenaar 11727d5dc18SMarcel Moolenaar if (sc->sc_opened) { 11827d5dc18SMarcel Moolenaar UART_RECEIVE(sc); 11927d5dc18SMarcel Moolenaar if (uart_rx_put(sc, UART_STAT_OVERRUN)) 12027d5dc18SMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 12127d5dc18SMarcel Moolenaar atomic_set_32(&sc->sc_ttypend, UART_IPEND_RXREADY); 12227d5dc18SMarcel Moolenaar } 12327d5dc18SMarcel Moolenaar UART_FLUSH(sc, UART_FLUSH_RECEIVER); 12427d5dc18SMarcel Moolenaar } 12527d5dc18SMarcel Moolenaar 12627d5dc18SMarcel Moolenaar /* 12727d5dc18SMarcel Moolenaar * Received data ready. 12827d5dc18SMarcel Moolenaar */ 12927d5dc18SMarcel Moolenaar static void 13027d5dc18SMarcel Moolenaar uart_intr_rxready(struct uart_softc *sc) 13127d5dc18SMarcel Moolenaar { 13227d5dc18SMarcel Moolenaar int rxp; 13327d5dc18SMarcel Moolenaar 13427d5dc18SMarcel Moolenaar rxp = sc->sc_rxput; 13527d5dc18SMarcel Moolenaar UART_RECEIVE(sc); 13627d5dc18SMarcel Moolenaar #if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER) 13727d5dc18SMarcel Moolenaar if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { 13827d5dc18SMarcel Moolenaar while (rxp != sc->sc_rxput) { 13927d5dc18SMarcel Moolenaar if (db_alt_break(sc->sc_rxbuf[rxp++], &sc->sc_altbrk)) 14027d5dc18SMarcel Moolenaar breakpoint(); 14127d5dc18SMarcel Moolenaar if (rxp == sc->sc_rxbufsz) 14227d5dc18SMarcel Moolenaar rxp = 0; 14327d5dc18SMarcel Moolenaar } 14427d5dc18SMarcel Moolenaar } 14527d5dc18SMarcel Moolenaar #endif 14627d5dc18SMarcel Moolenaar if (sc->sc_opened) 14727d5dc18SMarcel Moolenaar atomic_set_32(&sc->sc_ttypend, UART_IPEND_RXREADY); 14827d5dc18SMarcel Moolenaar else 14927d5dc18SMarcel Moolenaar sc->sc_rxput = sc->sc_rxget; /* Ignore received data. */ 15027d5dc18SMarcel Moolenaar } 15127d5dc18SMarcel Moolenaar 15227d5dc18SMarcel Moolenaar /* 15327d5dc18SMarcel Moolenaar * Line or modem status change (OOB signalling). 15427d5dc18SMarcel Moolenaar * We pass the signals to the software interrupt handler for further 15527d5dc18SMarcel Moolenaar * processing. Note that we merge the delta bits, but set the state 15627d5dc18SMarcel Moolenaar * bits. This is to avoid loosing state transitions due to having more 15727d5dc18SMarcel Moolenaar * than 1 hardware interrupt between software interrupts. 15827d5dc18SMarcel Moolenaar */ 15927d5dc18SMarcel Moolenaar static void 16027d5dc18SMarcel Moolenaar uart_intr_sigchg(struct uart_softc *sc) 16127d5dc18SMarcel Moolenaar { 16227d5dc18SMarcel Moolenaar int new, old, sig; 16327d5dc18SMarcel Moolenaar 16427d5dc18SMarcel Moolenaar sig = UART_GETSIG(sc); 1658194412bSMarcel Moolenaar 1668194412bSMarcel Moolenaar if (sc->sc_pps.ppsparam.mode & PPS_CAPTUREBOTH) { 1678194412bSMarcel Moolenaar if (sig & UART_SIG_DPPS) { 1688194412bSMarcel Moolenaar pps_capture(&sc->sc_pps); 1698194412bSMarcel Moolenaar pps_event(&sc->sc_pps, (sig & UART_SIG_PPS) ? 1708194412bSMarcel Moolenaar PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 1718194412bSMarcel Moolenaar } 1728194412bSMarcel Moolenaar } 1738194412bSMarcel Moolenaar 17427d5dc18SMarcel Moolenaar do { 17527d5dc18SMarcel Moolenaar old = sc->sc_ttypend; 17627d5dc18SMarcel Moolenaar new = old & ~UART_SIGMASK_STATE; 17727d5dc18SMarcel Moolenaar new |= sig & UART_IPEND_SIGMASK; 17827d5dc18SMarcel Moolenaar new |= UART_IPEND_SIGCHG; 17927d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_ttypend, old, new)); 18027d5dc18SMarcel Moolenaar } 18127d5dc18SMarcel Moolenaar 18227d5dc18SMarcel Moolenaar /* 18327d5dc18SMarcel Moolenaar * The transmitter can accept more data. 18427d5dc18SMarcel Moolenaar */ 18527d5dc18SMarcel Moolenaar static void 18627d5dc18SMarcel Moolenaar uart_intr_txidle(struct uart_softc *sc) 18727d5dc18SMarcel Moolenaar { 18827d5dc18SMarcel Moolenaar if (sc->sc_txbusy) { 18927d5dc18SMarcel Moolenaar sc->sc_txbusy = 0; 19027d5dc18SMarcel Moolenaar atomic_set_32(&sc->sc_ttypend, UART_IPEND_TXIDLE); 19127d5dc18SMarcel Moolenaar } 19227d5dc18SMarcel Moolenaar } 19327d5dc18SMarcel Moolenaar 19427d5dc18SMarcel Moolenaar static void 19527d5dc18SMarcel Moolenaar uart_intr(void *arg) 19627d5dc18SMarcel Moolenaar { 19727d5dc18SMarcel Moolenaar struct uart_softc *sc = arg; 19827d5dc18SMarcel Moolenaar int ipend; 19927d5dc18SMarcel Moolenaar 20027d5dc18SMarcel Moolenaar if (sc->sc_leaving) 20127d5dc18SMarcel Moolenaar return; 20227d5dc18SMarcel Moolenaar 20344ed791bSMarcel Moolenaar do { 20427d5dc18SMarcel Moolenaar ipend = UART_IPEND(sc); 20544ed791bSMarcel Moolenaar if (ipend == 0) 20644ed791bSMarcel Moolenaar break; 20727d5dc18SMarcel Moolenaar if (ipend & UART_IPEND_OVERRUN) 20827d5dc18SMarcel Moolenaar uart_intr_overrun(sc); 20927d5dc18SMarcel Moolenaar if (ipend & UART_IPEND_BREAK) 21027d5dc18SMarcel Moolenaar uart_intr_break(sc); 21127d5dc18SMarcel Moolenaar if (ipend & UART_IPEND_RXREADY) 21227d5dc18SMarcel Moolenaar uart_intr_rxready(sc); 21327d5dc18SMarcel Moolenaar if (ipend & UART_IPEND_SIGCHG) 21427d5dc18SMarcel Moolenaar uart_intr_sigchg(sc); 21527d5dc18SMarcel Moolenaar if (ipend & UART_IPEND_TXIDLE) 21627d5dc18SMarcel Moolenaar uart_intr_txidle(sc); 21744ed791bSMarcel Moolenaar } while (1); 21827d5dc18SMarcel Moolenaar 21927d5dc18SMarcel Moolenaar if (sc->sc_opened && sc->sc_ttypend != 0) 22027d5dc18SMarcel Moolenaar swi_sched(sc->sc_softih, 0); 22127d5dc18SMarcel Moolenaar } 22227d5dc18SMarcel Moolenaar 22327d5dc18SMarcel Moolenaar int 224875f70dbSMarcel Moolenaar uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan) 22527d5dc18SMarcel Moolenaar { 22627d5dc18SMarcel Moolenaar struct uart_softc *sc; 22727d5dc18SMarcel Moolenaar struct uart_devinfo *sysdev; 22827d5dc18SMarcel Moolenaar int error; 22927d5dc18SMarcel Moolenaar 23027d5dc18SMarcel Moolenaar /* 23127d5dc18SMarcel Moolenaar * Initialize the instance. Note that the instance (=softc) does 23227d5dc18SMarcel Moolenaar * not necessarily match the hardware specific softc. We can't do 23327d5dc18SMarcel Moolenaar * anything about it now, because we may not attach to the device. 23427d5dc18SMarcel Moolenaar * Hardware drivers cannot use any of the class specific fields 23527d5dc18SMarcel Moolenaar * while probing. 23627d5dc18SMarcel Moolenaar */ 23727d5dc18SMarcel Moolenaar sc = device_get_softc(dev); 23827d5dc18SMarcel Moolenaar kobj_init((kobj_t)sc, (kobj_class_t)sc->sc_class); 23927d5dc18SMarcel Moolenaar sc->sc_dev = dev; 24027d5dc18SMarcel Moolenaar if (device_get_desc(dev) == NULL) 24127d5dc18SMarcel Moolenaar device_set_desc(dev, sc->sc_class->name); 24227d5dc18SMarcel Moolenaar 24327d5dc18SMarcel Moolenaar /* 24427d5dc18SMarcel Moolenaar * Allocate the register resource. We assume that all UARTs have 24527d5dc18SMarcel Moolenaar * a single register window in either I/O port space or memory 24627d5dc18SMarcel Moolenaar * mapped I/O space. Any UART that needs multiple windows will 24727d5dc18SMarcel Moolenaar * consequently not be supported by this driver as-is. We try I/O 24827d5dc18SMarcel Moolenaar * port space first because that's the common case. 24927d5dc18SMarcel Moolenaar */ 25027d5dc18SMarcel Moolenaar sc->sc_rrid = rid; 25127d5dc18SMarcel Moolenaar sc->sc_rtype = SYS_RES_IOPORT; 25227d5dc18SMarcel Moolenaar sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid, 25327d5dc18SMarcel Moolenaar 0, ~0, sc->sc_class->uc_range, RF_ACTIVE); 25427d5dc18SMarcel Moolenaar if (sc->sc_rres == NULL) { 25527d5dc18SMarcel Moolenaar sc->sc_rrid = rid; 25627d5dc18SMarcel Moolenaar sc->sc_rtype = SYS_RES_MEMORY; 25727d5dc18SMarcel Moolenaar sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, 25827d5dc18SMarcel Moolenaar &sc->sc_rrid, 0, ~0, sc->sc_class->uc_range, RF_ACTIVE); 25927d5dc18SMarcel Moolenaar if (sc->sc_rres == NULL) 26027d5dc18SMarcel Moolenaar return (ENXIO); 26127d5dc18SMarcel Moolenaar } 26227d5dc18SMarcel Moolenaar 26327d5dc18SMarcel Moolenaar /* 26427d5dc18SMarcel Moolenaar * Fill in the bus access structure and compare this device with 26527d5dc18SMarcel Moolenaar * a possible console device and/or a debug port. We set the flags 26627d5dc18SMarcel Moolenaar * in the softc so that the hardware dependent probe can adjust 26727d5dc18SMarcel Moolenaar * accordingly. In general, you don't want to permanently disrupt 26827d5dc18SMarcel Moolenaar * console I/O. 26927d5dc18SMarcel Moolenaar */ 27027d5dc18SMarcel Moolenaar sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres); 27127d5dc18SMarcel Moolenaar sc->sc_bas.bst = rman_get_bustag(sc->sc_rres); 272875f70dbSMarcel Moolenaar sc->sc_bas.chan = chan; 27327d5dc18SMarcel Moolenaar sc->sc_bas.regshft = regshft; 27427d5dc18SMarcel Moolenaar sc->sc_bas.rclk = (rclk == 0) ? sc->sc_class->uc_rclk : rclk; 27527d5dc18SMarcel Moolenaar 27627d5dc18SMarcel Moolenaar SLIST_FOREACH(sysdev, &uart_sysdevs, next) { 277875f70dbSMarcel Moolenaar if (chan == sysdev->bas.chan && 278875f70dbSMarcel Moolenaar uart_cpu_eqres(&sc->sc_bas, &sysdev->bas)) { 27927d5dc18SMarcel Moolenaar /* XXX check if ops matches class. */ 28027d5dc18SMarcel Moolenaar sc->sc_sysdev = sysdev; 28127d5dc18SMarcel Moolenaar break; 28227d5dc18SMarcel Moolenaar } 28327d5dc18SMarcel Moolenaar } 28427d5dc18SMarcel Moolenaar 28527d5dc18SMarcel Moolenaar error = UART_PROBE(sc); 28627d5dc18SMarcel Moolenaar bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); 28727d5dc18SMarcel Moolenaar return (error); 28827d5dc18SMarcel Moolenaar } 28927d5dc18SMarcel Moolenaar 29027d5dc18SMarcel Moolenaar int 29127d5dc18SMarcel Moolenaar uart_bus_attach(device_t dev) 29227d5dc18SMarcel Moolenaar { 29327d5dc18SMarcel Moolenaar struct uart_softc *sc, *sc0; 29427d5dc18SMarcel Moolenaar const char *sep; 29527d5dc18SMarcel Moolenaar int error; 29627d5dc18SMarcel Moolenaar 29727d5dc18SMarcel Moolenaar /* 29827d5dc18SMarcel Moolenaar * The sc_class field defines the type of UART we're going to work 29927d5dc18SMarcel Moolenaar * with and thus the size of the softc. Replace the generic softc 30027d5dc18SMarcel Moolenaar * with one that matches the UART now that we're certain we handle 30127d5dc18SMarcel Moolenaar * the device. 30227d5dc18SMarcel Moolenaar */ 30327d5dc18SMarcel Moolenaar sc0 = device_get_softc(dev); 30427d5dc18SMarcel Moolenaar if (sc0->sc_class->size > sizeof(*sc)) { 30527d5dc18SMarcel Moolenaar sc = malloc(sc0->sc_class->size, M_UART, M_WAITOK|M_ZERO); 30627d5dc18SMarcel Moolenaar bcopy(sc0, sc, sizeof(*sc)); 30727d5dc18SMarcel Moolenaar device_set_softc(dev, sc); 30827d5dc18SMarcel Moolenaar } else 30927d5dc18SMarcel Moolenaar sc = sc0; 31027d5dc18SMarcel Moolenaar 31127d5dc18SMarcel Moolenaar /* 31227d5dc18SMarcel Moolenaar * Protect ourselves against interrupts while we're not completely 31327d5dc18SMarcel Moolenaar * finished attaching and initializing. We don't expect interrupts 31427d5dc18SMarcel Moolenaar * until after UART_ATTACH() though. 31527d5dc18SMarcel Moolenaar */ 31627d5dc18SMarcel Moolenaar sc->sc_leaving = 1; 31727d5dc18SMarcel Moolenaar 31806287620SMarcel Moolenaar mtx_init(&sc->sc_hwmtx, "uart_hwmtx", NULL, MTX_SPIN); 31906287620SMarcel Moolenaar 32027d5dc18SMarcel Moolenaar /* 32127d5dc18SMarcel Moolenaar * Re-allocate. We expect that the softc contains the information 32227d5dc18SMarcel Moolenaar * collected by uart_bus_probe() intact. 32327d5dc18SMarcel Moolenaar */ 32427d5dc18SMarcel Moolenaar sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid, 32527d5dc18SMarcel Moolenaar 0, ~0, sc->sc_class->uc_range, RF_ACTIVE); 32627d5dc18SMarcel Moolenaar if (sc->sc_rres == NULL) 32727d5dc18SMarcel Moolenaar return (ENXIO); 328b8759afcSYoshihiro Takahashi sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres); 329b8759afcSYoshihiro Takahashi sc->sc_bas.bst = rman_get_bustag(sc->sc_rres); 330b8759afcSYoshihiro Takahashi 33127d5dc18SMarcel Moolenaar sc->sc_irid = 0; 3325f96beb9SNate Lawson sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid, 3335f96beb9SNate Lawson RF_ACTIVE); 33427d5dc18SMarcel Moolenaar if (sc->sc_ires != NULL) { 33527d5dc18SMarcel Moolenaar error = BUS_SETUP_INTR(device_get_parent(dev), dev, 33627d5dc18SMarcel Moolenaar sc->sc_ires, INTR_TYPE_TTY | INTR_FAST, uart_intr, 33727d5dc18SMarcel Moolenaar sc, &sc->sc_icookie); 33827d5dc18SMarcel Moolenaar if (error) 33927d5dc18SMarcel Moolenaar error = BUS_SETUP_INTR(device_get_parent(dev), dev, 340*5918c72dSMarcel Moolenaar sc->sc_ires, INTR_TYPE_TTY | INTR_MPSAFE, 341*5918c72dSMarcel Moolenaar uart_intr, sc, &sc->sc_icookie); 34227d5dc18SMarcel Moolenaar else 34327d5dc18SMarcel Moolenaar sc->sc_fastintr = 1; 34427d5dc18SMarcel Moolenaar 34527d5dc18SMarcel Moolenaar if (error) { 34627d5dc18SMarcel Moolenaar device_printf(dev, "could not activate interrupt\n"); 34727d5dc18SMarcel Moolenaar bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, 34827d5dc18SMarcel Moolenaar sc->sc_ires); 34927d5dc18SMarcel Moolenaar sc->sc_ires = NULL; 35027d5dc18SMarcel Moolenaar } 35127d5dc18SMarcel Moolenaar } 35227d5dc18SMarcel Moolenaar if (sc->sc_ires == NULL) { 35327d5dc18SMarcel Moolenaar /* XXX no interrupt resource. Force polled mode. */ 35427d5dc18SMarcel Moolenaar sc->sc_polled = 1; 35527d5dc18SMarcel Moolenaar } 35627d5dc18SMarcel Moolenaar 35727d5dc18SMarcel Moolenaar sc->sc_rxbufsz = IBUFSIZ; 35827d5dc18SMarcel Moolenaar sc->sc_rxbuf = malloc(sc->sc_rxbufsz * sizeof(*sc->sc_rxbuf), 35927d5dc18SMarcel Moolenaar M_UART, M_WAITOK); 36027d5dc18SMarcel Moolenaar sc->sc_txbuf = malloc(sc->sc_txfifosz * sizeof(*sc->sc_txbuf), 36127d5dc18SMarcel Moolenaar M_UART, M_WAITOK); 36227d5dc18SMarcel Moolenaar 36327d5dc18SMarcel Moolenaar error = UART_ATTACH(sc); 36427d5dc18SMarcel Moolenaar if (error) 36527d5dc18SMarcel Moolenaar goto fail; 36627d5dc18SMarcel Moolenaar 36727d5dc18SMarcel Moolenaar if (sc->sc_hwiflow || sc->sc_hwoflow) { 36827d5dc18SMarcel Moolenaar sep = ""; 36927d5dc18SMarcel Moolenaar device_print_prettyname(dev); 37027d5dc18SMarcel Moolenaar if (sc->sc_hwiflow) { 37127d5dc18SMarcel Moolenaar printf("%sRTS iflow", sep); 37227d5dc18SMarcel Moolenaar sep = ", "; 37327d5dc18SMarcel Moolenaar } 37427d5dc18SMarcel Moolenaar if (sc->sc_hwoflow) { 37527d5dc18SMarcel Moolenaar printf("%sCTS oflow", sep); 37627d5dc18SMarcel Moolenaar sep = ", "; 37727d5dc18SMarcel Moolenaar } 37827d5dc18SMarcel Moolenaar printf("\n"); 37927d5dc18SMarcel Moolenaar } 38027d5dc18SMarcel Moolenaar 38127d5dc18SMarcel Moolenaar if (bootverbose && (sc->sc_fastintr || sc->sc_polled)) { 38227d5dc18SMarcel Moolenaar sep = ""; 38327d5dc18SMarcel Moolenaar device_print_prettyname(dev); 38427d5dc18SMarcel Moolenaar if (sc->sc_fastintr) { 38527d5dc18SMarcel Moolenaar printf("%sfast interrupt", sep); 38627d5dc18SMarcel Moolenaar sep = ", "; 38727d5dc18SMarcel Moolenaar } 38827d5dc18SMarcel Moolenaar if (sc->sc_polled) { 38927d5dc18SMarcel Moolenaar printf("%spolled mode", sep); 39027d5dc18SMarcel Moolenaar sep = ", "; 39127d5dc18SMarcel Moolenaar } 39227d5dc18SMarcel Moolenaar printf("\n"); 39327d5dc18SMarcel Moolenaar } 39427d5dc18SMarcel Moolenaar 39527d5dc18SMarcel Moolenaar if (sc->sc_sysdev != NULL) { 39627d5dc18SMarcel Moolenaar switch (sc->sc_sysdev->type) { 39727d5dc18SMarcel Moolenaar case UART_DEV_CONSOLE: 39827d5dc18SMarcel Moolenaar device_printf(dev, "console"); 39927d5dc18SMarcel Moolenaar break; 40027d5dc18SMarcel Moolenaar case UART_DEV_DBGPORT: 40127d5dc18SMarcel Moolenaar device_printf(dev, "debug port"); 40227d5dc18SMarcel Moolenaar break; 40327d5dc18SMarcel Moolenaar case UART_DEV_KEYBOARD: 40427d5dc18SMarcel Moolenaar device_printf(dev, "keyboard"); 40527d5dc18SMarcel Moolenaar break; 40627d5dc18SMarcel Moolenaar default: 40727d5dc18SMarcel Moolenaar device_printf(dev, "unknown system device"); 40827d5dc18SMarcel Moolenaar break; 40927d5dc18SMarcel Moolenaar } 41027d5dc18SMarcel Moolenaar printf(" (%d,%c,%d,%d)\n", sc->sc_sysdev->baudrate, 41127d5dc18SMarcel Moolenaar "noems"[sc->sc_sysdev->parity], sc->sc_sysdev->databits, 41227d5dc18SMarcel Moolenaar sc->sc_sysdev->stopbits); 41327d5dc18SMarcel Moolenaar } 41427d5dc18SMarcel Moolenaar 4158194412bSMarcel Moolenaar sc->sc_pps.ppscap = PPS_CAPTUREBOTH; 4168194412bSMarcel Moolenaar pps_init(&sc->sc_pps); 4178194412bSMarcel Moolenaar 41827d5dc18SMarcel Moolenaar error = (sc->sc_sysdev != NULL && sc->sc_sysdev->attach != NULL) 41927d5dc18SMarcel Moolenaar ? (*sc->sc_sysdev->attach)(sc) : uart_tty_attach(sc); 42027d5dc18SMarcel Moolenaar if (error) 42127d5dc18SMarcel Moolenaar goto fail; 42227d5dc18SMarcel Moolenaar 42327d5dc18SMarcel Moolenaar sc->sc_leaving = 0; 42427d5dc18SMarcel Moolenaar uart_intr(sc); 42527d5dc18SMarcel Moolenaar return (0); 42627d5dc18SMarcel Moolenaar 42727d5dc18SMarcel Moolenaar fail: 42827d5dc18SMarcel Moolenaar free(sc->sc_txbuf, M_UART); 42927d5dc18SMarcel Moolenaar free(sc->sc_rxbuf, M_UART); 43027d5dc18SMarcel Moolenaar 43127d5dc18SMarcel Moolenaar if (sc->sc_ires != NULL) { 43227d5dc18SMarcel Moolenaar bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie); 43327d5dc18SMarcel Moolenaar bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, 43427d5dc18SMarcel Moolenaar sc->sc_ires); 43527d5dc18SMarcel Moolenaar } 43627d5dc18SMarcel Moolenaar bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); 43727d5dc18SMarcel Moolenaar 43827d5dc18SMarcel Moolenaar return (error); 43927d5dc18SMarcel Moolenaar } 44027d5dc18SMarcel Moolenaar 44127d5dc18SMarcel Moolenaar int 44227d5dc18SMarcel Moolenaar uart_bus_detach(device_t dev) 44327d5dc18SMarcel Moolenaar { 44427d5dc18SMarcel Moolenaar struct uart_softc *sc; 44527d5dc18SMarcel Moolenaar 44627d5dc18SMarcel Moolenaar sc = device_get_softc(dev); 44727d5dc18SMarcel Moolenaar 44827d5dc18SMarcel Moolenaar sc->sc_leaving = 1; 44927d5dc18SMarcel Moolenaar 45027d5dc18SMarcel Moolenaar UART_DETACH(sc); 45127d5dc18SMarcel Moolenaar 45227d5dc18SMarcel Moolenaar if (sc->sc_sysdev != NULL && sc->sc_sysdev->detach != NULL) 45327d5dc18SMarcel Moolenaar (*sc->sc_sysdev->detach)(sc); 45427d5dc18SMarcel Moolenaar else 45527d5dc18SMarcel Moolenaar uart_tty_detach(sc); 45627d5dc18SMarcel Moolenaar 45727d5dc18SMarcel Moolenaar free(sc->sc_txbuf, M_UART); 45827d5dc18SMarcel Moolenaar free(sc->sc_rxbuf, M_UART); 45927d5dc18SMarcel Moolenaar 46027d5dc18SMarcel Moolenaar if (sc->sc_ires != NULL) { 46127d5dc18SMarcel Moolenaar bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie); 46227d5dc18SMarcel Moolenaar bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, 46327d5dc18SMarcel Moolenaar sc->sc_ires); 46427d5dc18SMarcel Moolenaar } 46527d5dc18SMarcel Moolenaar bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); 46627d5dc18SMarcel Moolenaar 46727d5dc18SMarcel Moolenaar if (sc->sc_class->size > sizeof(*sc)) { 46827d5dc18SMarcel Moolenaar device_set_softc(dev, NULL); 46927d5dc18SMarcel Moolenaar free(sc, M_UART); 47027d5dc18SMarcel Moolenaar } else 47127d5dc18SMarcel Moolenaar device_set_softc(dev, NULL); 47227d5dc18SMarcel Moolenaar 47327d5dc18SMarcel Moolenaar return (0); 47427d5dc18SMarcel Moolenaar } 475