1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2015-2016, Stanislav Galabov 5 * Copyright (c) 2014, Aleksandr A. Mityaev 6 * Copyright (c) 2011, Aleksandr Rybalko 7 * based on hard work 8 * by Alexander Egorenkov <[email protected]> 9 * and by Damien Bergamini <[email protected]> 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include "if_rtvar.h" 39 #include "if_rtreg.h" 40 41 #include <net/if.h> 42 #include <net/if_var.h> 43 #include <net/if_arp.h> 44 #include <net/ethernet.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_types.h> 48 #include <net/if_vlan_var.h> 49 50 #include <net/bpf.h> 51 52 #include <machine/bus.h> 53 #include <machine/cache.h> 54 #include <machine/cpufunc.h> 55 #include <machine/resource.h> 56 #include <vm/vm_param.h> 57 #include <vm/vm.h> 58 #include <vm/pmap.h> 59 #include <machine/pmap.h> 60 #include <sys/bus.h> 61 #include <sys/rman.h> 62 63 #include "opt_platform.h" 64 #include "opt_rt305x.h" 65 66 #ifdef FDT 67 #include <dev/ofw/openfirm.h> 68 #include <dev/ofw/ofw_bus.h> 69 #include <dev/ofw/ofw_bus_subr.h> 70 #endif 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #ifdef RT_MDIO 76 #include <dev/mdio/mdio.h> 77 #include <dev/etherswitch/miiproxy.h> 78 #include "mdio_if.h" 79 #endif 80 81 #if 0 82 #include <mips/rt305x/rt305x_sysctlvar.h> 83 #include <mips/rt305x/rt305xreg.h> 84 #endif 85 86 #ifdef IF_RT_PHY_SUPPORT 87 #include "miibus_if.h" 88 #endif 89 90 /* 91 * Defines and macros 92 */ 93 #define RT_MAX_AGG_SIZE 3840 94 95 #define RT_TX_DATA_SEG0_SIZE MJUMPAGESIZE 96 97 #define RT_MS(_v, _f) (((_v) & _f) >> _f##_S) 98 #define RT_SM(_v, _f) (((_v) << _f##_S) & _f) 99 100 #define RT_TX_WATCHDOG_TIMEOUT 5 101 102 #define RT_CHIPID_RT2880 0x2880 103 #define RT_CHIPID_RT3050 0x3050 104 #define RT_CHIPID_RT3883 0x3883 105 #define RT_CHIPID_RT5350 0x5350 106 #define RT_CHIPID_MT7620 0x7620 107 #define RT_CHIPID_MT7621 0x7621 108 109 #ifdef FDT 110 /* more specific and new models should go first */ 111 static const struct ofw_compat_data rt_compat_data[] = { 112 { "ralink,rt2880-eth", RT_CHIPID_RT2880 }, 113 { "ralink,rt3050-eth", RT_CHIPID_RT3050 }, 114 { "ralink,rt3352-eth", RT_CHIPID_RT3050 }, 115 { "ralink,rt3883-eth", RT_CHIPID_RT3883 }, 116 { "ralink,rt5350-eth", RT_CHIPID_RT5350 }, 117 { "ralink,mt7620a-eth", RT_CHIPID_MT7620 }, 118 { "mediatek,mt7620-eth", RT_CHIPID_MT7620 }, 119 { "ralink,mt7621-eth", RT_CHIPID_MT7621 }, 120 { "mediatek,mt7621-eth", RT_CHIPID_MT7621 }, 121 { NULL, 0 } 122 }; 123 #endif 124 125 /* 126 * Static function prototypes 127 */ 128 static int rt_probe(device_t dev); 129 static int rt_attach(device_t dev); 130 static int rt_detach(device_t dev); 131 static int rt_shutdown(device_t dev); 132 static int rt_suspend(device_t dev); 133 static int rt_resume(device_t dev); 134 static void rt_init_locked(void *priv); 135 static void rt_init(void *priv); 136 static void rt_stop_locked(void *priv); 137 static void rt_stop(void *priv); 138 static void rt_start(struct ifnet *ifp); 139 static int rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 140 static void rt_periodic(void *arg); 141 static void rt_tx_watchdog(void *arg); 142 static void rt_intr(void *arg); 143 static void rt_rt5350_intr(void *arg); 144 static void rt_tx_coherent_intr(struct rt_softc *sc); 145 static void rt_rx_coherent_intr(struct rt_softc *sc); 146 static void rt_rx_delay_intr(struct rt_softc *sc); 147 static void rt_tx_delay_intr(struct rt_softc *sc); 148 static void rt_rx_intr(struct rt_softc *sc, int qid); 149 static void rt_tx_intr(struct rt_softc *sc, int qid); 150 static void rt_rx_done_task(void *context, int pending); 151 static void rt_tx_done_task(void *context, int pending); 152 static void rt_periodic_task(void *context, int pending); 153 static int rt_rx_eof(struct rt_softc *sc, 154 struct rt_softc_rx_ring *ring, int limit); 155 static void rt_tx_eof(struct rt_softc *sc, 156 struct rt_softc_tx_ring *ring); 157 static void rt_update_stats(struct rt_softc *sc); 158 static void rt_watchdog(struct rt_softc *sc); 159 static void rt_update_raw_counters(struct rt_softc *sc); 160 static void rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask); 161 static void rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask); 162 static int rt_txrx_enable(struct rt_softc *sc); 163 static int rt_alloc_rx_ring(struct rt_softc *sc, 164 struct rt_softc_rx_ring *ring, int qid); 165 static void rt_reset_rx_ring(struct rt_softc *sc, 166 struct rt_softc_rx_ring *ring); 167 static void rt_free_rx_ring(struct rt_softc *sc, 168 struct rt_softc_rx_ring *ring); 169 static int rt_alloc_tx_ring(struct rt_softc *sc, 170 struct rt_softc_tx_ring *ring, int qid); 171 static void rt_reset_tx_ring(struct rt_softc *sc, 172 struct rt_softc_tx_ring *ring); 173 static void rt_free_tx_ring(struct rt_softc *sc, 174 struct rt_softc_tx_ring *ring); 175 static void rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, 176 int nseg, int error); 177 static void rt_sysctl_attach(struct rt_softc *sc); 178 #ifdef IF_RT_PHY_SUPPORT 179 void rt_miibus_statchg(device_t); 180 #endif 181 #if defined(IF_RT_PHY_SUPPORT) || defined(RT_MDIO) 182 static int rt_miibus_readreg(device_t, int, int); 183 static int rt_miibus_writereg(device_t, int, int, int); 184 #endif 185 static int rt_ifmedia_upd(struct ifnet *); 186 static void rt_ifmedia_sts(struct ifnet *, struct ifmediareq *); 187 188 static SYSCTL_NODE(_hw, OID_AUTO, rt, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 189 "RT driver parameters"); 190 #ifdef IF_RT_DEBUG 191 static int rt_debug = 0; 192 SYSCTL_INT(_hw_rt, OID_AUTO, debug, CTLFLAG_RWTUN, &rt_debug, 0, 193 "RT debug level"); 194 #endif 195 196 static int 197 rt_probe(device_t dev) 198 { 199 struct rt_softc *sc = device_get_softc(dev); 200 char buf[80]; 201 #ifdef FDT 202 const struct ofw_compat_data * cd; 203 204 cd = ofw_bus_search_compatible(dev, rt_compat_data); 205 if (cd->ocd_data == 0) 206 return (ENXIO); 207 208 sc->rt_chipid = (unsigned int)(cd->ocd_data); 209 #else 210 #if defined(MT7620) 211 sc->rt_chipid = RT_CHIPID_MT7620; 212 #elif defined(MT7621) 213 sc->rt_chipid = RT_CHIPID_MT7621; 214 #elif defined(RT5350) 215 sc->rt_chipid = RT_CHIPID_RT5350; 216 #else 217 sc->rt_chipid = RT_CHIPID_RT3050; 218 #endif 219 #endif 220 snprintf(buf, sizeof(buf), "Ralink %cT%x onChip Ethernet driver", 221 sc->rt_chipid >= 0x7600 ? 'M' : 'R', sc->rt_chipid); 222 device_set_desc_copy(dev, buf); 223 return (BUS_PROBE_GENERIC); 224 } 225 226 /* 227 * macaddr_atoi - translate string MAC address to uint8_t array 228 */ 229 static int 230 macaddr_atoi(const char *str, uint8_t *mac) 231 { 232 int count, i; 233 unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */ 234 235 count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x", 236 &amac[0], &amac[1], &amac[2], 237 &amac[3], &amac[4], &amac[5]); 238 if (count < ETHER_ADDR_LEN) { 239 memset(mac, 0, ETHER_ADDR_LEN); 240 return (1); 241 } 242 243 /* Copy aligned to result */ 244 for (i = 0; i < ETHER_ADDR_LEN; i ++) 245 mac[i] = (amac[i] & 0xff); 246 247 return (0); 248 } 249 250 #ifdef USE_GENERATED_MAC_ADDRESS 251 /* 252 * generate_mac(uin8_t *mac) 253 * This is MAC address generator for cases when real device MAC address 254 * unknown or not yet accessible. 255 * Use 'b','s','d' signature and 3 octets from CRC32 on kenv. 256 * MAC = 'b', 's', 'd', CRC[3]^CRC[2], CRC[1], CRC[0] 257 * 258 * Output - MAC address, that do not change between reboots, if hints or 259 * bootloader info unchange. 260 */ 261 static void 262 generate_mac(uint8_t *mac) 263 { 264 unsigned char *cp; 265 int i = 0; 266 uint32_t crc = 0xffffffff; 267 268 /* Generate CRC32 on kenv */ 269 for (cp = kenvp[0]; cp != NULL; cp = kenvp[++i]) { 270 crc = calculate_crc32c(crc, cp, strlen(cp) + 1); 271 } 272 crc = ~crc; 273 274 mac[0] = 'b'; 275 mac[1] = 's'; 276 mac[2] = 'd'; 277 mac[3] = (crc >> 24) ^ ((crc >> 16) & 0xff); 278 mac[4] = (crc >> 8) & 0xff; 279 mac[5] = crc & 0xff; 280 } 281 #endif 282 283 /* 284 * ether_request_mac - try to find usable MAC address. 285 */ 286 static int 287 ether_request_mac(device_t dev, uint8_t *mac) 288 { 289 char *var; 290 291 /* 292 * "ethaddr" is passed via envp on RedBoot platforms 293 * "kmac" is passed via argv on RouterBOOT platforms 294 */ 295 #if defined(RT305X_UBOOT) || defined(__REDBOOT__) || defined(__ROUTERBOOT__) 296 if ((var = kern_getenv("ethaddr")) != NULL || 297 (var = kern_getenv("kmac")) != NULL ) { 298 299 if(!macaddr_atoi(var, mac)) { 300 printf("%s: use %s macaddr from KENV\n", 301 device_get_nameunit(dev), var); 302 freeenv(var); 303 return (0); 304 } 305 freeenv(var); 306 } 307 #endif 308 309 /* 310 * Try from hints 311 * hint.[dev].[unit].macaddr 312 */ 313 if (!resource_string_value(device_get_name(dev), 314 device_get_unit(dev), "macaddr", (const char **)&var)) { 315 316 if(!macaddr_atoi(var, mac)) { 317 printf("%s: use %s macaddr from hints\n", 318 device_get_nameunit(dev), var); 319 return (0); 320 } 321 } 322 323 #ifdef USE_GENERATED_MAC_ADDRESS 324 generate_mac(mac); 325 326 device_printf(dev, "use generated %02x:%02x:%02x:%02x:%02x:%02x " 327 "macaddr\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); 328 #else 329 /* Hardcoded */ 330 mac[0] = 0x00; 331 mac[1] = 0x18; 332 mac[2] = 0xe7; 333 mac[3] = 0xd5; 334 mac[4] = 0x83; 335 mac[5] = 0x90; 336 337 device_printf(dev, "use hardcoded 00:18:e7:d5:83:90 macaddr\n"); 338 #endif 339 340 return (0); 341 } 342 343 /* 344 * Reset hardware 345 */ 346 static void 347 reset_freng(struct rt_softc *sc) 348 { 349 /* XXX hard reset kills everything so skip it ... */ 350 return; 351 } 352 353 static int 354 rt_attach(device_t dev) 355 { 356 struct rt_softc *sc; 357 struct ifnet *ifp; 358 int error, i; 359 #ifdef FDT 360 phandle_t node; 361 char fdtval[32]; 362 #endif 363 364 sc = device_get_softc(dev); 365 sc->dev = dev; 366 367 #ifdef FDT 368 node = ofw_bus_get_node(sc->dev); 369 #endif 370 371 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK, 372 MTX_DEF | MTX_RECURSE); 373 374 sc->mem_rid = 0; 375 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 376 RF_ACTIVE | RF_SHAREABLE); 377 if (sc->mem == NULL) { 378 device_printf(dev, "could not allocate memory resource\n"); 379 error = ENXIO; 380 goto fail; 381 } 382 383 sc->bst = rman_get_bustag(sc->mem); 384 sc->bsh = rman_get_bushandle(sc->mem); 385 386 sc->irq_rid = 0; 387 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 388 RF_ACTIVE); 389 if (sc->irq == NULL) { 390 device_printf(dev, 391 "could not allocate interrupt resource\n"); 392 error = ENXIO; 393 goto fail; 394 } 395 396 #ifdef IF_RT_DEBUG 397 sc->debug = rt_debug; 398 399 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 400 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 401 "debug", CTLFLAG_RW, &sc->debug, 0, "rt debug level"); 402 #endif 403 404 /* Reset hardware */ 405 reset_freng(sc); 406 407 408 if (sc->rt_chipid == RT_CHIPID_MT7620) { 409 sc->csum_fail_ip = MT7620_RXD_SRC_IP_CSUM_FAIL; 410 sc->csum_fail_l4 = MT7620_RXD_SRC_L4_CSUM_FAIL; 411 } else if (sc->rt_chipid == RT_CHIPID_MT7621) { 412 sc->csum_fail_ip = MT7621_RXD_SRC_IP_CSUM_FAIL; 413 sc->csum_fail_l4 = MT7621_RXD_SRC_L4_CSUM_FAIL; 414 } else { 415 sc->csum_fail_ip = RT305X_RXD_SRC_IP_CSUM_FAIL; 416 sc->csum_fail_l4 = RT305X_RXD_SRC_L4_CSUM_FAIL; 417 } 418 419 /* Fill in soc-specific registers map */ 420 switch(sc->rt_chipid) { 421 case RT_CHIPID_MT7620: 422 case RT_CHIPID_MT7621: 423 sc->gdma1_base = MT7620_GDMA1_BASE; 424 /* fallthrough */ 425 case RT_CHIPID_RT5350: 426 device_printf(dev, "%cT%x Ethernet MAC (rev 0x%08x)\n", 427 sc->rt_chipid >= 0x7600 ? 'M' : 'R', 428 sc->rt_chipid, sc->mac_rev); 429 /* RT5350: No GDMA, PSE, CDMA, PPE */ 430 RT_WRITE(sc, GE_PORT_BASE + 0x0C00, // UDPCS, TCPCS, IPCS=1 431 RT_READ(sc, GE_PORT_BASE + 0x0C00) | (0x7<<16)); 432 sc->delay_int_cfg=RT5350_PDMA_BASE+RT5350_DELAY_INT_CFG; 433 sc->fe_int_status=RT5350_FE_INT_STATUS; 434 sc->fe_int_enable=RT5350_FE_INT_ENABLE; 435 sc->pdma_glo_cfg=RT5350_PDMA_BASE+RT5350_PDMA_GLO_CFG; 436 sc->pdma_rst_idx=RT5350_PDMA_BASE+RT5350_PDMA_RST_IDX; 437 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { 438 sc->tx_base_ptr[i]=RT5350_PDMA_BASE+RT5350_TX_BASE_PTR(i); 439 sc->tx_max_cnt[i]=RT5350_PDMA_BASE+RT5350_TX_MAX_CNT(i); 440 sc->tx_ctx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_CTX_IDX(i); 441 sc->tx_dtx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_DTX_IDX(i); 442 } 443 sc->rx_ring_count=2; 444 sc->rx_base_ptr[0]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR0; 445 sc->rx_max_cnt[0]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT0; 446 sc->rx_calc_idx[0]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX0; 447 sc->rx_drx_idx[0]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX0; 448 sc->rx_base_ptr[1]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR1; 449 sc->rx_max_cnt[1]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT1; 450 sc->rx_calc_idx[1]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX1; 451 sc->rx_drx_idx[1]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX1; 452 sc->int_rx_done_mask=RT5350_INT_RXQ0_DONE; 453 sc->int_tx_done_mask=RT5350_INT_TXQ0_DONE; 454 break; 455 default: 456 device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n", 457 sc->mac_rev); 458 sc->gdma1_base = GDMA1_BASE; 459 sc->delay_int_cfg=PDMA_BASE+DELAY_INT_CFG; 460 sc->fe_int_status=GE_PORT_BASE+FE_INT_STATUS; 461 sc->fe_int_enable=GE_PORT_BASE+FE_INT_ENABLE; 462 sc->pdma_glo_cfg=PDMA_BASE+PDMA_GLO_CFG; 463 sc->pdma_rst_idx=PDMA_BASE+PDMA_RST_IDX; 464 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { 465 sc->tx_base_ptr[i]=PDMA_BASE+TX_BASE_PTR(i); 466 sc->tx_max_cnt[i]=PDMA_BASE+TX_MAX_CNT(i); 467 sc->tx_ctx_idx[i]=PDMA_BASE+TX_CTX_IDX(i); 468 sc->tx_dtx_idx[i]=PDMA_BASE+TX_DTX_IDX(i); 469 } 470 sc->rx_ring_count=1; 471 sc->rx_base_ptr[0]=PDMA_BASE+RX_BASE_PTR0; 472 sc->rx_max_cnt[0]=PDMA_BASE+RX_MAX_CNT0; 473 sc->rx_calc_idx[0]=PDMA_BASE+RX_CALC_IDX0; 474 sc->rx_drx_idx[0]=PDMA_BASE+RX_DRX_IDX0; 475 sc->int_rx_done_mask=INT_RX_DONE; 476 sc->int_tx_done_mask=INT_TXQ0_DONE; 477 } 478 479 if (sc->gdma1_base != 0) 480 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG, 481 ( 482 GDM_ICS_EN | /* Enable IP Csum */ 483 GDM_TCS_EN | /* Enable TCP Csum */ 484 GDM_UCS_EN | /* Enable UDP Csum */ 485 GDM_STRPCRC | /* Strip CRC from packet */ 486 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */ 487 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */ 488 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */ 489 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */ 490 )); 491 492 #ifdef FDT 493 if (sc->rt_chipid == RT_CHIPID_RT2880 || 494 sc->rt_chipid == RT_CHIPID_RT3883) { 495 if (OF_getprop(node, "port-mode", fdtval, sizeof(fdtval)) > 0 && 496 strcmp(fdtval, "gigasw") == 0) 497 RT_WRITE(sc, MDIO_CFG, MDIO_2880_GIGA_INIT); 498 else 499 RT_WRITE(sc, MDIO_CFG, MDIO_2880_100T_INIT); 500 } 501 #endif 502 503 /* allocate Tx and Rx rings */ 504 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { 505 error = rt_alloc_tx_ring(sc, &sc->tx_ring[i], i); 506 if (error != 0) { 507 device_printf(dev, "could not allocate Tx ring #%d\n", 508 i); 509 goto fail; 510 } 511 } 512 513 sc->tx_ring_mgtqid = 5; 514 for (i = 0; i < sc->rx_ring_count; i++) { 515 error = rt_alloc_rx_ring(sc, &sc->rx_ring[i], i); 516 if (error != 0) { 517 device_printf(dev, "could not allocate Rx ring\n"); 518 goto fail; 519 } 520 } 521 522 callout_init(&sc->periodic_ch, 0); 523 callout_init_mtx(&sc->tx_watchdog_ch, &sc->lock, 0); 524 525 ifp = sc->ifp = if_alloc(IFT_ETHER); 526 if (ifp == NULL) { 527 device_printf(dev, "could not if_alloc()\n"); 528 error = ENOMEM; 529 goto fail; 530 } 531 532 ifp->if_softc = sc; 533 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 534 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 535 ifp->if_init = rt_init; 536 ifp->if_ioctl = rt_ioctl; 537 ifp->if_start = rt_start; 538 #define RT_TX_QLEN 256 539 540 IFQ_SET_MAXLEN(&ifp->if_snd, RT_TX_QLEN); 541 ifp->if_snd.ifq_drv_maxlen = RT_TX_QLEN; 542 IFQ_SET_READY(&ifp->if_snd); 543 544 #ifdef IF_RT_PHY_SUPPORT 545 error = mii_attach(dev, &sc->rt_miibus, ifp, rt_ifmedia_upd, 546 rt_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 547 if (error != 0) { 548 device_printf(dev, "attaching PHYs failed\n"); 549 error = ENXIO; 550 goto fail; 551 } 552 #else 553 ifmedia_init(&sc->rt_ifmedia, 0, rt_ifmedia_upd, rt_ifmedia_sts); 554 ifmedia_add(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, 555 NULL); 556 ifmedia_set(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX); 557 558 #endif /* IF_RT_PHY_SUPPORT */ 559 560 ether_request_mac(dev, sc->mac_addr); 561 ether_ifattach(ifp, sc->mac_addr); 562 563 /* 564 * Tell the upper layer(s) we support long frames. 565 */ 566 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 567 ifp->if_capabilities |= IFCAP_VLAN_MTU; 568 ifp->if_capenable |= IFCAP_VLAN_MTU; 569 ifp->if_capabilities |= IFCAP_RXCSUM|IFCAP_TXCSUM; 570 ifp->if_capenable |= IFCAP_RXCSUM|IFCAP_TXCSUM; 571 572 /* init task queue */ 573 NET_TASK_INIT(&sc->rx_done_task, 0, rt_rx_done_task, sc); 574 TASK_INIT(&sc->tx_done_task, 0, rt_tx_done_task, sc); 575 TASK_INIT(&sc->periodic_task, 0, rt_periodic_task, sc); 576 577 sc->rx_process_limit = 100; 578 579 sc->taskqueue = taskqueue_create("rt_taskq", M_NOWAIT, 580 taskqueue_thread_enqueue, &sc->taskqueue); 581 582 taskqueue_start_threads(&sc->taskqueue, 1, PI_NET, "%s taskq", 583 device_get_nameunit(sc->dev)); 584 585 rt_sysctl_attach(sc); 586 587 /* set up interrupt */ 588 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 589 NULL, (sc->rt_chipid == RT_CHIPID_RT5350 || 590 sc->rt_chipid == RT_CHIPID_MT7620 || 591 sc->rt_chipid == RT_CHIPID_MT7621) ? rt_rt5350_intr : rt_intr, 592 sc, &sc->irqh); 593 if (error != 0) { 594 printf("%s: could not set up interrupt\n", 595 device_get_nameunit(dev)); 596 goto fail; 597 } 598 #ifdef IF_RT_DEBUG 599 device_printf(dev, "debug var at %#08x\n", (u_int)&(sc->debug)); 600 #endif 601 602 return (0); 603 604 fail: 605 /* free Tx and Rx rings */ 606 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) 607 rt_free_tx_ring(sc, &sc->tx_ring[i]); 608 609 for (i = 0; i < sc->rx_ring_count; i++) 610 rt_free_rx_ring(sc, &sc->rx_ring[i]); 611 612 mtx_destroy(&sc->lock); 613 614 if (sc->mem != NULL) 615 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, 616 sc->mem); 617 618 if (sc->irq != NULL) 619 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 620 sc->irq); 621 622 return (error); 623 } 624 625 /* 626 * Set media options. 627 */ 628 static int 629 rt_ifmedia_upd(struct ifnet *ifp) 630 { 631 struct rt_softc *sc; 632 #ifdef IF_RT_PHY_SUPPORT 633 struct mii_data *mii; 634 struct mii_softc *miisc; 635 int error = 0; 636 637 sc = ifp->if_softc; 638 RT_SOFTC_LOCK(sc); 639 640 mii = device_get_softc(sc->rt_miibus); 641 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 642 PHY_RESET(miisc); 643 error = mii_mediachg(mii); 644 RT_SOFTC_UNLOCK(sc); 645 646 return (error); 647 648 #else /* !IF_RT_PHY_SUPPORT */ 649 650 struct ifmedia *ifm; 651 struct ifmedia_entry *ife; 652 653 sc = ifp->if_softc; 654 ifm = &sc->rt_ifmedia; 655 ife = ifm->ifm_cur; 656 657 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 658 return (EINVAL); 659 660 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 661 device_printf(sc->dev, 662 "AUTO is not supported for multiphy MAC"); 663 return (EINVAL); 664 } 665 666 /* 667 * Ignore everything 668 */ 669 return (0); 670 #endif /* IF_RT_PHY_SUPPORT */ 671 } 672 673 /* 674 * Report current media status. 675 */ 676 static void 677 rt_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 678 { 679 #ifdef IF_RT_PHY_SUPPORT 680 struct rt_softc *sc; 681 struct mii_data *mii; 682 683 sc = ifp->if_softc; 684 685 RT_SOFTC_LOCK(sc); 686 mii = device_get_softc(sc->rt_miibus); 687 mii_pollstat(mii); 688 ifmr->ifm_active = mii->mii_media_active; 689 ifmr->ifm_status = mii->mii_media_status; 690 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 691 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 692 RT_SOFTC_UNLOCK(sc); 693 #else /* !IF_RT_PHY_SUPPORT */ 694 695 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 696 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 697 #endif /* IF_RT_PHY_SUPPORT */ 698 } 699 700 static int 701 rt_detach(device_t dev) 702 { 703 struct rt_softc *sc; 704 struct ifnet *ifp; 705 int i; 706 707 sc = device_get_softc(dev); 708 ifp = sc->ifp; 709 710 RT_DPRINTF(sc, RT_DEBUG_ANY, "detaching\n"); 711 712 RT_SOFTC_LOCK(sc); 713 714 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 715 716 callout_stop(&sc->periodic_ch); 717 callout_stop(&sc->tx_watchdog_ch); 718 719 taskqueue_drain(sc->taskqueue, &sc->rx_done_task); 720 taskqueue_drain(sc->taskqueue, &sc->tx_done_task); 721 taskqueue_drain(sc->taskqueue, &sc->periodic_task); 722 723 /* free Tx and Rx rings */ 724 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) 725 rt_free_tx_ring(sc, &sc->tx_ring[i]); 726 for (i = 0; i < sc->rx_ring_count; i++) 727 rt_free_rx_ring(sc, &sc->rx_ring[i]); 728 729 RT_SOFTC_UNLOCK(sc); 730 731 #ifdef IF_RT_PHY_SUPPORT 732 if (sc->rt_miibus != NULL) 733 device_delete_child(dev, sc->rt_miibus); 734 #endif 735 736 ether_ifdetach(ifp); 737 if_free(ifp); 738 739 taskqueue_free(sc->taskqueue); 740 741 mtx_destroy(&sc->lock); 742 743 bus_generic_detach(dev); 744 bus_teardown_intr(dev, sc->irq, sc->irqh); 745 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 746 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 747 748 return (0); 749 } 750 751 static int 752 rt_shutdown(device_t dev) 753 { 754 struct rt_softc *sc; 755 756 sc = device_get_softc(dev); 757 RT_DPRINTF(sc, RT_DEBUG_ANY, "shutting down\n"); 758 rt_stop(sc); 759 760 return (0); 761 } 762 763 static int 764 rt_suspend(device_t dev) 765 { 766 struct rt_softc *sc; 767 768 sc = device_get_softc(dev); 769 RT_DPRINTF(sc, RT_DEBUG_ANY, "suspending\n"); 770 rt_stop(sc); 771 772 return (0); 773 } 774 775 static int 776 rt_resume(device_t dev) 777 { 778 struct rt_softc *sc; 779 struct ifnet *ifp; 780 781 sc = device_get_softc(dev); 782 ifp = sc->ifp; 783 784 RT_DPRINTF(sc, RT_DEBUG_ANY, "resuming\n"); 785 786 if (ifp->if_flags & IFF_UP) 787 rt_init(sc); 788 789 return (0); 790 } 791 792 /* 793 * rt_init_locked - Run initialization process having locked mtx. 794 */ 795 static void 796 rt_init_locked(void *priv) 797 { 798 struct rt_softc *sc; 799 struct ifnet *ifp; 800 #ifdef IF_RT_PHY_SUPPORT 801 struct mii_data *mii; 802 #endif 803 int i, ntries; 804 uint32_t tmp; 805 806 sc = priv; 807 ifp = sc->ifp; 808 #ifdef IF_RT_PHY_SUPPORT 809 mii = device_get_softc(sc->rt_miibus); 810 #endif 811 812 RT_DPRINTF(sc, RT_DEBUG_ANY, "initializing\n"); 813 814 RT_SOFTC_ASSERT_LOCKED(sc); 815 816 /* hardware reset */ 817 //RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET); 818 //rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG); 819 820 /* Fwd to CPU (uni|broad|multi)cast and Unknown */ 821 if (sc->gdma1_base != 0) 822 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG, 823 ( 824 GDM_ICS_EN | /* Enable IP Csum */ 825 GDM_TCS_EN | /* Enable TCP Csum */ 826 GDM_UCS_EN | /* Enable UDP Csum */ 827 GDM_STRPCRC | /* Strip CRC from packet */ 828 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */ 829 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */ 830 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */ 831 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */ 832 )); 833 834 /* disable DMA engine */ 835 RT_WRITE(sc, sc->pdma_glo_cfg, 0); 836 RT_WRITE(sc, sc->pdma_rst_idx, 0xffffffff); 837 838 /* wait while DMA engine is busy */ 839 for (ntries = 0; ntries < 100; ntries++) { 840 tmp = RT_READ(sc, sc->pdma_glo_cfg); 841 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY))) 842 break; 843 DELAY(1000); 844 } 845 846 if (ntries == 100) { 847 device_printf(sc->dev, "timeout waiting for DMA engine\n"); 848 goto fail; 849 } 850 851 /* reset Rx and Tx rings */ 852 tmp = FE_RST_DRX_IDX0 | 853 FE_RST_DTX_IDX3 | 854 FE_RST_DTX_IDX2 | 855 FE_RST_DTX_IDX1 | 856 FE_RST_DTX_IDX0; 857 858 RT_WRITE(sc, sc->pdma_rst_idx, tmp); 859 860 /* XXX switch set mac address */ 861 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) 862 rt_reset_tx_ring(sc, &sc->tx_ring[i]); 863 864 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { 865 /* update TX_BASE_PTRx */ 866 RT_WRITE(sc, sc->tx_base_ptr[i], 867 sc->tx_ring[i].desc_phys_addr); 868 RT_WRITE(sc, sc->tx_max_cnt[i], 869 RT_SOFTC_TX_RING_DESC_COUNT); 870 RT_WRITE(sc, sc->tx_ctx_idx[i], 0); 871 } 872 873 /* init Rx ring */ 874 for (i = 0; i < sc->rx_ring_count; i++) 875 rt_reset_rx_ring(sc, &sc->rx_ring[i]); 876 877 /* update RX_BASE_PTRx */ 878 for (i = 0; i < sc->rx_ring_count; i++) { 879 RT_WRITE(sc, sc->rx_base_ptr[i], 880 sc->rx_ring[i].desc_phys_addr); 881 RT_WRITE(sc, sc->rx_max_cnt[i], 882 RT_SOFTC_RX_RING_DATA_COUNT); 883 RT_WRITE(sc, sc->rx_calc_idx[i], 884 RT_SOFTC_RX_RING_DATA_COUNT - 1); 885 } 886 887 /* write back DDONE, 16byte burst enable RX/TX DMA */ 888 tmp = FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN; 889 if (sc->rt_chipid == RT_CHIPID_MT7620 || 890 sc->rt_chipid == RT_CHIPID_MT7621) 891 tmp |= (1<<31); 892 RT_WRITE(sc, sc->pdma_glo_cfg, tmp); 893 894 /* disable interrupts mitigation */ 895 RT_WRITE(sc, sc->delay_int_cfg, 0); 896 897 /* clear pending interrupts */ 898 RT_WRITE(sc, sc->fe_int_status, 0xffffffff); 899 900 /* enable interrupts */ 901 if (sc->rt_chipid == RT_CHIPID_RT5350 || 902 sc->rt_chipid == RT_CHIPID_MT7620 || 903 sc->rt_chipid == RT_CHIPID_MT7621) 904 tmp = RT5350_INT_TX_COHERENT | 905 RT5350_INT_RX_COHERENT | 906 RT5350_INT_TXQ3_DONE | 907 RT5350_INT_TXQ2_DONE | 908 RT5350_INT_TXQ1_DONE | 909 RT5350_INT_TXQ0_DONE | 910 RT5350_INT_RXQ1_DONE | 911 RT5350_INT_RXQ0_DONE; 912 else 913 tmp = CNT_PPE_AF | 914 CNT_GDM_AF | 915 PSE_P2_FC | 916 GDM_CRC_DROP | 917 PSE_BUF_DROP | 918 GDM_OTHER_DROP | 919 PSE_P1_FC | 920 PSE_P0_FC | 921 PSE_FQ_EMPTY | 922 INT_TX_COHERENT | 923 INT_RX_COHERENT | 924 INT_TXQ3_DONE | 925 INT_TXQ2_DONE | 926 INT_TXQ1_DONE | 927 INT_TXQ0_DONE | 928 INT_RX_DONE; 929 930 sc->intr_enable_mask = tmp; 931 932 RT_WRITE(sc, sc->fe_int_enable, tmp); 933 934 if (rt_txrx_enable(sc) != 0) 935 goto fail; 936 937 #ifdef IF_RT_PHY_SUPPORT 938 if (mii) mii_mediachg(mii); 939 #endif /* IF_RT_PHY_SUPPORT */ 940 941 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 942 ifp->if_drv_flags |= IFF_DRV_RUNNING; 943 944 sc->periodic_round = 0; 945 946 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc); 947 948 return; 949 950 fail: 951 rt_stop_locked(sc); 952 } 953 954 /* 955 * rt_init - lock and initialize device. 956 */ 957 static void 958 rt_init(void *priv) 959 { 960 struct rt_softc *sc; 961 962 sc = priv; 963 RT_SOFTC_LOCK(sc); 964 rt_init_locked(sc); 965 RT_SOFTC_UNLOCK(sc); 966 } 967 968 /* 969 * rt_stop_locked - stop TX/RX w/ lock 970 */ 971 static void 972 rt_stop_locked(void *priv) 973 { 974 struct rt_softc *sc; 975 struct ifnet *ifp; 976 977 sc = priv; 978 ifp = sc->ifp; 979 980 RT_DPRINTF(sc, RT_DEBUG_ANY, "stopping\n"); 981 982 RT_SOFTC_ASSERT_LOCKED(sc); 983 sc->tx_timer = 0; 984 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 985 callout_stop(&sc->periodic_ch); 986 callout_stop(&sc->tx_watchdog_ch); 987 RT_SOFTC_UNLOCK(sc); 988 taskqueue_block(sc->taskqueue); 989 990 /* 991 * Sometime rt_stop_locked called from isr and we get panic 992 * When found, I fix it 993 */ 994 #ifdef notyet 995 taskqueue_drain(sc->taskqueue, &sc->rx_done_task); 996 taskqueue_drain(sc->taskqueue, &sc->tx_done_task); 997 taskqueue_drain(sc->taskqueue, &sc->periodic_task); 998 #endif 999 RT_SOFTC_LOCK(sc); 1000 1001 /* disable interrupts */ 1002 RT_WRITE(sc, sc->fe_int_enable, 0); 1003 1004 if(sc->rt_chipid != RT_CHIPID_RT5350 && 1005 sc->rt_chipid != RT_CHIPID_MT7620 && 1006 sc->rt_chipid != RT_CHIPID_MT7621) { 1007 /* reset adapter */ 1008 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET); 1009 } 1010 1011 if (sc->gdma1_base != 0) 1012 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG, 1013 ( 1014 GDM_ICS_EN | /* Enable IP Csum */ 1015 GDM_TCS_EN | /* Enable TCP Csum */ 1016 GDM_UCS_EN | /* Enable UDP Csum */ 1017 GDM_STRPCRC | /* Strip CRC from packet */ 1018 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */ 1019 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */ 1020 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */ 1021 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */ 1022 )); 1023 } 1024 1025 static void 1026 rt_stop(void *priv) 1027 { 1028 struct rt_softc *sc; 1029 1030 sc = priv; 1031 RT_SOFTC_LOCK(sc); 1032 rt_stop_locked(sc); 1033 RT_SOFTC_UNLOCK(sc); 1034 } 1035 1036 /* 1037 * rt_tx_data - transmit packet. 1038 */ 1039 static int 1040 rt_tx_data(struct rt_softc *sc, struct mbuf *m, int qid) 1041 { 1042 struct ifnet *ifp; 1043 struct rt_softc_tx_ring *ring; 1044 struct rt_softc_tx_data *data; 1045 struct rt_txdesc *desc; 1046 struct mbuf *m_d; 1047 bus_dma_segment_t dma_seg[RT_SOFTC_MAX_SCATTER]; 1048 int error, ndmasegs, ndescs, i; 1049 1050 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT, 1051 ("%s: Tx data: invalid qid=%d\n", 1052 device_get_nameunit(sc->dev), qid)); 1053 1054 RT_SOFTC_TX_RING_ASSERT_LOCKED(&sc->tx_ring[qid]); 1055 1056 ifp = sc->ifp; 1057 ring = &sc->tx_ring[qid]; 1058 desc = &ring->desc[ring->desc_cur]; 1059 data = &ring->data[ring->data_cur]; 1060 1061 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m, 1062 dma_seg, &ndmasegs, 0); 1063 if (error != 0) { 1064 /* too many fragments, linearize */ 1065 1066 RT_DPRINTF(sc, RT_DEBUG_TX, 1067 "could not load mbuf DMA map, trying to linearize " 1068 "mbuf: ndmasegs=%d, len=%d, error=%d\n", 1069 ndmasegs, m->m_pkthdr.len, error); 1070 1071 m_d = m_collapse(m, M_NOWAIT, 16); 1072 if (m_d == NULL) { 1073 m_freem(m); 1074 m = NULL; 1075 return (ENOMEM); 1076 } 1077 m = m_d; 1078 1079 sc->tx_defrag_packets++; 1080 1081 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, 1082 data->dma_map, m, dma_seg, &ndmasegs, 0); 1083 if (error != 0) { 1084 device_printf(sc->dev, "could not load mbuf DMA map: " 1085 "ndmasegs=%d, len=%d, error=%d\n", 1086 ndmasegs, m->m_pkthdr.len, error); 1087 m_freem(m); 1088 return (error); 1089 } 1090 } 1091 1092 if (m->m_pkthdr.len == 0) 1093 ndmasegs = 0; 1094 1095 /* determine how many Tx descs are required */ 1096 ndescs = 1 + ndmasegs / 2; 1097 if ((ring->desc_queued + ndescs) > 1098 (RT_SOFTC_TX_RING_DESC_COUNT - 2)) { 1099 RT_DPRINTF(sc, RT_DEBUG_TX, 1100 "there are not enough Tx descs\n"); 1101 1102 sc->no_tx_desc_avail++; 1103 1104 bus_dmamap_unload(ring->data_dma_tag, data->dma_map); 1105 m_freem(m); 1106 return (EFBIG); 1107 } 1108 1109 data->m = m; 1110 1111 /* set up Tx descs */ 1112 for (i = 0; i < ndmasegs; i += 2) { 1113 1114 /* TODO: this needs to be refined as MT7620 for example has 1115 * a different word3 layout than RT305x and RT5350 (the last 1116 * one doesn't use word3 at all). And so does MT7621... 1117 */ 1118 1119 if (sc->rt_chipid != RT_CHIPID_MT7621) { 1120 /* Set destination */ 1121 if (sc->rt_chipid != RT_CHIPID_MT7620) 1122 desc->dst = (TXDSCR_DST_PORT_GDMA1); 1123 1124 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1125 desc->dst |= (TXDSCR_IP_CSUM_GEN | 1126 TXDSCR_UDP_CSUM_GEN | TXDSCR_TCP_CSUM_GEN); 1127 /* Set queue id */ 1128 desc->qn = qid; 1129 /* No PPPoE */ 1130 desc->pppoe = 0; 1131 /* No VLAN */ 1132 desc->vid = 0; 1133 } else { 1134 desc->vid = 0; 1135 desc->pppoe = 0; 1136 desc->qn = 0; 1137 desc->dst = 2; 1138 } 1139 1140 desc->sdp0 = htole32(dma_seg[i].ds_addr); 1141 desc->sdl0 = htole16(dma_seg[i].ds_len | 1142 ( ((i+1) == ndmasegs )?RT_TXDESC_SDL0_LASTSEG:0 )); 1143 1144 if ((i+1) < ndmasegs) { 1145 desc->sdp1 = htole32(dma_seg[i+1].ds_addr); 1146 desc->sdl1 = htole16(dma_seg[i+1].ds_len | 1147 ( ((i+2) == ndmasegs )?RT_TXDESC_SDL1_LASTSEG:0 )); 1148 } else { 1149 desc->sdp1 = 0; 1150 desc->sdl1 = 0; 1151 } 1152 1153 if ((i+2) < ndmasegs) { 1154 ring->desc_queued++; 1155 ring->desc_cur = (ring->desc_cur + 1) % 1156 RT_SOFTC_TX_RING_DESC_COUNT; 1157 } 1158 desc = &ring->desc[ring->desc_cur]; 1159 } 1160 1161 RT_DPRINTF(sc, RT_DEBUG_TX, "sending data: len=%d, ndmasegs=%d, " 1162 "DMA ds_len=%d/%d/%d/%d/%d\n", 1163 m->m_pkthdr.len, ndmasegs, 1164 (int) dma_seg[0].ds_len, 1165 (int) dma_seg[1].ds_len, 1166 (int) dma_seg[2].ds_len, 1167 (int) dma_seg[3].ds_len, 1168 (int) dma_seg[4].ds_len); 1169 1170 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, 1171 BUS_DMASYNC_PREWRITE); 1172 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 1173 BUS_DMASYNC_PREWRITE); 1174 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 1175 BUS_DMASYNC_PREWRITE); 1176 1177 ring->desc_queued++; 1178 ring->desc_cur = (ring->desc_cur + 1) % RT_SOFTC_TX_RING_DESC_COUNT; 1179 1180 ring->data_queued++; 1181 ring->data_cur = (ring->data_cur + 1) % RT_SOFTC_TX_RING_DATA_COUNT; 1182 1183 /* kick Tx */ 1184 RT_WRITE(sc, sc->tx_ctx_idx[qid], ring->desc_cur); 1185 1186 return (0); 1187 } 1188 1189 /* 1190 * rt_start - start Transmit/Receive 1191 */ 1192 static void 1193 rt_start(struct ifnet *ifp) 1194 { 1195 struct rt_softc *sc; 1196 struct mbuf *m; 1197 int qid = 0 /* XXX must check QoS priority */; 1198 1199 sc = ifp->if_softc; 1200 1201 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1202 return; 1203 1204 for (;;) { 1205 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1206 if (m == NULL) 1207 break; 1208 1209 m->m_pkthdr.rcvif = NULL; 1210 1211 RT_SOFTC_TX_RING_LOCK(&sc->tx_ring[qid]); 1212 1213 if (sc->tx_ring[qid].data_queued >= 1214 RT_SOFTC_TX_RING_DATA_COUNT) { 1215 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]); 1216 1217 RT_DPRINTF(sc, RT_DEBUG_TX, 1218 "if_start: Tx ring with qid=%d is full\n", qid); 1219 1220 m_freem(m); 1221 1222 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1223 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1224 1225 sc->tx_data_queue_full[qid]++; 1226 1227 break; 1228 } 1229 1230 if (rt_tx_data(sc, m, qid) != 0) { 1231 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]); 1232 1233 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1234 1235 break; 1236 } 1237 1238 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]); 1239 sc->tx_timer = RT_TX_WATCHDOG_TIMEOUT; 1240 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc); 1241 } 1242 } 1243 1244 /* 1245 * rt_update_promisc - set/clear promiscuous mode. Unused yet, because 1246 * filtering done by attached Ethernet switch. 1247 */ 1248 static void 1249 rt_update_promisc(struct ifnet *ifp) 1250 { 1251 struct rt_softc *sc; 1252 1253 sc = ifp->if_softc; 1254 printf("%s: %s promiscuous mode\n", 1255 device_get_nameunit(sc->dev), 1256 (ifp->if_flags & IFF_PROMISC) ? "entering" : "leaving"); 1257 } 1258 1259 /* 1260 * rt_ioctl - ioctl handler. 1261 */ 1262 static int 1263 rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1264 { 1265 struct rt_softc *sc; 1266 struct ifreq *ifr; 1267 #ifdef IF_RT_PHY_SUPPORT 1268 struct mii_data *mii; 1269 #endif /* IF_RT_PHY_SUPPORT */ 1270 int error, startall; 1271 1272 sc = ifp->if_softc; 1273 ifr = (struct ifreq *) data; 1274 1275 error = 0; 1276 1277 switch (cmd) { 1278 case SIOCSIFFLAGS: 1279 startall = 0; 1280 RT_SOFTC_LOCK(sc); 1281 if (ifp->if_flags & IFF_UP) { 1282 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1283 if ((ifp->if_flags ^ sc->if_flags) & 1284 IFF_PROMISC) 1285 rt_update_promisc(ifp); 1286 } else { 1287 rt_init_locked(sc); 1288 startall = 1; 1289 } 1290 } else { 1291 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1292 rt_stop_locked(sc); 1293 } 1294 sc->if_flags = ifp->if_flags; 1295 RT_SOFTC_UNLOCK(sc); 1296 break; 1297 case SIOCGIFMEDIA: 1298 case SIOCSIFMEDIA: 1299 #ifdef IF_RT_PHY_SUPPORT 1300 mii = device_get_softc(sc->rt_miibus); 1301 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1302 #else 1303 error = ifmedia_ioctl(ifp, ifr, &sc->rt_ifmedia, cmd); 1304 #endif /* IF_RT_PHY_SUPPORT */ 1305 break; 1306 default: 1307 error = ether_ioctl(ifp, cmd, data); 1308 break; 1309 } 1310 return (error); 1311 } 1312 1313 /* 1314 * rt_periodic - Handler of PERIODIC interrupt 1315 */ 1316 static void 1317 rt_periodic(void *arg) 1318 { 1319 struct rt_softc *sc; 1320 1321 sc = arg; 1322 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic\n"); 1323 taskqueue_enqueue(sc->taskqueue, &sc->periodic_task); 1324 } 1325 1326 /* 1327 * rt_tx_watchdog - Handler of TX Watchdog 1328 */ 1329 static void 1330 rt_tx_watchdog(void *arg) 1331 { 1332 struct rt_softc *sc; 1333 struct ifnet *ifp; 1334 1335 sc = arg; 1336 ifp = sc->ifp; 1337 1338 if (sc->tx_timer == 0) 1339 return; 1340 1341 if (--sc->tx_timer == 0) { 1342 device_printf(sc->dev, "Tx watchdog timeout: resetting\n"); 1343 #ifdef notyet 1344 /* 1345 * XXX: Commented out, because reset break input. 1346 */ 1347 rt_stop_locked(sc); 1348 rt_init_locked(sc); 1349 #endif 1350 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1351 sc->tx_watchdog_timeouts++; 1352 } 1353 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc); 1354 } 1355 1356 /* 1357 * rt_cnt_ppe_af - Handler of PPE Counter Table Almost Full interrupt 1358 */ 1359 static void 1360 rt_cnt_ppe_af(struct rt_softc *sc) 1361 { 1362 1363 RT_DPRINTF(sc, RT_DEBUG_INTR, "PPE Counter Table Almost Full\n"); 1364 } 1365 1366 /* 1367 * rt_cnt_gdm_af - Handler of GDMA 1 & 2 Counter Table Almost Full interrupt 1368 */ 1369 static void 1370 rt_cnt_gdm_af(struct rt_softc *sc) 1371 { 1372 1373 RT_DPRINTF(sc, RT_DEBUG_INTR, 1374 "GDMA 1 & 2 Counter Table Almost Full\n"); 1375 } 1376 1377 /* 1378 * rt_pse_p2_fc - Handler of PSE port2 (GDMA 2) flow control interrupt 1379 */ 1380 static void 1381 rt_pse_p2_fc(struct rt_softc *sc) 1382 { 1383 1384 RT_DPRINTF(sc, RT_DEBUG_INTR, 1385 "PSE port2 (GDMA 2) flow control asserted.\n"); 1386 } 1387 1388 /* 1389 * rt_gdm_crc_drop - Handler of GDMA 1/2 discard a packet due to CRC error 1390 * interrupt 1391 */ 1392 static void 1393 rt_gdm_crc_drop(struct rt_softc *sc) 1394 { 1395 1396 RT_DPRINTF(sc, RT_DEBUG_INTR, 1397 "GDMA 1 & 2 discard a packet due to CRC error\n"); 1398 } 1399 1400 /* 1401 * rt_pse_buf_drop - Handler of buffer sharing limitation interrupt 1402 */ 1403 static void 1404 rt_pse_buf_drop(struct rt_softc *sc) 1405 { 1406 1407 RT_DPRINTF(sc, RT_DEBUG_INTR, 1408 "PSE discards a packet due to buffer sharing limitation\n"); 1409 } 1410 1411 /* 1412 * rt_gdm_other_drop - Handler of discard on other reason interrupt 1413 */ 1414 static void 1415 rt_gdm_other_drop(struct rt_softc *sc) 1416 { 1417 1418 RT_DPRINTF(sc, RT_DEBUG_INTR, 1419 "GDMA 1 & 2 discard a packet due to other reason\n"); 1420 } 1421 1422 /* 1423 * rt_pse_p1_fc - Handler of PSE port1 (GDMA 1) flow control interrupt 1424 */ 1425 static void 1426 rt_pse_p1_fc(struct rt_softc *sc) 1427 { 1428 1429 RT_DPRINTF(sc, RT_DEBUG_INTR, 1430 "PSE port1 (GDMA 1) flow control asserted.\n"); 1431 } 1432 1433 /* 1434 * rt_pse_p0_fc - Handler of PSE port0 (CDMA) flow control interrupt 1435 */ 1436 static void 1437 rt_pse_p0_fc(struct rt_softc *sc) 1438 { 1439 1440 RT_DPRINTF(sc, RT_DEBUG_INTR, 1441 "PSE port0 (CDMA) flow control asserted.\n"); 1442 } 1443 1444 /* 1445 * rt_pse_fq_empty - Handler of PSE free Q empty threshold reached interrupt 1446 */ 1447 static void 1448 rt_pse_fq_empty(struct rt_softc *sc) 1449 { 1450 1451 RT_DPRINTF(sc, RT_DEBUG_INTR, 1452 "PSE free Q empty threshold reached & forced drop " 1453 "condition occurred.\n"); 1454 } 1455 1456 /* 1457 * rt_intr - main ISR 1458 */ 1459 static void 1460 rt_intr(void *arg) 1461 { 1462 struct rt_softc *sc; 1463 struct ifnet *ifp; 1464 uint32_t status; 1465 1466 sc = arg; 1467 ifp = sc->ifp; 1468 1469 /* acknowledge interrupts */ 1470 status = RT_READ(sc, sc->fe_int_status); 1471 RT_WRITE(sc, sc->fe_int_status, status); 1472 1473 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status); 1474 1475 if (status == 0xffffffff || /* device likely went away */ 1476 status == 0) /* not for us */ 1477 return; 1478 1479 sc->interrupts++; 1480 1481 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1482 return; 1483 1484 if (status & CNT_PPE_AF) 1485 rt_cnt_ppe_af(sc); 1486 1487 if (status & CNT_GDM_AF) 1488 rt_cnt_gdm_af(sc); 1489 1490 if (status & PSE_P2_FC) 1491 rt_pse_p2_fc(sc); 1492 1493 if (status & GDM_CRC_DROP) 1494 rt_gdm_crc_drop(sc); 1495 1496 if (status & PSE_BUF_DROP) 1497 rt_pse_buf_drop(sc); 1498 1499 if (status & GDM_OTHER_DROP) 1500 rt_gdm_other_drop(sc); 1501 1502 if (status & PSE_P1_FC) 1503 rt_pse_p1_fc(sc); 1504 1505 if (status & PSE_P0_FC) 1506 rt_pse_p0_fc(sc); 1507 1508 if (status & PSE_FQ_EMPTY) 1509 rt_pse_fq_empty(sc); 1510 1511 if (status & INT_TX_COHERENT) 1512 rt_tx_coherent_intr(sc); 1513 1514 if (status & INT_RX_COHERENT) 1515 rt_rx_coherent_intr(sc); 1516 1517 if (status & RX_DLY_INT) 1518 rt_rx_delay_intr(sc); 1519 1520 if (status & TX_DLY_INT) 1521 rt_tx_delay_intr(sc); 1522 1523 if (status & INT_RX_DONE) 1524 rt_rx_intr(sc, 0); 1525 1526 if (status & INT_TXQ3_DONE) 1527 rt_tx_intr(sc, 3); 1528 1529 if (status & INT_TXQ2_DONE) 1530 rt_tx_intr(sc, 2); 1531 1532 if (status & INT_TXQ1_DONE) 1533 rt_tx_intr(sc, 1); 1534 1535 if (status & INT_TXQ0_DONE) 1536 rt_tx_intr(sc, 0); 1537 } 1538 1539 /* 1540 * rt_rt5350_intr - main ISR for Ralink 5350 SoC 1541 */ 1542 static void 1543 rt_rt5350_intr(void *arg) 1544 { 1545 struct rt_softc *sc; 1546 struct ifnet *ifp; 1547 uint32_t status; 1548 1549 sc = arg; 1550 ifp = sc->ifp; 1551 1552 /* acknowledge interrupts */ 1553 status = RT_READ(sc, sc->fe_int_status); 1554 RT_WRITE(sc, sc->fe_int_status, status); 1555 1556 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status); 1557 1558 if (status == 0xffffffff || /* device likely went away */ 1559 status == 0) /* not for us */ 1560 return; 1561 1562 sc->interrupts++; 1563 1564 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1565 return; 1566 1567 if (status & RT5350_INT_TX_COHERENT) 1568 rt_tx_coherent_intr(sc); 1569 if (status & RT5350_INT_RX_COHERENT) 1570 rt_rx_coherent_intr(sc); 1571 if (status & RT5350_RX_DLY_INT) 1572 rt_rx_delay_intr(sc); 1573 if (status & RT5350_TX_DLY_INT) 1574 rt_tx_delay_intr(sc); 1575 if (status & RT5350_INT_RXQ1_DONE) 1576 rt_rx_intr(sc, 1); 1577 if (status & RT5350_INT_RXQ0_DONE) 1578 rt_rx_intr(sc, 0); 1579 if (status & RT5350_INT_TXQ3_DONE) 1580 rt_tx_intr(sc, 3); 1581 if (status & RT5350_INT_TXQ2_DONE) 1582 rt_tx_intr(sc, 2); 1583 if (status & RT5350_INT_TXQ1_DONE) 1584 rt_tx_intr(sc, 1); 1585 if (status & RT5350_INT_TXQ0_DONE) 1586 rt_tx_intr(sc, 0); 1587 } 1588 1589 static void 1590 rt_tx_coherent_intr(struct rt_softc *sc) 1591 { 1592 uint32_t tmp; 1593 int i; 1594 1595 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx coherent interrupt\n"); 1596 1597 sc->tx_coherent_interrupts++; 1598 1599 /* restart DMA engine */ 1600 tmp = RT_READ(sc, sc->pdma_glo_cfg); 1601 tmp &= ~(FE_TX_WB_DDONE | FE_TX_DMA_EN); 1602 RT_WRITE(sc, sc->pdma_glo_cfg, tmp); 1603 1604 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) 1605 rt_reset_tx_ring(sc, &sc->tx_ring[i]); 1606 1607 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) { 1608 RT_WRITE(sc, sc->tx_base_ptr[i], 1609 sc->tx_ring[i].desc_phys_addr); 1610 RT_WRITE(sc, sc->tx_max_cnt[i], 1611 RT_SOFTC_TX_RING_DESC_COUNT); 1612 RT_WRITE(sc, sc->tx_ctx_idx[i], 0); 1613 } 1614 1615 rt_txrx_enable(sc); 1616 } 1617 1618 /* 1619 * rt_rx_coherent_intr 1620 */ 1621 static void 1622 rt_rx_coherent_intr(struct rt_softc *sc) 1623 { 1624 uint32_t tmp; 1625 int i; 1626 1627 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx coherent interrupt\n"); 1628 1629 sc->rx_coherent_interrupts++; 1630 1631 /* restart DMA engine */ 1632 tmp = RT_READ(sc, sc->pdma_glo_cfg); 1633 tmp &= ~(FE_RX_DMA_EN); 1634 RT_WRITE(sc, sc->pdma_glo_cfg, tmp); 1635 1636 /* init Rx ring */ 1637 for (i = 0; i < sc->rx_ring_count; i++) 1638 rt_reset_rx_ring(sc, &sc->rx_ring[i]); 1639 1640 for (i = 0; i < sc->rx_ring_count; i++) { 1641 RT_WRITE(sc, sc->rx_base_ptr[i], 1642 sc->rx_ring[i].desc_phys_addr); 1643 RT_WRITE(sc, sc->rx_max_cnt[i], 1644 RT_SOFTC_RX_RING_DATA_COUNT); 1645 RT_WRITE(sc, sc->rx_calc_idx[i], 1646 RT_SOFTC_RX_RING_DATA_COUNT - 1); 1647 } 1648 1649 rt_txrx_enable(sc); 1650 } 1651 1652 /* 1653 * rt_rx_intr - a packet received 1654 */ 1655 static void 1656 rt_rx_intr(struct rt_softc *sc, int qid) 1657 { 1658 KASSERT(qid >= 0 && qid < sc->rx_ring_count, 1659 ("%s: Rx interrupt: invalid qid=%d\n", 1660 device_get_nameunit(sc->dev), qid)); 1661 1662 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx interrupt\n"); 1663 sc->rx_interrupts[qid]++; 1664 RT_SOFTC_LOCK(sc); 1665 1666 if (!(sc->intr_disable_mask & (sc->int_rx_done_mask << qid))) { 1667 rt_intr_disable(sc, (sc->int_rx_done_mask << qid)); 1668 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task); 1669 } 1670 1671 sc->intr_pending_mask |= (sc->int_rx_done_mask << qid); 1672 RT_SOFTC_UNLOCK(sc); 1673 } 1674 1675 static void 1676 rt_rx_delay_intr(struct rt_softc *sc) 1677 { 1678 1679 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx delay interrupt\n"); 1680 sc->rx_delay_interrupts++; 1681 } 1682 1683 static void 1684 rt_tx_delay_intr(struct rt_softc *sc) 1685 { 1686 1687 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx delay interrupt\n"); 1688 sc->tx_delay_interrupts++; 1689 } 1690 1691 /* 1692 * rt_tx_intr - Transsmition of packet done 1693 */ 1694 static void 1695 rt_tx_intr(struct rt_softc *sc, int qid) 1696 { 1697 1698 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT, 1699 ("%s: Tx interrupt: invalid qid=%d\n", 1700 device_get_nameunit(sc->dev), qid)); 1701 1702 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx interrupt: qid=%d\n", qid); 1703 1704 sc->tx_interrupts[qid]++; 1705 RT_SOFTC_LOCK(sc); 1706 1707 if (!(sc->intr_disable_mask & (sc->int_tx_done_mask << qid))) { 1708 rt_intr_disable(sc, (sc->int_tx_done_mask << qid)); 1709 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task); 1710 } 1711 1712 sc->intr_pending_mask |= (sc->int_tx_done_mask << qid); 1713 RT_SOFTC_UNLOCK(sc); 1714 } 1715 1716 /* 1717 * rt_rx_done_task - run RX task 1718 */ 1719 static void 1720 rt_rx_done_task(void *context, int pending) 1721 { 1722 struct rt_softc *sc; 1723 struct ifnet *ifp; 1724 int again; 1725 1726 sc = context; 1727 ifp = sc->ifp; 1728 1729 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx done task\n"); 1730 1731 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1732 return; 1733 1734 sc->intr_pending_mask &= ~sc->int_rx_done_mask; 1735 1736 again = rt_rx_eof(sc, &sc->rx_ring[0], sc->rx_process_limit); 1737 1738 RT_SOFTC_LOCK(sc); 1739 1740 if ((sc->intr_pending_mask & sc->int_rx_done_mask) || again) { 1741 RT_DPRINTF(sc, RT_DEBUG_RX, 1742 "Rx done task: scheduling again\n"); 1743 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task); 1744 } else { 1745 rt_intr_enable(sc, sc->int_rx_done_mask); 1746 } 1747 1748 RT_SOFTC_UNLOCK(sc); 1749 } 1750 1751 /* 1752 * rt_tx_done_task - check for pending TX task in all queues 1753 */ 1754 static void 1755 rt_tx_done_task(void *context, int pending) 1756 { 1757 struct rt_softc *sc; 1758 struct ifnet *ifp; 1759 uint32_t intr_mask; 1760 int i; 1761 1762 sc = context; 1763 ifp = sc->ifp; 1764 1765 RT_DPRINTF(sc, RT_DEBUG_TX, "Tx done task\n"); 1766 1767 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1768 return; 1769 1770 for (i = RT_SOFTC_TX_RING_COUNT - 1; i >= 0; i--) { 1771 if (sc->intr_pending_mask & (sc->int_tx_done_mask << i)) { 1772 sc->intr_pending_mask &= ~(sc->int_tx_done_mask << i); 1773 rt_tx_eof(sc, &sc->tx_ring[i]); 1774 } 1775 } 1776 1777 sc->tx_timer = 0; 1778 1779 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1780 1781 if(sc->rt_chipid == RT_CHIPID_RT5350 || 1782 sc->rt_chipid == RT_CHIPID_MT7620 || 1783 sc->rt_chipid == RT_CHIPID_MT7621) 1784 intr_mask = ( 1785 RT5350_INT_TXQ3_DONE | 1786 RT5350_INT_TXQ2_DONE | 1787 RT5350_INT_TXQ1_DONE | 1788 RT5350_INT_TXQ0_DONE); 1789 else 1790 intr_mask = ( 1791 INT_TXQ3_DONE | 1792 INT_TXQ2_DONE | 1793 INT_TXQ1_DONE | 1794 INT_TXQ0_DONE); 1795 1796 RT_SOFTC_LOCK(sc); 1797 1798 rt_intr_enable(sc, ~sc->intr_pending_mask & 1799 (sc->intr_disable_mask & intr_mask)); 1800 1801 if (sc->intr_pending_mask & intr_mask) { 1802 RT_DPRINTF(sc, RT_DEBUG_TX, 1803 "Tx done task: scheduling again\n"); 1804 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task); 1805 } 1806 1807 RT_SOFTC_UNLOCK(sc); 1808 1809 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1810 rt_start(ifp); 1811 } 1812 1813 /* 1814 * rt_periodic_task - run periodic task 1815 */ 1816 static void 1817 rt_periodic_task(void *context, int pending) 1818 { 1819 struct rt_softc *sc; 1820 struct ifnet *ifp; 1821 1822 sc = context; 1823 ifp = sc->ifp; 1824 1825 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic task: round=%lu\n", 1826 sc->periodic_round); 1827 1828 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1829 return; 1830 1831 RT_SOFTC_LOCK(sc); 1832 sc->periodic_round++; 1833 rt_update_stats(sc); 1834 1835 if ((sc->periodic_round % 10) == 0) { 1836 rt_update_raw_counters(sc); 1837 rt_watchdog(sc); 1838 } 1839 1840 RT_SOFTC_UNLOCK(sc); 1841 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc); 1842 } 1843 1844 /* 1845 * rt_rx_eof - check for frames that done by DMA engine and pass it into 1846 * network subsystem. 1847 */ 1848 static int 1849 rt_rx_eof(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int limit) 1850 { 1851 struct ifnet *ifp; 1852 /* struct rt_softc_rx_ring *ring; */ 1853 struct rt_rxdesc *desc; 1854 struct rt_softc_rx_data *data; 1855 struct mbuf *m, *mnew; 1856 bus_dma_segment_t segs[1]; 1857 bus_dmamap_t dma_map; 1858 uint32_t index, desc_flags; 1859 int error, nsegs, len, nframes; 1860 1861 ifp = sc->ifp; 1862 /* ring = &sc->rx_ring[0]; */ 1863 1864 nframes = 0; 1865 1866 while (limit != 0) { 1867 index = RT_READ(sc, sc->rx_drx_idx[0]); 1868 if (ring->cur == index) 1869 break; 1870 1871 desc = &ring->desc[ring->cur]; 1872 data = &ring->data[ring->cur]; 1873 1874 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 1875 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1876 1877 #ifdef IF_RT_DEBUG 1878 if ( sc->debug & RT_DEBUG_RX ) { 1879 printf("\nRX Descriptor[%#08x] dump:\n", (u_int)desc); 1880 hexdump(desc, 16, 0, 0); 1881 printf("-----------------------------------\n"); 1882 } 1883 #endif 1884 1885 /* XXX Sometime device don`t set DDONE bit */ 1886 #ifdef DDONE_FIXED 1887 if (!(desc->sdl0 & htole16(RT_RXDESC_SDL0_DDONE))) { 1888 RT_DPRINTF(sc, RT_DEBUG_RX, "DDONE=0, try next\n"); 1889 break; 1890 } 1891 #endif 1892 1893 len = le16toh(desc->sdl0) & 0x3fff; 1894 RT_DPRINTF(sc, RT_DEBUG_RX, "new frame len=%d\n", len); 1895 1896 nframes++; 1897 1898 mnew = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 1899 MJUMPAGESIZE); 1900 if (mnew == NULL) { 1901 sc->rx_mbuf_alloc_errors++; 1902 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1903 goto skip; 1904 } 1905 1906 mnew->m_len = mnew->m_pkthdr.len = MJUMPAGESIZE; 1907 1908 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, 1909 ring->spare_dma_map, mnew, segs, &nsegs, BUS_DMA_NOWAIT); 1910 if (error != 0) { 1911 RT_DPRINTF(sc, RT_DEBUG_RX, 1912 "could not load Rx mbuf DMA map: " 1913 "error=%d, nsegs=%d\n", 1914 error, nsegs); 1915 1916 m_freem(mnew); 1917 1918 sc->rx_mbuf_dmamap_errors++; 1919 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1920 1921 goto skip; 1922 } 1923 1924 KASSERT(nsegs == 1, ("%s: too many DMA segments", 1925 device_get_nameunit(sc->dev))); 1926 1927 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 1928 BUS_DMASYNC_POSTREAD); 1929 bus_dmamap_unload(ring->data_dma_tag, data->dma_map); 1930 1931 dma_map = data->dma_map; 1932 data->dma_map = ring->spare_dma_map; 1933 ring->spare_dma_map = dma_map; 1934 1935 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 1936 BUS_DMASYNC_PREREAD); 1937 1938 m = data->m; 1939 desc_flags = desc->word3; 1940 1941 data->m = mnew; 1942 /* Add 2 for proper align of RX IP header */ 1943 desc->sdp0 = htole32(segs[0].ds_addr+2); 1944 desc->sdl0 = htole32(segs[0].ds_len-2); 1945 desc->word3 = 0; 1946 1947 RT_DPRINTF(sc, RT_DEBUG_RX, 1948 "Rx frame: rxdesc flags=0x%08x\n", desc_flags); 1949 1950 m->m_pkthdr.rcvif = ifp; 1951 /* Add 2 to fix data align, after sdp0 = addr + 2 */ 1952 m->m_data += 2; 1953 m->m_pkthdr.len = m->m_len = len; 1954 1955 /* check for crc errors */ 1956 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1957 /*check for valid checksum*/ 1958 if (desc_flags & (sc->csum_fail_ip|sc->csum_fail_l4)) { 1959 RT_DPRINTF(sc, RT_DEBUG_RX, 1960 "rxdesc: crc error\n"); 1961 1962 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1963 1964 if (!(ifp->if_flags & IFF_PROMISC)) { 1965 m_freem(m); 1966 goto skip; 1967 } 1968 } 1969 if ((desc_flags & sc->csum_fail_ip) == 0) { 1970 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1971 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1972 m->m_pkthdr.csum_data = 0xffff; 1973 } 1974 m->m_flags &= ~M_HASFCS; 1975 } 1976 1977 (*ifp->if_input)(ifp, m); 1978 skip: 1979 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE); 1980 1981 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 1982 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1983 1984 ring->cur = (ring->cur + 1) % RT_SOFTC_RX_RING_DATA_COUNT; 1985 1986 limit--; 1987 } 1988 1989 if (ring->cur == 0) 1990 RT_WRITE(sc, sc->rx_calc_idx[0], 1991 RT_SOFTC_RX_RING_DATA_COUNT - 1); 1992 else 1993 RT_WRITE(sc, sc->rx_calc_idx[0], 1994 ring->cur - 1); 1995 1996 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx eof: nframes=%d\n", nframes); 1997 1998 sc->rx_packets += nframes; 1999 2000 return (limit == 0); 2001 } 2002 2003 /* 2004 * rt_tx_eof - check for successful transmitted frames and mark their 2005 * descriptor as free. 2006 */ 2007 static void 2008 rt_tx_eof(struct rt_softc *sc, struct rt_softc_tx_ring *ring) 2009 { 2010 struct ifnet *ifp; 2011 struct rt_txdesc *desc; 2012 struct rt_softc_tx_data *data; 2013 uint32_t index; 2014 int ndescs, nframes; 2015 2016 ifp = sc->ifp; 2017 2018 ndescs = 0; 2019 nframes = 0; 2020 2021 for (;;) { 2022 index = RT_READ(sc, sc->tx_dtx_idx[ring->qid]); 2023 if (ring->desc_next == index) 2024 break; 2025 2026 ndescs++; 2027 2028 desc = &ring->desc[ring->desc_next]; 2029 2030 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 2031 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2032 2033 if (desc->sdl0 & htole16(RT_TXDESC_SDL0_LASTSEG) || 2034 desc->sdl1 & htole16(RT_TXDESC_SDL1_LASTSEG)) { 2035 nframes++; 2036 2037 data = &ring->data[ring->data_next]; 2038 2039 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 2040 BUS_DMASYNC_POSTWRITE); 2041 bus_dmamap_unload(ring->data_dma_tag, data->dma_map); 2042 2043 m_freem(data->m); 2044 2045 data->m = NULL; 2046 2047 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2048 2049 RT_SOFTC_TX_RING_LOCK(ring); 2050 ring->data_queued--; 2051 ring->data_next = (ring->data_next + 1) % 2052 RT_SOFTC_TX_RING_DATA_COUNT; 2053 RT_SOFTC_TX_RING_UNLOCK(ring); 2054 } 2055 2056 desc->sdl0 &= ~htole16(RT_TXDESC_SDL0_DDONE); 2057 2058 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 2059 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2060 2061 RT_SOFTC_TX_RING_LOCK(ring); 2062 ring->desc_queued--; 2063 ring->desc_next = (ring->desc_next + 1) % 2064 RT_SOFTC_TX_RING_DESC_COUNT; 2065 RT_SOFTC_TX_RING_UNLOCK(ring); 2066 } 2067 2068 RT_DPRINTF(sc, RT_DEBUG_TX, 2069 "Tx eof: qid=%d, ndescs=%d, nframes=%d\n", ring->qid, ndescs, 2070 nframes); 2071 } 2072 2073 /* 2074 * rt_update_stats - query statistics counters and update related variables. 2075 */ 2076 static void 2077 rt_update_stats(struct rt_softc *sc) 2078 { 2079 struct ifnet *ifp; 2080 2081 ifp = sc->ifp; 2082 RT_DPRINTF(sc, RT_DEBUG_STATS, "update statistic: \n"); 2083 /* XXX do update stats here */ 2084 } 2085 2086 /* 2087 * rt_watchdog - reinit device on watchdog event. 2088 */ 2089 static void 2090 rt_watchdog(struct rt_softc *sc) 2091 { 2092 uint32_t tmp; 2093 #ifdef notyet 2094 int ntries; 2095 #endif 2096 if(sc->rt_chipid != RT_CHIPID_RT5350 && 2097 sc->rt_chipid != RT_CHIPID_MT7620 && 2098 sc->rt_chipid != RT_CHIPID_MT7621) { 2099 tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA); 2100 2101 RT_DPRINTF(sc, RT_DEBUG_WATCHDOG, 2102 "watchdog: PSE_IQ_STA=0x%08x\n", tmp); 2103 } 2104 /* XXX: do not reset */ 2105 #ifdef notyet 2106 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) != 0) { 2107 sc->tx_queue_not_empty[0]++; 2108 2109 for (ntries = 0; ntries < 10; ntries++) { 2110 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA); 2111 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) == 0) 2112 break; 2113 2114 DELAY(1); 2115 } 2116 } 2117 2118 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) != 0) { 2119 sc->tx_queue_not_empty[1]++; 2120 2121 for (ntries = 0; ntries < 10; ntries++) { 2122 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA); 2123 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) == 0) 2124 break; 2125 2126 DELAY(1); 2127 } 2128 } 2129 #endif 2130 } 2131 2132 /* 2133 * rt_update_raw_counters - update counters. 2134 */ 2135 static void 2136 rt_update_raw_counters(struct rt_softc *sc) 2137 { 2138 2139 sc->tx_bytes += RT_READ(sc, CNTR_BASE + GDMA_TX_GBCNT0); 2140 sc->tx_packets += RT_READ(sc, CNTR_BASE + GDMA_TX_GPCNT0); 2141 sc->tx_skip += RT_READ(sc, CNTR_BASE + GDMA_TX_SKIPCNT0); 2142 sc->tx_collision+= RT_READ(sc, CNTR_BASE + GDMA_TX_COLCNT0); 2143 2144 sc->rx_bytes += RT_READ(sc, CNTR_BASE + GDMA_RX_GBCNT0); 2145 sc->rx_packets += RT_READ(sc, CNTR_BASE + GDMA_RX_GPCNT0); 2146 sc->rx_crc_err += RT_READ(sc, CNTR_BASE + GDMA_RX_CSUM_ERCNT0); 2147 sc->rx_short_err+= RT_READ(sc, CNTR_BASE + GDMA_RX_SHORT_ERCNT0); 2148 sc->rx_long_err += RT_READ(sc, CNTR_BASE + GDMA_RX_LONG_ERCNT0); 2149 sc->rx_phy_err += RT_READ(sc, CNTR_BASE + GDMA_RX_FERCNT0); 2150 sc->rx_fifo_overflows+= RT_READ(sc, CNTR_BASE + GDMA_RX_OERCNT0); 2151 } 2152 2153 static void 2154 rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask) 2155 { 2156 uint32_t tmp; 2157 2158 sc->intr_disable_mask &= ~intr_mask; 2159 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask; 2160 RT_WRITE(sc, sc->fe_int_enable, tmp); 2161 } 2162 2163 static void 2164 rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask) 2165 { 2166 uint32_t tmp; 2167 2168 sc->intr_disable_mask |= intr_mask; 2169 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask; 2170 RT_WRITE(sc, sc->fe_int_enable, tmp); 2171 } 2172 2173 /* 2174 * rt_txrx_enable - enable TX/RX DMA 2175 */ 2176 static int 2177 rt_txrx_enable(struct rt_softc *sc) 2178 { 2179 struct ifnet *ifp; 2180 uint32_t tmp; 2181 int ntries; 2182 2183 ifp = sc->ifp; 2184 2185 /* enable Tx/Rx DMA engine */ 2186 for (ntries = 0; ntries < 200; ntries++) { 2187 tmp = RT_READ(sc, sc->pdma_glo_cfg); 2188 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY))) 2189 break; 2190 2191 DELAY(1000); 2192 } 2193 2194 if (ntries == 200) { 2195 device_printf(sc->dev, "timeout waiting for DMA engine\n"); 2196 return (-1); 2197 } 2198 2199 DELAY(50); 2200 2201 tmp |= FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN; 2202 RT_WRITE(sc, sc->pdma_glo_cfg, tmp); 2203 2204 /* XXX set Rx filter */ 2205 return (0); 2206 } 2207 2208 /* 2209 * rt_alloc_rx_ring - allocate RX DMA ring buffer 2210 */ 2211 static int 2212 rt_alloc_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int qid) 2213 { 2214 struct rt_rxdesc *desc; 2215 struct rt_softc_rx_data *data; 2216 bus_dma_segment_t segs[1]; 2217 int i, nsegs, error; 2218 2219 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, 2220 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2221 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 1, 2222 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 2223 0, NULL, NULL, &ring->desc_dma_tag); 2224 if (error != 0) { 2225 device_printf(sc->dev, 2226 "could not create Rx desc DMA tag\n"); 2227 goto fail; 2228 } 2229 2230 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc, 2231 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map); 2232 if (error != 0) { 2233 device_printf(sc->dev, 2234 "could not allocate Rx desc DMA memory\n"); 2235 goto fail; 2236 } 2237 2238 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map, 2239 ring->desc, 2240 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 2241 rt_dma_map_addr, &ring->desc_phys_addr, 0); 2242 if (error != 0) { 2243 device_printf(sc->dev, "could not load Rx desc DMA map\n"); 2244 goto fail; 2245 } 2246 2247 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, 2248 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2249 MJUMPAGESIZE, 1, MJUMPAGESIZE, 0, NULL, NULL, 2250 &ring->data_dma_tag); 2251 if (error != 0) { 2252 device_printf(sc->dev, 2253 "could not create Rx data DMA tag\n"); 2254 goto fail; 2255 } 2256 2257 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) { 2258 desc = &ring->desc[i]; 2259 data = &ring->data[i]; 2260 2261 error = bus_dmamap_create(ring->data_dma_tag, 0, 2262 &data->dma_map); 2263 if (error != 0) { 2264 device_printf(sc->dev, "could not create Rx data DMA " 2265 "map\n"); 2266 goto fail; 2267 } 2268 2269 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 2270 MJUMPAGESIZE); 2271 if (data->m == NULL) { 2272 device_printf(sc->dev, "could not allocate Rx mbuf\n"); 2273 error = ENOMEM; 2274 goto fail; 2275 } 2276 2277 data->m->m_len = data->m->m_pkthdr.len = MJUMPAGESIZE; 2278 2279 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, 2280 data->dma_map, data->m, segs, &nsegs, BUS_DMA_NOWAIT); 2281 if (error != 0) { 2282 device_printf(sc->dev, 2283 "could not load Rx mbuf DMA map\n"); 2284 goto fail; 2285 } 2286 2287 KASSERT(nsegs == 1, ("%s: too many DMA segments", 2288 device_get_nameunit(sc->dev))); 2289 2290 /* Add 2 for proper align of RX IP header */ 2291 desc->sdp0 = htole32(segs[0].ds_addr+2); 2292 desc->sdl0 = htole32(segs[0].ds_len-2); 2293 } 2294 2295 error = bus_dmamap_create(ring->data_dma_tag, 0, 2296 &ring->spare_dma_map); 2297 if (error != 0) { 2298 device_printf(sc->dev, 2299 "could not create Rx spare DMA map\n"); 2300 goto fail; 2301 } 2302 2303 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 2304 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2305 ring->qid = qid; 2306 return (0); 2307 2308 fail: 2309 rt_free_rx_ring(sc, ring); 2310 return (error); 2311 } 2312 2313 /* 2314 * rt_reset_rx_ring - reset RX ring buffer 2315 */ 2316 static void 2317 rt_reset_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring) 2318 { 2319 struct rt_rxdesc *desc; 2320 int i; 2321 2322 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) { 2323 desc = &ring->desc[i]; 2324 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE); 2325 } 2326 2327 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 2328 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2329 ring->cur = 0; 2330 } 2331 2332 /* 2333 * rt_free_rx_ring - free memory used by RX ring buffer 2334 */ 2335 static void 2336 rt_free_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring) 2337 { 2338 struct rt_softc_rx_data *data; 2339 int i; 2340 2341 if (ring->desc != NULL) { 2342 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 2343 BUS_DMASYNC_POSTWRITE); 2344 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map); 2345 bus_dmamem_free(ring->desc_dma_tag, ring->desc, 2346 ring->desc_dma_map); 2347 } 2348 2349 if (ring->desc_dma_tag != NULL) 2350 bus_dma_tag_destroy(ring->desc_dma_tag); 2351 2352 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) { 2353 data = &ring->data[i]; 2354 2355 if (data->m != NULL) { 2356 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 2357 BUS_DMASYNC_POSTREAD); 2358 bus_dmamap_unload(ring->data_dma_tag, data->dma_map); 2359 m_freem(data->m); 2360 } 2361 2362 if (data->dma_map != NULL) 2363 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map); 2364 } 2365 2366 if (ring->spare_dma_map != NULL) 2367 bus_dmamap_destroy(ring->data_dma_tag, ring->spare_dma_map); 2368 2369 if (ring->data_dma_tag != NULL) 2370 bus_dma_tag_destroy(ring->data_dma_tag); 2371 } 2372 2373 /* 2374 * rt_alloc_tx_ring - allocate TX ring buffer 2375 */ 2376 static int 2377 rt_alloc_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring, int qid) 2378 { 2379 struct rt_softc_tx_data *data; 2380 int error, i; 2381 2382 mtx_init(&ring->lock, device_get_nameunit(sc->dev), NULL, MTX_DEF); 2383 2384 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, 2385 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2386 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 1, 2387 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 2388 0, NULL, NULL, &ring->desc_dma_tag); 2389 if (error != 0) { 2390 device_printf(sc->dev, 2391 "could not create Tx desc DMA tag\n"); 2392 goto fail; 2393 } 2394 2395 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc, 2396 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map); 2397 if (error != 0) { 2398 device_printf(sc->dev, 2399 "could not allocate Tx desc DMA memory\n"); 2400 goto fail; 2401 } 2402 2403 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map, 2404 ring->desc, (RT_SOFTC_TX_RING_DESC_COUNT * 2405 sizeof(struct rt_txdesc)), rt_dma_map_addr, 2406 &ring->desc_phys_addr, 0); 2407 if (error != 0) { 2408 device_printf(sc->dev, "could not load Tx desc DMA map\n"); 2409 goto fail; 2410 } 2411 2412 ring->desc_queued = 0; 2413 ring->desc_cur = 0; 2414 ring->desc_next = 0; 2415 2416 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, 2417 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2418 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 1, 2419 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 2420 0, NULL, NULL, &ring->seg0_dma_tag); 2421 if (error != 0) { 2422 device_printf(sc->dev, 2423 "could not create Tx seg0 DMA tag\n"); 2424 goto fail; 2425 } 2426 2427 error = bus_dmamem_alloc(ring->seg0_dma_tag, (void **) &ring->seg0, 2428 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->seg0_dma_map); 2429 if (error != 0) { 2430 device_printf(sc->dev, 2431 "could not allocate Tx seg0 DMA memory\n"); 2432 goto fail; 2433 } 2434 2435 error = bus_dmamap_load(ring->seg0_dma_tag, ring->seg0_dma_map, 2436 ring->seg0, 2437 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 2438 rt_dma_map_addr, &ring->seg0_phys_addr, 0); 2439 if (error != 0) { 2440 device_printf(sc->dev, "could not load Tx seg0 DMA map\n"); 2441 goto fail; 2442 } 2443 2444 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0, 2445 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2446 MJUMPAGESIZE, RT_SOFTC_MAX_SCATTER, MJUMPAGESIZE, 0, NULL, NULL, 2447 &ring->data_dma_tag); 2448 if (error != 0) { 2449 device_printf(sc->dev, 2450 "could not create Tx data DMA tag\n"); 2451 goto fail; 2452 } 2453 2454 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) { 2455 data = &ring->data[i]; 2456 2457 error = bus_dmamap_create(ring->data_dma_tag, 0, 2458 &data->dma_map); 2459 if (error != 0) { 2460 device_printf(sc->dev, "could not create Tx data DMA " 2461 "map\n"); 2462 goto fail; 2463 } 2464 } 2465 2466 ring->data_queued = 0; 2467 ring->data_cur = 0; 2468 ring->data_next = 0; 2469 2470 ring->qid = qid; 2471 return (0); 2472 2473 fail: 2474 rt_free_tx_ring(sc, ring); 2475 return (error); 2476 } 2477 2478 /* 2479 * rt_reset_tx_ring - reset TX ring buffer to empty state 2480 */ 2481 static void 2482 rt_reset_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring) 2483 { 2484 struct rt_softc_tx_data *data; 2485 struct rt_txdesc *desc; 2486 int i; 2487 2488 for (i = 0; i < RT_SOFTC_TX_RING_DESC_COUNT; i++) { 2489 desc = &ring->desc[i]; 2490 2491 desc->sdl0 = 0; 2492 desc->sdl1 = 0; 2493 } 2494 2495 ring->desc_queued = 0; 2496 ring->desc_cur = 0; 2497 ring->desc_next = 0; 2498 2499 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 2500 BUS_DMASYNC_PREWRITE); 2501 2502 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, 2503 BUS_DMASYNC_PREWRITE); 2504 2505 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) { 2506 data = &ring->data[i]; 2507 2508 if (data->m != NULL) { 2509 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 2510 BUS_DMASYNC_POSTWRITE); 2511 bus_dmamap_unload(ring->data_dma_tag, data->dma_map); 2512 m_freem(data->m); 2513 data->m = NULL; 2514 } 2515 } 2516 2517 ring->data_queued = 0; 2518 ring->data_cur = 0; 2519 ring->data_next = 0; 2520 } 2521 2522 /* 2523 * rt_free_tx_ring - free RX ring buffer 2524 */ 2525 static void 2526 rt_free_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring) 2527 { 2528 struct rt_softc_tx_data *data; 2529 int i; 2530 2531 if (ring->desc != NULL) { 2532 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map, 2533 BUS_DMASYNC_POSTWRITE); 2534 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map); 2535 bus_dmamem_free(ring->desc_dma_tag, ring->desc, 2536 ring->desc_dma_map); 2537 } 2538 2539 if (ring->desc_dma_tag != NULL) 2540 bus_dma_tag_destroy(ring->desc_dma_tag); 2541 2542 if (ring->seg0 != NULL) { 2543 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map, 2544 BUS_DMASYNC_POSTWRITE); 2545 bus_dmamap_unload(ring->seg0_dma_tag, ring->seg0_dma_map); 2546 bus_dmamem_free(ring->seg0_dma_tag, ring->seg0, 2547 ring->seg0_dma_map); 2548 } 2549 2550 if (ring->seg0_dma_tag != NULL) 2551 bus_dma_tag_destroy(ring->seg0_dma_tag); 2552 2553 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) { 2554 data = &ring->data[i]; 2555 2556 if (data->m != NULL) { 2557 bus_dmamap_sync(ring->data_dma_tag, data->dma_map, 2558 BUS_DMASYNC_POSTWRITE); 2559 bus_dmamap_unload(ring->data_dma_tag, data->dma_map); 2560 m_freem(data->m); 2561 } 2562 2563 if (data->dma_map != NULL) 2564 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map); 2565 } 2566 2567 if (ring->data_dma_tag != NULL) 2568 bus_dma_tag_destroy(ring->data_dma_tag); 2569 2570 mtx_destroy(&ring->lock); 2571 } 2572 2573 /* 2574 * rt_dma_map_addr - get address of busdma segment 2575 */ 2576 static void 2577 rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2578 { 2579 if (error != 0) 2580 return; 2581 2582 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 2583 2584 *(bus_addr_t *) arg = segs[0].ds_addr; 2585 } 2586 2587 /* 2588 * rt_sysctl_attach - attach sysctl nodes for NIC counters. 2589 */ 2590 static void 2591 rt_sysctl_attach(struct rt_softc *sc) 2592 { 2593 struct sysctl_ctx_list *ctx; 2594 struct sysctl_oid *tree; 2595 struct sysctl_oid *stats; 2596 2597 ctx = device_get_sysctl_ctx(sc->dev); 2598 tree = device_get_sysctl_tree(sc->dev); 2599 2600 /* statistic counters */ 2601 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2602 "stats", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "statistic"); 2603 2604 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2605 "interrupts", CTLFLAG_RD, &sc->interrupts, 2606 "all interrupts"); 2607 2608 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2609 "tx_coherent_interrupts", CTLFLAG_RD, &sc->tx_coherent_interrupts, 2610 "Tx coherent interrupts"); 2611 2612 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2613 "rx_coherent_interrupts", CTLFLAG_RD, &sc->rx_coherent_interrupts, 2614 "Rx coherent interrupts"); 2615 2616 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2617 "rx_interrupts", CTLFLAG_RD, &sc->rx_interrupts[0], 2618 "Rx interrupts"); 2619 2620 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2621 "rx_delay_interrupts", CTLFLAG_RD, &sc->rx_delay_interrupts, 2622 "Rx delay interrupts"); 2623 2624 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2625 "TXQ3_interrupts", CTLFLAG_RD, &sc->tx_interrupts[3], 2626 "Tx AC3 interrupts"); 2627 2628 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2629 "TXQ2_interrupts", CTLFLAG_RD, &sc->tx_interrupts[2], 2630 "Tx AC2 interrupts"); 2631 2632 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2633 "TXQ1_interrupts", CTLFLAG_RD, &sc->tx_interrupts[1], 2634 "Tx AC1 interrupts"); 2635 2636 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2637 "TXQ0_interrupts", CTLFLAG_RD, &sc->tx_interrupts[0], 2638 "Tx AC0 interrupts"); 2639 2640 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2641 "tx_delay_interrupts", CTLFLAG_RD, &sc->tx_delay_interrupts, 2642 "Tx delay interrupts"); 2643 2644 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2645 "TXQ3_desc_queued", CTLFLAG_RD, &sc->tx_ring[3].desc_queued, 2646 0, "Tx AC3 descriptors queued"); 2647 2648 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2649 "TXQ3_data_queued", CTLFLAG_RD, &sc->tx_ring[3].data_queued, 2650 0, "Tx AC3 data queued"); 2651 2652 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2653 "TXQ2_desc_queued", CTLFLAG_RD, &sc->tx_ring[2].desc_queued, 2654 0, "Tx AC2 descriptors queued"); 2655 2656 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2657 "TXQ2_data_queued", CTLFLAG_RD, &sc->tx_ring[2].data_queued, 2658 0, "Tx AC2 data queued"); 2659 2660 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2661 "TXQ1_desc_queued", CTLFLAG_RD, &sc->tx_ring[1].desc_queued, 2662 0, "Tx AC1 descriptors queued"); 2663 2664 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2665 "TXQ1_data_queued", CTLFLAG_RD, &sc->tx_ring[1].data_queued, 2666 0, "Tx AC1 data queued"); 2667 2668 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2669 "TXQ0_desc_queued", CTLFLAG_RD, &sc->tx_ring[0].desc_queued, 2670 0, "Tx AC0 descriptors queued"); 2671 2672 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2673 "TXQ0_data_queued", CTLFLAG_RD, &sc->tx_ring[0].data_queued, 2674 0, "Tx AC0 data queued"); 2675 2676 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2677 "TXQ3_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[3], 2678 "Tx AC3 data queue full"); 2679 2680 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2681 "TXQ2_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[2], 2682 "Tx AC2 data queue full"); 2683 2684 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2685 "TXQ1_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[1], 2686 "Tx AC1 data queue full"); 2687 2688 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2689 "TXQ0_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[0], 2690 "Tx AC0 data queue full"); 2691 2692 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2693 "tx_watchdog_timeouts", CTLFLAG_RD, &sc->tx_watchdog_timeouts, 2694 "Tx watchdog timeouts"); 2695 2696 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2697 "tx_defrag_packets", CTLFLAG_RD, &sc->tx_defrag_packets, 2698 "Tx defragmented packets"); 2699 2700 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2701 "no_tx_desc_avail", CTLFLAG_RD, &sc->no_tx_desc_avail, 2702 "no Tx descriptors available"); 2703 2704 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2705 "rx_mbuf_alloc_errors", CTLFLAG_RD, &sc->rx_mbuf_alloc_errors, 2706 "Rx mbuf allocation errors"); 2707 2708 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2709 "rx_mbuf_dmamap_errors", CTLFLAG_RD, &sc->rx_mbuf_dmamap_errors, 2710 "Rx mbuf DMA mapping errors"); 2711 2712 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2713 "tx_queue_0_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[0], 2714 "Tx queue 0 not empty"); 2715 2716 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2717 "tx_queue_1_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[1], 2718 "Tx queue 1 not empty"); 2719 2720 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2721 "rx_packets", CTLFLAG_RD, &sc->rx_packets, 2722 "Rx packets"); 2723 2724 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2725 "rx_crc_errors", CTLFLAG_RD, &sc->rx_crc_err, 2726 "Rx CRC errors"); 2727 2728 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2729 "rx_phy_errors", CTLFLAG_RD, &sc->rx_phy_err, 2730 "Rx PHY errors"); 2731 2732 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2733 "rx_dup_packets", CTLFLAG_RD, &sc->rx_dup_packets, 2734 "Rx duplicate packets"); 2735 2736 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2737 "rx_fifo_overflows", CTLFLAG_RD, &sc->rx_fifo_overflows, 2738 "Rx FIFO overflows"); 2739 2740 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2741 "rx_bytes", CTLFLAG_RD, &sc->rx_bytes, 2742 "Rx bytes"); 2743 2744 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2745 "rx_long_err", CTLFLAG_RD, &sc->rx_long_err, 2746 "Rx too long frame errors"); 2747 2748 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2749 "rx_short_err", CTLFLAG_RD, &sc->rx_short_err, 2750 "Rx too short frame errors"); 2751 2752 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2753 "tx_bytes", CTLFLAG_RD, &sc->tx_bytes, 2754 "Tx bytes"); 2755 2756 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2757 "tx_packets", CTLFLAG_RD, &sc->tx_packets, 2758 "Tx packets"); 2759 2760 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2761 "tx_skip", CTLFLAG_RD, &sc->tx_skip, 2762 "Tx skip count for GDMA ports"); 2763 2764 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, 2765 "tx_collision", CTLFLAG_RD, &sc->tx_collision, 2766 "Tx collision count for GDMA ports"); 2767 } 2768 2769 #if defined(IF_RT_PHY_SUPPORT) || defined(RT_MDIO) 2770 /* This code is only work RT2880 and same chip. */ 2771 /* TODO: make RT3052 and later support code. But nobody need it? */ 2772 static int 2773 rt_miibus_readreg(device_t dev, int phy, int reg) 2774 { 2775 struct rt_softc *sc = device_get_softc(dev); 2776 int dat; 2777 2778 /* 2779 * PSEUDO_PHYAD is a special value for indicate switch attached. 2780 * No one PHY use PSEUDO_PHYAD (0x1e) address. 2781 */ 2782 #ifndef RT_MDIO 2783 if (phy == 31) { 2784 /* Fake PHY ID for bfeswitch attach */ 2785 switch (reg) { 2786 case MII_BMSR: 2787 return (BMSR_EXTSTAT|BMSR_MEDIAMASK); 2788 case MII_PHYIDR1: 2789 return (0x40); /* As result of faking */ 2790 case MII_PHYIDR2: /* PHY will detect as */ 2791 return (0x6250); /* bfeswitch */ 2792 } 2793 } 2794 #endif 2795 2796 /* Wait prev command done if any */ 2797 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO); 2798 dat = ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) | 2799 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK); 2800 RT_WRITE(sc, MDIO_ACCESS, dat); 2801 RT_WRITE(sc, MDIO_ACCESS, dat | MDIO_CMD_ONGO); 2802 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO); 2803 2804 return (RT_READ(sc, MDIO_ACCESS) & MDIO_PHY_DATA_MASK); 2805 } 2806 2807 static int 2808 rt_miibus_writereg(device_t dev, int phy, int reg, int val) 2809 { 2810 struct rt_softc *sc = device_get_softc(dev); 2811 int dat; 2812 2813 /* Wait prev command done if any */ 2814 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO); 2815 dat = MDIO_CMD_WR | 2816 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) | 2817 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK) | 2818 (val & MDIO_PHY_DATA_MASK); 2819 RT_WRITE(sc, MDIO_ACCESS, dat); 2820 RT_WRITE(sc, MDIO_ACCESS, dat | MDIO_CMD_ONGO); 2821 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO); 2822 2823 return (0); 2824 } 2825 #endif 2826 2827 #ifdef IF_RT_PHY_SUPPORT 2828 void 2829 rt_miibus_statchg(device_t dev) 2830 { 2831 struct rt_softc *sc = device_get_softc(dev); 2832 struct mii_data *mii; 2833 2834 mii = device_get_softc(sc->rt_miibus); 2835 2836 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2837 (IFM_ACTIVE | IFM_AVALID)) { 2838 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2839 case IFM_10_T: 2840 case IFM_100_TX: 2841 /* XXX check link here */ 2842 sc->flags |= 1; 2843 break; 2844 default: 2845 break; 2846 } 2847 } 2848 } 2849 #endif /* IF_RT_PHY_SUPPORT */ 2850 2851 static device_method_t rt_dev_methods[] = 2852 { 2853 DEVMETHOD(device_probe, rt_probe), 2854 DEVMETHOD(device_attach, rt_attach), 2855 DEVMETHOD(device_detach, rt_detach), 2856 DEVMETHOD(device_shutdown, rt_shutdown), 2857 DEVMETHOD(device_suspend, rt_suspend), 2858 DEVMETHOD(device_resume, rt_resume), 2859 2860 #ifdef IF_RT_PHY_SUPPORT 2861 /* MII interface */ 2862 DEVMETHOD(miibus_readreg, rt_miibus_readreg), 2863 DEVMETHOD(miibus_writereg, rt_miibus_writereg), 2864 DEVMETHOD(miibus_statchg, rt_miibus_statchg), 2865 #endif 2866 2867 DEVMETHOD_END 2868 }; 2869 2870 static driver_t rt_driver = 2871 { 2872 "rt", 2873 rt_dev_methods, 2874 sizeof(struct rt_softc) 2875 }; 2876 2877 static devclass_t rt_dev_class; 2878 2879 DRIVER_MODULE(rt, nexus, rt_driver, rt_dev_class, 0, 0); 2880 #ifdef FDT 2881 DRIVER_MODULE(rt, simplebus, rt_driver, rt_dev_class, 0, 0); 2882 #endif 2883 2884 MODULE_DEPEND(rt, ether, 1, 1, 1); 2885 MODULE_DEPEND(rt, miibus, 1, 1, 1); 2886 2887 #ifdef RT_MDIO 2888 MODULE_DEPEND(rt, mdio, 1, 1, 1); 2889 2890 static int rtmdio_probe(device_t); 2891 static int rtmdio_attach(device_t); 2892 static int rtmdio_detach(device_t); 2893 2894 static struct mtx miibus_mtx; 2895 2896 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "rt mii lock", MTX_DEF); 2897 2898 /* 2899 * Declare an additional, separate driver for accessing the MDIO bus. 2900 */ 2901 static device_method_t rtmdio_methods[] = { 2902 /* Device interface */ 2903 DEVMETHOD(device_probe, rtmdio_probe), 2904 DEVMETHOD(device_attach, rtmdio_attach), 2905 DEVMETHOD(device_detach, rtmdio_detach), 2906 2907 /* bus interface */ 2908 DEVMETHOD(bus_add_child, device_add_child_ordered), 2909 2910 /* MDIO access */ 2911 DEVMETHOD(mdio_readreg, rt_miibus_readreg), 2912 DEVMETHOD(mdio_writereg, rt_miibus_writereg), 2913 }; 2914 2915 DEFINE_CLASS_0(rtmdio, rtmdio_driver, rtmdio_methods, 2916 sizeof(struct rt_softc)); 2917 static devclass_t rtmdio_devclass; 2918 2919 DRIVER_MODULE(miiproxy, rt, miiproxy_driver, miiproxy_devclass, 0, 0); 2920 DRIVER_MODULE(rtmdio, simplebus, rtmdio_driver, rtmdio_devclass, 0, 0); 2921 DRIVER_MODULE(mdio, rtmdio, mdio_driver, mdio_devclass, 0, 0); 2922 2923 static int 2924 rtmdio_probe(device_t dev) 2925 { 2926 if (!ofw_bus_status_okay(dev)) 2927 return (ENXIO); 2928 2929 if (!ofw_bus_is_compatible(dev, "ralink,rt2880-mdio")) 2930 return (ENXIO); 2931 2932 device_set_desc(dev, "RT built-in ethernet interface, MDIO controller"); 2933 return(0); 2934 } 2935 2936 static int 2937 rtmdio_attach(device_t dev) 2938 { 2939 struct rt_softc *sc; 2940 int error; 2941 2942 sc = device_get_softc(dev); 2943 sc->dev = dev; 2944 sc->mem_rid = 0; 2945 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2946 &sc->mem_rid, RF_ACTIVE | RF_SHAREABLE); 2947 if (sc->mem == NULL) { 2948 device_printf(dev, "couldn't map memory\n"); 2949 error = ENXIO; 2950 goto fail; 2951 } 2952 2953 sc->bst = rman_get_bustag(sc->mem); 2954 sc->bsh = rman_get_bushandle(sc->mem); 2955 2956 bus_generic_probe(dev); 2957 bus_enumerate_hinted_children(dev); 2958 error = bus_generic_attach(dev); 2959 fail: 2960 return(error); 2961 } 2962 2963 static int 2964 rtmdio_detach(device_t dev) 2965 { 2966 return(0); 2967 } 2968 #endif 2969