1 /*- 2 * SPDX-License-Identifier: Beerware 3 * 4 * ---------------------------------------------------------------------------- 5 * "THE BEER-WARE LICENSE" (Revision 42): 6 * <[email protected]> wrote this file. As long as you retain this notice you 7 * can do whatever you want with this stuff. If we meet some day, and you think 8 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp 9 * ---------------------------------------------------------------------------- 10 */ 11 12 /* 13 * Driver for Siemens reference design card "Easy321-R1". 14 * 15 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC 16 * controller. 17 * 18 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't 19 * check it coming in. 20 * 21 * The FALC54 and MUNICH32X have far too many registers and weird modes for 22 * comfort, so I have not bothered typing it all into a "fooreg.h" file, 23 * you will (badly!) need the documentation anyway if you want to mess with 24 * this gadget. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Stuff to describe the MUNIC32X and FALC54 chips. 32 */ 33 34 #define M32_CHAN 32 /* We have 32 channels */ 35 #define M32_TS 32 /* We have 32 timeslots */ 36 37 #define NG_MN_NODE_TYPE "mn" 38 39 #include <sys/param.h> 40 #include <sys/kernel.h> 41 #include <sys/sysctl.h> 42 #include <sys/bus.h> 43 #include <sys/mbuf.h> 44 #include <sys/systm.h> 45 #include <sys/malloc.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include "pci_if.h" 50 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 54 #include <sys/rman.h> 55 56 #include <vm/vm.h> 57 #include <vm/pmap.h> 58 59 #include <netgraph/ng_message.h> 60 #include <netgraph/netgraph.h> 61 62 63 static int mn_maxlatency = 1000; 64 SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW, 65 &mn_maxlatency, 0, 66 "The number of milliseconds a packet is allowed to spend in the output queue. " 67 "If the output queue is longer than this number of milliseconds when the packet " 68 "arrives for output, the packet will be dropped." 69 ); 70 71 #ifndef NMN 72 /* Most machines don't support more than 4 busmaster PCI slots, if even that many */ 73 #define NMN 4 74 #endif 75 76 /* From: PEB 20321 data sheet, p187, table 22 */ 77 struct m32xreg { 78 u_int32_t conf, cmd, stat, imask; 79 u_int32_t fill10, piqba, piql, fill1c; 80 u_int32_t mode1, mode2, ccba, txpoll; 81 u_int32_t tiqba, tiql, riqba, riql; 82 u_int32_t lconf, lccba, fill48, ltran; 83 u_int32_t ltiqba, ltiql, lriqba, lriql; 84 u_int32_t lreg0, lreg1, lreg2, lreg3; 85 u_int32_t lreg4, lreg5, lre6, lstat; 86 u_int32_t gpdir, gpdata, gpod, fill8c; 87 u_int32_t ssccon, sscbr, ssctb, sscrb; 88 u_int32_t ssccse, sscim, fillab, fillac; 89 u_int32_t iomcon1, iomcon2, iomstat, fillbc; 90 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1; 91 u_int32_t iomtmo, iomrmo, filld8, filldc; 92 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3; 93 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7; 94 }; 95 96 /* From: PEB 2254 data sheet, p80, table 10 */ 97 struct f54wreg { 98 u_int16_t xfifo; 99 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2; 100 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 101 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 102 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 103 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 104 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3; 105 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 106 u_int8_t lim2, fill39[7]; 107 u_int8_t fill40[8]; 108 u_int8_t fill48[8]; 109 u_int8_t fill50[8]; 110 u_int8_t fill58[8]; 111 u_int8_t dec, fill61, test2, fill63[5]; 112 u_int8_t fill68[8]; 113 u_int8_t xs[16]; 114 }; 115 116 /* From: PEB 2254 data sheet, p117, table 10 */ 117 struct f54rreg { 118 u_int16_t rfifo; 119 u_int8_t fill2, mode, rah1, rah2, ral1, ral2; 120 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4; 121 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3; 122 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp; 123 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm; 124 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13; 125 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr; 126 u_int8_t lim2, fill39[7]; 127 u_int8_t fill40[8]; 128 u_int8_t fill48[4], frs0, frs1, rsw, rsp; 129 u_int16_t fec, cvc, cec1, ebc; 130 u_int16_t cec2, cec3; 131 u_int8_t rsa4, rsa5, rsa6, rsa7; 132 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis; 133 u_int16_t rbc; 134 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr; 135 u_int8_t rs[16]; 136 }; 137 138 /* Transmit & receive descriptors */ 139 struct trxd { 140 u_int32_t flags; 141 vm_offset_t next; 142 vm_offset_t data; 143 u_int32_t status; /* only used for receive */ 144 struct mbuf *m; /* software use only */ 145 struct trxd *vnext; /* software use only */ 146 }; 147 148 /* Channel specification */ 149 struct cspec { 150 u_int32_t flags; 151 vm_offset_t rdesc; 152 vm_offset_t tdesc; 153 u_int32_t itbs; 154 }; 155 156 struct m32_mem { 157 vm_offset_t csa; 158 u_int32_t ccb; 159 u_int32_t reserve1[2]; 160 u_int32_t ts[M32_TS]; 161 struct cspec cs[M32_CHAN]; 162 vm_offset_t crxd[M32_CHAN]; 163 vm_offset_t ctxd[M32_CHAN]; 164 }; 165 166 struct mn_softc; 167 struct sockaddr; 168 169 static int mn_probe(device_t self); 170 static int mn_attach(device_t self); 171 static void mn_create_channel(struct mn_softc *sc, int chan); 172 static int mn_reset(struct mn_softc *sc); 173 static struct trxd * mn_alloc_desc(void); 174 static void mn_free_desc(struct trxd *dp); 175 static void mn_intr(void *xsc); 176 static u_int32_t mn_parse_ts(const char *s, int *nbit); 177 #ifdef notyet 178 static void m32_dump(struct mn_softc *sc); 179 static void f54_dump(struct mn_softc *sc); 180 static void mn_fmt_ts(char *p, u_int32_t ts); 181 #endif /* notyet */ 182 static void f54_init(struct mn_softc *sc); 183 184 static ng_constructor_t ngmn_constructor; 185 static ng_rcvmsg_t ngmn_rcvmsg; 186 static ng_shutdown_t ngmn_shutdown; 187 static ng_newhook_t ngmn_newhook; 188 static ng_connect_t ngmn_connect; 189 static ng_rcvdata_t ngmn_rcvdata; 190 static ng_disconnect_t ngmn_disconnect; 191 192 static struct ng_type mntypestruct = { 193 .version = NG_ABI_VERSION, 194 .name = NG_MN_NODE_TYPE, 195 .constructor = ngmn_constructor, 196 .rcvmsg = ngmn_rcvmsg, 197 .shutdown = ngmn_shutdown, 198 .newhook = ngmn_newhook, 199 .connect = ngmn_connect, 200 .rcvdata = ngmn_rcvdata, 201 .disconnect = ngmn_disconnect, 202 }; 203 204 static MALLOC_DEFINE(M_MN, "mn", "Mx driver related"); 205 206 #define NIQB 64 207 208 struct schan { 209 enum {DOWN, UP} state; 210 struct mn_softc *sc; 211 int chan; 212 u_int32_t ts; 213 char name[8]; 214 struct trxd *r1, *rl; 215 struct trxd *x1, *xl; 216 hook_p hook; 217 218 time_t last_recv; 219 time_t last_rxerr; 220 time_t last_xmit; 221 222 u_long rx_error; 223 224 u_long short_error; 225 u_long crc_error; 226 u_long dribble_error; 227 u_long long_error; 228 u_long abort_error; 229 u_long overflow_error; 230 231 int last_error; 232 int prev_error; 233 234 u_long tx_pending; 235 u_long tx_limit; 236 }; 237 238 enum framing {WHOKNOWS, E1, E1U, T1, T1U}; 239 240 struct mn_softc { 241 int unit; 242 device_t dev; 243 struct resource *irq; 244 void *intrhand; 245 enum framing framing; 246 int nhooks; 247 void *m0v, *m1v; 248 vm_offset_t m0p, m1p; 249 struct m32xreg *m32x; 250 struct f54wreg *f54w; 251 struct f54rreg *f54r; 252 struct m32_mem m32_mem; 253 u_int32_t tiqb[NIQB]; 254 u_int32_t riqb[NIQB]; 255 u_int32_t piqb[NIQB]; 256 u_int32_t ltiqb[NIQB]; 257 u_int32_t lriqb[NIQB]; 258 char name[8]; 259 u_int32_t falc_irq, falc_state, framer_state; 260 struct schan *ch[M32_CHAN]; 261 char nodename[NG_NODESIZ]; 262 node_p node; 263 264 u_long cnt_fec; 265 u_long cnt_cvc; 266 u_long cnt_cec1; 267 u_long cnt_ebc; 268 u_long cnt_cec2; 269 u_long cnt_cec3; 270 u_long cnt_rbc; 271 }; 272 273 static int 274 ngmn_constructor(node_p node) 275 { 276 277 return (EINVAL); 278 } 279 280 static int 281 ngmn_shutdown(node_p nodep) 282 { 283 284 return (EINVAL); 285 } 286 287 static void 288 ngmn_config(node_p node, char *set, char *ret) 289 { 290 struct mn_softc *sc; 291 enum framing wframing; 292 293 sc = NG_NODE_PRIVATE(node); 294 295 if (set != NULL) { 296 if (!strncmp(set, "line ", 5)) { 297 wframing = sc->framing; 298 if (!strcmp(set, "line e1")) { 299 wframing = E1; 300 } else if (!strcmp(set, "line e1u")) { 301 wframing = E1U; 302 } else { 303 strcat(ret, "ENOGROK\n"); 304 return; 305 } 306 if (wframing == sc->framing) 307 return; 308 if (sc->nhooks > 0) { 309 sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks); 310 return; 311 } 312 sc->framing = wframing; 313 #if 1 314 f54_init(sc); 315 #else 316 mn_reset(sc); 317 #endif 318 } else { 319 printf("%s CONFIG SET [%s]\n", sc->nodename, set); 320 strcat(ret, "ENOGROK\n"); 321 return; 322 } 323 } 324 325 } 326 327 static int 328 ngmn_rcvmsg(node_p node, item_p item, hook_p lasthook) 329 { 330 struct mn_softc *sc; 331 struct ng_mesg *resp = NULL; 332 struct schan *sch; 333 char *s, *r; 334 int pos, i; 335 struct ng_mesg *msg; 336 337 NGI_GET_MSG(item, msg); 338 sc = NG_NODE_PRIVATE(node); 339 340 if (msg->header.typecookie != NGM_GENERIC_COOKIE) { 341 NG_FREE_ITEM(item); 342 NG_FREE_MSG(msg); 343 return (EINVAL); 344 } 345 346 if (msg->header.cmd != NGM_TEXT_CONFIG && 347 msg->header.cmd != NGM_TEXT_STATUS) { 348 NG_FREE_ITEM(item); 349 NG_FREE_MSG(msg); 350 return (EINVAL); 351 } 352 353 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE, 354 M_NOWAIT); 355 if (resp == NULL) { 356 NG_FREE_ITEM(item); 357 NG_FREE_MSG(msg); 358 return (ENOMEM); 359 } 360 361 if (msg->header.arglen) 362 s = (char *)msg->data; 363 else 364 s = NULL; 365 r = (char *)resp->data; 366 *r = '\0'; 367 368 if (msg->header.cmd == NGM_TEXT_CONFIG) { 369 ngmn_config(node, s, r); 370 resp->header.arglen = strlen(r) + 1; 371 NG_RESPOND_MSG(i, node, item, resp); 372 NG_FREE_MSG(msg); 373 return (0); 374 } 375 pos = 0; 376 pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20" 377 "\40LOS\37AIS\36LFA\35RRA" 378 "\34AUXP\33NMF\32LMFA\31frs0.0" 379 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 380 "\24TS16LFA\23frs1.2\22XLS\21XLO" 381 "\20RS1\17rsw.6\16RRA\15RY0" 382 "\14RY1\13RY2\12RY3\11RY4" 383 "\10SI1\7SI2\6rsp.5\5rsp.4" 384 "\4rsp.3\3RSIF\2RS13\1RS15"); 385 pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec); 386 pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc); 387 388 pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20" 389 "\40LOS\37AIS\36LFA\35RRA" 390 "\34AUXP\33NMF\32LMFA\31frs0.0" 391 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS" 392 "\24TS16LFA\23frs1.2\22XLS\21XLO" 393 "\20RS1\17rsw.6\16RRA\15RY0" 394 "\14RY1\13RY2\12RY3\11RY4" 395 "\10SI1\7SI2\6rsp.5\5rsp.4" 396 "\4rsp.3\3RSIF\2RS13\1RS15"); 397 pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20" 398 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 399 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 400 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 401 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 402 for (i = 0; i < M32_CHAN; i++) { 403 if (!sc->ch[i]) 404 continue; 405 sch = sc->ch[i]; 406 407 pos += sprintf(r + pos, " Chan %d <%s> ", 408 i, NG_HOOK_NAME(sch->hook)); 409 410 pos += sprintf(r + pos, " Last Rx: "); 411 if (sch->last_recv) 412 pos += sprintf(r + pos, "%lu s", 413 (unsigned long)(time_second - sch->last_recv)); 414 else 415 pos += sprintf(r + pos, "never"); 416 417 pos += sprintf(r + pos, ", last RxErr: "); 418 if (sch->last_rxerr) 419 pos += sprintf(r + pos, "%lu s", 420 (unsigned long)(time_second - sch->last_rxerr)); 421 else 422 pos += sprintf(r + pos, "never"); 423 424 pos += sprintf(r + pos, ", last Tx: "); 425 if (sch->last_xmit) 426 pos += sprintf(r + pos, "%lu s\n", 427 (unsigned long)(time_second - sch->last_xmit)); 428 else 429 pos += sprintf(r + pos, "never\n"); 430 431 pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error); 432 pos += sprintf(r + pos, " Short: %lu", sch->short_error); 433 pos += sprintf(r + pos, " CRC: %lu", sch->crc_error); 434 pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error); 435 pos += sprintf(r + pos, " Long: %lu", sch->long_error); 436 pos += sprintf(r + pos, " Abort: %lu", sch->abort_error); 437 pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error); 438 439 pos += sprintf(r + pos, " Last error: %b Prev error: %b\n", 440 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", 441 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN"); 442 pos += sprintf(r + pos, " Xmit bytes pending %ld\n", 443 sch->tx_pending); 444 } 445 resp->header.arglen = pos + 1; 446 447 /* Take care of synchronous response, if any */ 448 NG_RESPOND_MSG(i, node, item, resp); 449 NG_FREE_MSG(msg); 450 return (0); 451 } 452 453 static int 454 ngmn_newhook(node_p node, hook_p hook, const char *name) 455 { 456 u_int32_t ts, chan; 457 struct mn_softc *sc; 458 int nbit; 459 460 sc = NG_NODE_PRIVATE(node); 461 462 if (name[0] != 't' || name[1] != 's') 463 return (EINVAL); 464 465 ts = mn_parse_ts(name + 2, &nbit); 466 printf("%d bits %x\n", nbit, ts); 467 if (sc->framing == E1 && (ts & 1)) 468 return (EINVAL); 469 if (sc->framing == E1U && nbit != 32) 470 return (EINVAL); 471 if (ts == 0) 472 return (EINVAL); 473 if (sc->framing == E1) 474 chan = ffs(ts) - 1; 475 else 476 chan = 1; 477 if (!sc->ch[chan]) 478 mn_create_channel(sc, chan); 479 else if (sc->ch[chan]->state == UP) 480 return (EBUSY); 481 sc->ch[chan]->ts = ts; 482 sc->ch[chan]->hook = hook; 483 sc->ch[chan]->tx_limit = nbit * 8; 484 NG_HOOK_SET_PRIVATE(hook, sc->ch[chan]); 485 sc->nhooks++; 486 return(0); 487 } 488 489 490 static struct trxd *mn_desc_free; 491 492 static struct trxd * 493 mn_alloc_desc(void) 494 { 495 struct trxd *dp; 496 497 dp = mn_desc_free; 498 if (dp) 499 mn_desc_free = dp->vnext; 500 else 501 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT); 502 return (dp); 503 } 504 505 static void 506 mn_free_desc(struct trxd *dp) 507 { 508 dp->vnext = mn_desc_free; 509 mn_desc_free = dp; 510 } 511 512 static u_int32_t 513 mn_parse_ts(const char *s, int *nbit) 514 { 515 unsigned r; 516 int i, j; 517 char *p; 518 519 r = 0; 520 j = -1; 521 *nbit = 0; 522 while(*s) { 523 i = strtol(s, &p, 0); 524 if (i < 0 || i > 31) 525 return (0); 526 while (j != -1 && j < i) { 527 r |= 1 << j++; 528 (*nbit)++; 529 } 530 j = -1; 531 r |= 1 << i; 532 (*nbit)++; 533 if (*p == ',') { 534 s = p + 1; 535 continue; 536 } else if (*p == '-') { 537 j = i + 1; 538 s = p + 1; 539 continue; 540 } else if (!*p) { 541 break; 542 } else { 543 return (0); 544 } 545 } 546 return (r); 547 } 548 549 #ifdef notyet 550 static void 551 mn_fmt_ts(char *p, u_int32_t ts) 552 { 553 char *s; 554 int j; 555 556 s = ""; 557 ts &= 0xffffffff; 558 for (j = 0; j < 32; j++) { 559 if (!(ts & (1 << j))) 560 continue; 561 sprintf(p, "%s%d", s, j); 562 p += strlen(p); 563 s = ","; 564 if (!(ts & (1 << (j+1)))) 565 continue; 566 for (; j < 32; j++) 567 if (!(ts & (1 << (j+1)))) 568 break; 569 sprintf(p, "-%d", j); 570 p += strlen(p); 571 s = ","; 572 } 573 } 574 #endif /* notyet */ 575 576 /* 577 * OUTPUT 578 */ 579 580 static int 581 ngmn_rcvdata(hook_p hook, item_p item) 582 { 583 struct mbuf *m2; 584 struct trxd *dp, *dp2; 585 struct schan *sch; 586 struct mn_softc *sc; 587 int chan, pitch, len; 588 struct mbuf *m; 589 590 sch = NG_HOOK_PRIVATE(hook); 591 sc = sch->sc; 592 chan = sch->chan; 593 594 if (sch->state != UP) { 595 NG_FREE_ITEM(item); 596 return (0); 597 } 598 NGI_GET_M(item, m); 599 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) { 600 NG_FREE_M(m); 601 NG_FREE_ITEM(item); 602 return (0); 603 } 604 NG_FREE_ITEM(item); 605 pitch = 0; 606 m2 = m; 607 dp2 = sc->ch[chan]->xl; 608 len = m->m_pkthdr.len; 609 while (len) { 610 dp = mn_alloc_desc(); 611 if (!dp) { 612 pitch++; 613 m_freem(m); 614 sc->ch[chan]->xl = dp2; 615 dp = dp2->vnext; 616 while (dp) { 617 dp2 = dp->vnext; 618 mn_free_desc(dp); 619 dp = dp2; 620 } 621 sc->ch[chan]->xl->vnext = NULL; 622 break; 623 } 624 dp->data = vtophys(m2->m_data); 625 dp->flags = m2->m_len << 16; 626 dp->flags += 1; 627 len -= m2->m_len; 628 dp->next = vtophys(dp); 629 dp->vnext = NULL; 630 sc->ch[chan]->xl->next = vtophys(dp); 631 sc->ch[chan]->xl->vnext = dp; 632 sc->ch[chan]->xl = dp; 633 if (!len) { 634 dp->m = m; 635 dp->flags |= 0xc0000000; 636 dp2->flags &= ~0x40000000; 637 } else { 638 dp->m = NULL; 639 m2 = m2->m_next; 640 } 641 } 642 if (pitch) 643 printf("%s%d: Short on mem, pitched %d packets\n", 644 sc->name, chan, pitch); 645 else { 646 #if 0 647 printf("%d = %d + %d (%p)\n", 648 sch->tx_pending + m->m_pkthdr.len, 649 sch->tx_pending , m->m_pkthdr.len, m); 650 #endif 651 sch->tx_pending += m->m_pkthdr.len; 652 sc->m32x->txpoll &= ~(1 << chan); 653 } 654 return (0); 655 } 656 657 /* 658 * OPEN 659 */ 660 static int 661 ngmn_connect(hook_p hook) 662 { 663 int i, nts, chan; 664 struct trxd *dp, *dp2; 665 struct mbuf *m; 666 struct mn_softc *sc; 667 struct schan *sch; 668 u_int32_t u; 669 670 sch = NG_HOOK_PRIVATE(hook); 671 chan = sch->chan; 672 sc = sch->sc; 673 674 if (sch->state == UP) 675 return (0); 676 sch->state = UP; 677 678 /* Count and configure the timeslots for this channel */ 679 for (nts = i = 0; i < 32; i++) 680 if (sch->ts & (1 << i)) { 681 sc->m32_mem.ts[i] = 0x00ff00ff | 682 (chan << 24) | (chan << 8); 683 nts++; 684 } 685 686 /* Init the receiver & xmitter to HDLC */ 687 sc->m32_mem.cs[chan].flags = 0x80e90006; 688 /* Allocate two buffers per timeslot */ 689 if (nts == 32) 690 sc->m32_mem.cs[chan].itbs = 63; 691 else 692 sc->m32_mem.cs[chan].itbs = nts * 2; 693 694 /* Setup a transmit chain with one descriptor */ 695 /* XXX: we actually send a 1 byte packet */ 696 dp = mn_alloc_desc(); 697 MGETHDR(m, M_WAITOK, MT_DATA); 698 m->m_pkthdr.len = 0; 699 dp->m = m; 700 dp->flags = 0xc0000000 + (1 << 16); 701 dp->next = vtophys(dp); 702 dp->vnext = NULL; 703 dp->data = vtophys(sc->name); 704 sc->m32_mem.cs[chan].tdesc = vtophys(dp); 705 sc->ch[chan]->x1 = dp; 706 sc->ch[chan]->xl = dp; 707 708 /* Setup a receive chain with 5 + NTS descriptors */ 709 710 dp = mn_alloc_desc(); 711 m = NULL; 712 MGETHDR(m, M_WAITOK, MT_DATA); 713 MCLGET(m, M_WAITOK); 714 dp->m = m; 715 dp->data = vtophys(m->m_data); 716 dp->flags = 0x40000000; 717 dp->flags += 1600 << 16; 718 dp->next = vtophys(dp); 719 dp->vnext = NULL; 720 sc->ch[chan]->rl = dp; 721 722 for (i = 0; i < (nts + 10); i++) { 723 dp2 = dp; 724 dp = mn_alloc_desc(); 725 m = NULL; 726 MGETHDR(m, M_WAITOK, MT_DATA); 727 MCLGET(m, M_WAITOK); 728 dp->m = m; 729 dp->data = vtophys(m->m_data); 730 dp->flags = 0x00000000; 731 dp->flags += 1600 << 16; 732 dp->next = vtophys(dp2); 733 dp->vnext = dp2; 734 } 735 sc->m32_mem.cs[chan].rdesc = vtophys(dp); 736 sc->ch[chan]->r1 = dp; 737 738 /* Initialize this channel */ 739 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 740 sc->m32x->cmd = 0x1; 741 DELAY(1000); 742 u = sc->m32x->stat; 743 if (!(u & 1)) 744 printf("%s: init chan %d stat %08x\n", sc->name, chan, u); 745 sc->m32x->stat = 1; 746 747 return (0); 748 } 749 750 /* 751 * CLOSE 752 */ 753 static int 754 ngmn_disconnect(hook_p hook) 755 { 756 int chan, i; 757 struct mn_softc *sc; 758 struct schan *sch; 759 struct trxd *dp, *dp2; 760 u_int32_t u; 761 762 sch = NG_HOOK_PRIVATE(hook); 763 chan = sch->chan; 764 sc = sch->sc; 765 766 if (sch->state == DOWN) 767 return (0); 768 sch->state = DOWN; 769 770 /* Set receiver & transmitter off */ 771 sc->m32_mem.cs[chan].flags = 0x80920006; 772 sc->m32_mem.cs[chan].itbs = 0; 773 774 /* free the timeslots */ 775 for (i = 0; i < 32; i++) 776 if (sc->ch[chan]->ts & (1 << i)) 777 sc->m32_mem.ts[i] = 0x20002000; 778 779 /* Initialize this channel */ 780 sc->m32_mem.ccb = 0x00008000 + (chan << 8); 781 sc->m32x->cmd = 0x1; 782 DELAY(30); 783 u = sc->m32x->stat; 784 if (!(u & 1)) 785 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u); 786 sc->m32x->stat = 1; 787 788 /* Free all receive descriptors and mbufs */ 789 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) { 790 if (dp->m) 791 m_freem(dp->m); 792 sc->ch[chan]->r1 = dp2 = dp->vnext; 793 mn_free_desc(dp); 794 } 795 796 /* Free all transmit descriptors and mbufs */ 797 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) { 798 if (dp->m) { 799 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len; 800 m_freem(dp->m); 801 } 802 sc->ch[chan]->x1 = dp2 = dp->vnext; 803 mn_free_desc(dp); 804 } 805 sc->nhooks--; 806 return(0); 807 } 808 809 /* 810 * Create a new channel. 811 */ 812 static void 813 mn_create_channel(struct mn_softc *sc, int chan) 814 { 815 struct schan *sch; 816 817 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan], 818 M_MN, M_WAITOK | M_ZERO); 819 sch->sc = sc; 820 sch->state = DOWN; 821 sch->chan = chan; 822 sprintf(sch->name, "%s%d", sc->name, chan); 823 return; 824 } 825 826 #ifdef notyet 827 /* 828 * Dump Munich32x state 829 */ 830 static void 831 m32_dump(struct mn_softc *sc) 832 { 833 u_int32_t *tp4; 834 int i, j; 835 836 printf("mn%d: MUNICH32X dump\n", sc->unit); 837 tp4 = (u_int32_t *)sc->m0v; 838 for(j = 0; j < 64; j += 8) { 839 printf("%02x", j * sizeof *tp4); 840 for(i = 0; i < 8; i++) 841 printf(" %08x", tp4[i+j]); 842 printf("\n"); 843 } 844 for(j = 0; j < M32_CHAN; j++) { 845 if (!sc->ch[j]) 846 continue; 847 printf("CH%d: state %d ts %08x", 848 j, sc->ch[j]->state, sc->ch[j]->ts); 849 printf(" %08x %08x %08x %08x %08x %08x\n", 850 sc->m32_mem.cs[j].flags, 851 sc->m32_mem.cs[j].rdesc, 852 sc->m32_mem.cs[j].tdesc, 853 sc->m32_mem.cs[j].itbs, 854 sc->m32_mem.crxd[j], 855 sc->m32_mem.ctxd[j] ); 856 } 857 } 858 859 /* 860 * Dump Falch54 state 861 */ 862 static void 863 f54_dump(struct mn_softc *sc) 864 { 865 u_int8_t *tp1; 866 int i, j; 867 868 printf("%s: FALC54 dump\n", sc->name); 869 tp1 = (u_int8_t *)sc->m1v; 870 for(j = 0; j < 128; j += 16) { 871 printf("%s: %02x |", sc->name, j * sizeof *tp1); 872 for(i = 0; i < 16; i++) 873 printf(" %02x", tp1[i+j]); 874 printf("\n"); 875 } 876 } 877 #endif /* notyet */ 878 879 /* 880 * Init Munich32x 881 */ 882 static void 883 m32_init(struct mn_softc *sc) 884 { 885 886 sc->m32x->conf = 0x00000000; 887 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */ 888 #if 1 889 sc->m32x->mode2 = 0x00000081; 890 sc->m32x->txpoll = 0xffffffff; 891 #elif 1 892 sc->m32x->mode2 = 0x00000081; 893 sc->m32x->txpoll = 0xffffffff; 894 #else 895 sc->m32x->mode2 = 0x00000101; 896 #endif 897 sc->m32x->lconf = 0x6060009B; 898 sc->m32x->imask = 0x00000000; 899 } 900 901 /* 902 * Init the Falc54 903 */ 904 static void 905 f54_init(struct mn_softc *sc) 906 { 907 sc->f54w->ipc = 0x07; 908 909 sc->f54w->xpm0 = 0xbd; 910 sc->f54w->xpm1 = 0x03; 911 sc->f54w->xpm2 = 0x00; 912 913 sc->f54w->imr0 = 0x18; /* RMB, CASC */ 914 sc->f54w->imr1 = 0x08; /* XMB */ 915 sc->f54w->imr2 = 0x00; 916 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */ 917 sc->f54w->imr4 = 0x00; 918 919 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */ 920 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */ 921 if (sc->framing == E1) 922 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */ 923 else if (sc->framing == E1U) 924 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */ 925 926 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */ 927 sc->f54w->pcd = 0x0a; 928 sc->f54w->pcr = 0x15; 929 sc->f54w->xsw = 0x9f; /* fmr4 */ 930 if (sc->framing == E1) 931 sc->f54w->xsp = 0x1c; /* fmr5 */ 932 else if (sc->framing == E1U) 933 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */ 934 sc->f54w->xc0 = 0x07; 935 sc->f54w->xc1 = 0x3d; 936 sc->f54w->rc0 = 0x05; 937 sc->f54w->rc1 = 0x00; 938 sc->f54w->cmdr = 0x51; 939 } 940 941 static int 942 mn_reset(struct mn_softc *sc) 943 { 944 u_int32_t u; 945 int i; 946 947 sc->m32x->ccba = vtophys(&sc->m32_mem.csa); 948 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb); 949 950 bzero(sc->tiqb, sizeof sc->tiqb); 951 sc->m32x->tiqba = vtophys(&sc->tiqb); 952 sc->m32x->tiql = NIQB / 16 - 1; 953 954 bzero(sc->riqb, sizeof sc->riqb); 955 sc->m32x->riqba = vtophys(&sc->riqb); 956 sc->m32x->riql = NIQB / 16 - 1; 957 958 bzero(sc->ltiqb, sizeof sc->ltiqb); 959 sc->m32x->ltiqba = vtophys(&sc->ltiqb); 960 sc->m32x->ltiql = NIQB / 16 - 1; 961 962 bzero(sc->lriqb, sizeof sc->lriqb); 963 sc->m32x->lriqba = vtophys(&sc->lriqb); 964 sc->m32x->lriql = NIQB / 16 - 1; 965 966 bzero(sc->piqb, sizeof sc->piqb); 967 sc->m32x->piqba = vtophys(&sc->piqb); 968 sc->m32x->piql = NIQB / 16 - 1; 969 970 m32_init(sc); 971 f54_init(sc); 972 973 u = sc->m32x->stat; 974 sc->m32x->stat = u; 975 sc->m32_mem.ccb = 0x4; 976 sc->m32x->cmd = 0x1; 977 DELAY(1000); 978 u = sc->m32x->stat; 979 sc->m32x->stat = u; 980 981 /* set all timeslots to known state */ 982 for (i = 0; i < 32; i++) 983 sc->m32_mem.ts[i] = 0x20002000; 984 985 if (!(u & 1)) { 986 printf( 987 "mn%d: WARNING: Controller failed the PCI bus-master test.\n" 988 "mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n", 989 sc->unit, sc->unit); 990 return (0); 991 } 992 return (1); 993 } 994 995 /* 996 * FALC54 interrupt handling 997 */ 998 static void 999 f54_intr(struct mn_softc *sc) 1000 { 1001 unsigned g, u, s; 1002 1003 g = sc->f54r->gis; 1004 u = sc->f54r->isr0 << 24; 1005 u |= sc->f54r->isr1 << 16; 1006 u |= sc->f54r->isr2 << 8; 1007 u |= sc->f54r->isr3; 1008 sc->falc_irq = u; 1009 /* don't chat about the 1 sec heart beat */ 1010 if (u & ~0x40) { 1011 #if 0 1012 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20" 1013 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF" 1014 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR" 1015 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA" 1016 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP"); 1017 #endif 1018 s = sc->f54r->frs0 << 24; 1019 s |= sc->f54r->frs1 << 16; 1020 s |= sc->f54r->rsw << 8; 1021 s |= sc->f54r->rsp; 1022 sc->falc_state = s; 1023 1024 s &= ~0x01844038; /* undefined or static bits */ 1025 s &= ~0x00009fc7; /* bits we don't care about */ 1026 s &= ~0x00780000; /* XXX: TS16 related */ 1027 s &= ~0x06000000; /* XXX: Multiframe related */ 1028 #if 0 1029 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20" 1030 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0" 1031 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO" 1032 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4" 1033 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15"); 1034 #endif 1035 if (s != sc->framer_state) { 1036 #if 0 1037 for (i = 0; i < M32_CHAN; i++) { 1038 if (!sc->ch[i]) 1039 continue; 1040 sp = &sc->ch[i]->ifsppp; 1041 if (!(SP2IFP(sp)->if_flags & IFF_UP)) 1042 continue; 1043 if (s) 1044 timeout((timeout_t *)sp->pp_down, sp, 1 * hz); 1045 else 1046 timeout((timeout_t *)sp->pp_up, sp, 1 * hz); 1047 } 1048 #endif 1049 sc->framer_state = s; 1050 } 1051 } 1052 /* Once per second check error counters */ 1053 /* XXX: not clear if this is actually ok */ 1054 if (!(u & 0x40)) 1055 return; 1056 sc->cnt_fec += sc->f54r->fec; 1057 sc->cnt_cvc += sc->f54r->cvc; 1058 sc->cnt_cec1 += sc->f54r->cec1; 1059 sc->cnt_ebc += sc->f54r->ebc; 1060 sc->cnt_cec2 += sc->f54r->cec2; 1061 sc->cnt_cec3 += sc->f54r->cec3; 1062 sc->cnt_rbc += sc->f54r->rbc; 1063 } 1064 1065 /* 1066 * Transmit interrupt for one channel 1067 */ 1068 static void 1069 mn_tx_intr(struct mn_softc *sc, u_int32_t vector) 1070 { 1071 u_int32_t chan; 1072 struct trxd *dp; 1073 struct mbuf *m; 1074 1075 chan = vector & 0x1f; 1076 if (!sc->ch[chan]) 1077 return; 1078 if (sc->ch[chan]->state != UP) { 1079 printf("%s: tx_intr when not UP\n", sc->name); 1080 return; 1081 } 1082 for (;;) { 1083 dp = sc->ch[chan]->x1; 1084 if (vtophys(dp) == sc->m32_mem.ctxd[chan]) 1085 return; 1086 m = dp->m; 1087 if (m) { 1088 #if 0 1089 printf("%d = %d - %d (%p)\n", 1090 sc->ch[chan]->tx_pending - m->m_pkthdr.len, 1091 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m); 1092 #endif 1093 sc->ch[chan]->tx_pending -= m->m_pkthdr.len; 1094 m_freem(m); 1095 } 1096 sc->ch[chan]->last_xmit = time_second; 1097 sc->ch[chan]->x1 = dp->vnext; 1098 mn_free_desc(dp); 1099 } 1100 } 1101 1102 /* 1103 * Receive interrupt for one channel 1104 */ 1105 static void 1106 mn_rx_intr(struct mn_softc *sc, u_int32_t vector) 1107 { 1108 u_int32_t chan, err; 1109 struct trxd *dp; 1110 struct mbuf *m; 1111 struct schan *sch; 1112 1113 chan = vector & 0x1f; 1114 if (!sc->ch[chan]) 1115 return; 1116 sch = sc->ch[chan]; 1117 if (sch->state != UP) { 1118 printf("%s: rx_intr when not UP\n", sc->name); 1119 return; 1120 } 1121 vector &= ~0x1f; 1122 if (vector == 0x30000b00) 1123 sch->rx_error++; 1124 for (;;) { 1125 dp = sch->r1; 1126 if (vtophys(dp) == sc->m32_mem.crxd[chan]) 1127 return; 1128 m = dp->m; 1129 dp->m = NULL; 1130 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff; 1131 err = (dp->status >> 8) & 0xff; 1132 if (!err) { 1133 int error; 1134 NG_SEND_DATA_ONLY(error, sch->hook, m); 1135 sch->last_recv = time_second; 1136 /* we could be down by now... */ 1137 if (sch->state != UP) 1138 return; 1139 } else if (err & 0x40) { 1140 sch->short_error++; 1141 } else if (err & 0x10) { 1142 sch->crc_error++; 1143 } else if (err & 0x08) { 1144 sch->dribble_error++; 1145 } else if (err & 0x04) { 1146 sch->long_error++; 1147 } else if (err & 0x02) { 1148 sch->abort_error++; 1149 } else if (err & 0x01) { 1150 sch->overflow_error++; 1151 } 1152 if (err) { 1153 sch->last_rxerr = time_second; 1154 sch->prev_error = sch->last_error; 1155 sch->last_error = err; 1156 } 1157 1158 sc->ch[chan]->r1 = dp->vnext; 1159 1160 /* Replenish desc + mbuf supplies */ 1161 if (!m) { 1162 MGETHDR(m, M_NOWAIT, MT_DATA); 1163 if (m == NULL) { 1164 mn_free_desc(dp); 1165 return; /* ENOBUFS */ 1166 } 1167 if (!(MCLGET(m, M_NOWAIT))) { 1168 mn_free_desc(dp); 1169 m_freem(m); 1170 return; /* ENOBUFS */ 1171 } 1172 } 1173 dp->m = m; 1174 dp->data = vtophys(m->m_data); 1175 dp->flags = 0x40000000; 1176 dp->flags += 1600 << 16; 1177 dp->next = vtophys(dp); 1178 dp->vnext = NULL; 1179 sc->ch[chan]->rl->next = vtophys(dp); 1180 sc->ch[chan]->rl->vnext = dp; 1181 sc->ch[chan]->rl->flags &= ~0x40000000; 1182 sc->ch[chan]->rl = dp; 1183 } 1184 } 1185 1186 1187 /* 1188 * Interrupt handler 1189 */ 1190 1191 static void 1192 mn_intr(void *xsc) 1193 { 1194 struct mn_softc *sc; 1195 u_int32_t stat, lstat, u; 1196 int i, j; 1197 1198 sc = xsc; 1199 stat = sc->m32x->stat; 1200 lstat = sc->m32x->lstat; 1201 #if 0 1202 if (!stat && !(lstat & 2)) 1203 return; 1204 #endif 1205 1206 if (stat & ~0xc200) { 1207 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat); 1208 } 1209 1210 if ((stat & 0x200) || (lstat & 2)) 1211 f54_intr(sc); 1212 1213 for (j = i = 0; i < 64; i ++) { 1214 u = sc->riqb[i]; 1215 if (u) { 1216 sc->riqb[i] = 0; 1217 mn_rx_intr(sc, u); 1218 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00) 1219 continue; 1220 u &= ~0x30000400; /* bits we don't care about */ 1221 if ((u & ~0x1f) == 0x00000900) 1222 continue; 1223 if (!(u & ~0x1f)) 1224 continue; 1225 if (!j) 1226 printf("%s*: RIQB:", sc->name); 1227 printf(" [%d]=%08x", i, u); 1228 j++; 1229 } 1230 } 1231 if (j) 1232 printf("\n"); 1233 1234 for (j = i = 0; i < 64; i ++) { 1235 u = sc->tiqb[i]; 1236 if (u) { 1237 sc->tiqb[i] = 0; 1238 mn_tx_intr(sc, u); 1239 if ((u & ~0x1f) == 0x20000800) 1240 continue; 1241 u &= ~0x20000000; /* bits we don't care about */ 1242 if (!u) 1243 continue; 1244 if (!j) 1245 printf("%s*: TIQB:", sc->name); 1246 printf(" [%d]=%08x", i, u); 1247 j++; 1248 } 1249 } 1250 if (j) 1251 printf("\n"); 1252 sc->m32x->stat = stat; 1253 } 1254 1255 /* 1256 * PCI initialization stuff 1257 */ 1258 1259 static int 1260 mn_probe (device_t self) 1261 { 1262 u_int id = pci_get_devid(self); 1263 1264 if (sizeof (struct m32xreg) != 256) { 1265 printf("MN: sizeof(struct m32xreg) = %zd, should have been 256\n", sizeof (struct m32xreg)); 1266 return (ENXIO); 1267 } 1268 if (sizeof (struct f54rreg) != 128) { 1269 printf("MN: sizeof(struct f54rreg) = %zd, should have been 128\n", sizeof (struct f54rreg)); 1270 return (ENXIO); 1271 } 1272 if (sizeof (struct f54wreg) != 128) { 1273 printf("MN: sizeof(struct f54wreg) = %zd, should have been 128\n", sizeof (struct f54wreg)); 1274 return (ENXIO); 1275 } 1276 1277 if (id != 0x2101110a) 1278 return (ENXIO); 1279 1280 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller"); 1281 return (BUS_PROBE_DEFAULT); 1282 } 1283 1284 static int 1285 mn_attach (device_t self) 1286 { 1287 struct mn_softc *sc; 1288 u_int32_t u; 1289 u_int32_t ver; 1290 static int once; 1291 int rid, error; 1292 struct resource *res; 1293 1294 if (!once) { 1295 if (ng_newtype(&mntypestruct)) 1296 printf("ng_newtype failed\n"); 1297 once++; 1298 } 1299 1300 sc = (struct mn_softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO); 1301 device_set_softc(self, sc); 1302 1303 sc->dev = self; 1304 sc->unit = device_get_unit(self); 1305 sc->framing = E1; 1306 sprintf(sc->name, "mn%d", sc->unit); 1307 1308 rid = PCIR_BAR(0); 1309 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 1310 if (res == NULL) { 1311 device_printf(self, "Could not map memory\n"); 1312 free(sc, M_MN); 1313 return ENXIO; 1314 } 1315 sc->m0v = rman_get_virtual(res); 1316 sc->m0p = rman_get_start(res); 1317 1318 rid = PCIR_BAR(1); 1319 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 1320 if (res == NULL) { 1321 device_printf(self, "Could not map memory\n"); 1322 free(sc, M_MN); 1323 return ENXIO; 1324 } 1325 sc->m1v = rman_get_virtual(res); 1326 sc->m1p = rman_get_start(res); 1327 1328 /* Allocate interrupt */ 1329 rid = 0; 1330 sc->irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 1331 RF_SHAREABLE | RF_ACTIVE); 1332 1333 if (sc->irq == NULL) { 1334 printf("couldn't map interrupt\n"); 1335 free(sc, M_MN); 1336 return(ENXIO); 1337 } 1338 1339 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, NULL, mn_intr, sc, &sc->intrhand); 1340 1341 if (error) { 1342 printf("couldn't set up irq\n"); 1343 free(sc, M_MN); 1344 return(ENXIO); 1345 } 1346 1347 u = pci_read_config(self, PCIR_COMMAND, 2); 1348 printf("%x\n", u); 1349 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN, 2); 1350 #if 0 1351 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4); 1352 #endif 1353 u = pci_read_config(self, PCIR_COMMAND, 1); 1354 printf("%x\n", u); 1355 1356 ver = pci_get_revid(self); 1357 1358 sc->m32x = (struct m32xreg *) sc->m0v; 1359 sc->f54w = (struct f54wreg *) sc->m1v; 1360 sc->f54r = (struct f54rreg *) sc->m1v; 1361 1362 /* We must reset before poking at FALC54 registers */ 1363 u = mn_reset(sc); 1364 if (!u) 1365 return (0); 1366 1367 printf("mn%d: Munich32X", sc->unit); 1368 switch (ver) { 1369 case 0x13: 1370 printf(" Rev 2.2"); 1371 break; 1372 default: 1373 printf(" Rev 0x%x\n", ver); 1374 } 1375 printf(", Falc54"); 1376 switch (sc->f54r->vstr) { 1377 case 0: 1378 printf(" Rev < 1.3\n"); 1379 break; 1380 case 1: 1381 printf(" Rev 1.3\n"); 1382 break; 1383 case 2: 1384 printf(" Rev 1.4\n"); 1385 break; 1386 case 0x10: 1387 printf("-LH Rev 1.1\n"); 1388 break; 1389 case 0x13: 1390 printf("-LH Rev 1.3\n"); 1391 break; 1392 default: 1393 printf(" Rev 0x%x\n", sc->f54r->vstr); 1394 } 1395 gone_in_dev(self, 14, "sync serial (T1/E1) driver"); 1396 1397 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) { 1398 printf("ng_make_node_common failed\n"); 1399 return (0); 1400 } 1401 NG_NODE_SET_PRIVATE(sc->node, sc); 1402 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit); 1403 if (ng_name_node(sc->node, sc->nodename)) { 1404 NG_NODE_UNREF(sc->node); 1405 return (0); 1406 } 1407 1408 return (0); 1409 } 1410 1411 1412 static device_method_t mn_methods[] = { 1413 /* Device interface */ 1414 DEVMETHOD(device_probe, mn_probe), 1415 DEVMETHOD(device_attach, mn_attach), 1416 DEVMETHOD(device_suspend, bus_generic_suspend), 1417 DEVMETHOD(device_resume, bus_generic_resume), 1418 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1419 1420 DEVMETHOD_END 1421 }; 1422 1423 static driver_t mn_driver = { 1424 "mn", 1425 mn_methods, 1426 0 1427 }; 1428 1429 static devclass_t mn_devclass; 1430 1431 DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0); 1432