1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _LINUX_PCI_H_ 32 #define _LINUX_PCI_H_ 33 34 #define CONFIG_PCI_MSI 35 36 #include <linux/types.h> 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/nv.h> 41 #include <sys/pciio.h> 42 #include <sys/rman.h> 43 #include <sys/bus.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pci_private.h> 47 48 #include <machine/resource.h> 49 50 #include <linux/list.h> 51 #include <linux/dmapool.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/compiler.h> 54 #include <linux/errno.h> 55 #include <asm/atomic.h> 56 #include <linux/device.h> 57 58 struct pci_device_id { 59 uint32_t vendor; 60 uint32_t device; 61 uint32_t subvendor; 62 uint32_t subdevice; 63 uint32_t class; 64 uint32_t class_mask; 65 uintptr_t driver_data; 66 }; 67 68 #define MODULE_DEVICE_TABLE(bus, table) 69 70 #define PCI_BASE_CLASS_DISPLAY 0x03 71 #define PCI_CLASS_DISPLAY_VGA 0x0300 72 #define PCI_CLASS_DISPLAY_OTHER 0x0380 73 #define PCI_BASE_CLASS_BRIDGE 0x06 74 #define PCI_CLASS_BRIDGE_ISA 0x0601 75 76 #define PCI_ANY_ID -1U 77 #define PCI_VENDOR_ID_APPLE 0x106b 78 #define PCI_VENDOR_ID_ASUSTEK 0x1043 79 #define PCI_VENDOR_ID_ATI 0x1002 80 #define PCI_VENDOR_ID_DELL 0x1028 81 #define PCI_VENDOR_ID_HP 0x103c 82 #define PCI_VENDOR_ID_IBM 0x1014 83 #define PCI_VENDOR_ID_INTEL 0x8086 84 #define PCI_VENDOR_ID_MELLANOX 0x15b3 85 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 86 #define PCI_VENDOR_ID_SERVERWORKS 0x1166 87 #define PCI_VENDOR_ID_SONY 0x104d 88 #define PCI_VENDOR_ID_TOPSPIN 0x1867 89 #define PCI_VENDOR_ID_VIA 0x1106 90 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 91 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 92 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 93 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 94 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 95 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 96 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 97 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 98 #define PCI_SUBDEVICE_ID_QEMU 0x1100 99 100 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 101 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 102 #define PCI_FUNC(devfn) ((devfn) & 0x07) 103 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 104 105 #define PCI_VDEVICE(_vendor, _device) \ 106 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 108 #define PCI_DEVICE(_vendor, _device) \ 109 .vendor = (_vendor), .device = (_device), \ 110 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 111 112 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 113 114 #define PCI_VENDOR_ID PCIR_DEVVENDOR 115 #define PCI_COMMAND PCIR_COMMAND 116 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 117 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 118 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 119 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 120 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 121 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 122 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 123 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 124 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 125 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 126 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 127 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 128 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 129 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 130 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 131 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 132 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 133 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 134 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 135 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 136 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 137 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 138 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 139 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 140 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 141 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 142 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 143 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 144 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 145 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 146 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 147 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 148 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 149 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 150 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 151 152 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 153 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 154 #define PCI_EXP_DEVSTA_TRPND 0x0020 155 156 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 157 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 158 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 159 160 enum pci_bus_speed { 161 PCI_SPEED_UNKNOWN = -1, 162 PCIE_SPEED_2_5GT, 163 PCIE_SPEED_5_0GT, 164 PCIE_SPEED_8_0GT, 165 PCIE_SPEED_16_0GT, 166 }; 167 168 enum pcie_link_width { 169 PCIE_LNK_WIDTH_RESRV = 0x00, 170 PCIE_LNK_X1 = 0x01, 171 PCIE_LNK_X2 = 0x02, 172 PCIE_LNK_X4 = 0x04, 173 PCIE_LNK_X8 = 0x08, 174 PCIE_LNK_X12 = 0x0c, 175 PCIE_LNK_X16 = 0x10, 176 PCIE_LNK_X32 = 0x20, 177 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 178 }; 179 180 typedef int pci_power_t; 181 182 #define PCI_D0 PCI_POWERSTATE_D0 183 #define PCI_D1 PCI_POWERSTATE_D1 184 #define PCI_D2 PCI_POWERSTATE_D2 185 #define PCI_D3hot PCI_POWERSTATE_D3 186 #define PCI_D3cold 4 187 188 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 189 190 struct pci_dev; 191 192 struct pci_driver { 193 struct list_head links; 194 char *name; 195 const struct pci_device_id *id_table; 196 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 197 void (*remove)(struct pci_dev *dev); 198 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 199 int (*resume) (struct pci_dev *dev); /* Device woken up */ 200 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 201 driver_t bsddriver; 202 devclass_t bsdclass; 203 struct device_driver driver; 204 const struct pci_error_handlers *err_handler; 205 bool isdrm; 206 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 207 const nvlist_t *pf_config); 208 void (*bsd_iov_uninit)(device_t dev); 209 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 210 const nvlist_t *vf_config); 211 }; 212 213 struct pci_bus { 214 struct pci_dev *self; 215 int domain; 216 int number; 217 }; 218 219 extern struct list_head pci_drivers; 220 extern struct list_head pci_devices; 221 extern spinlock_t pci_lock; 222 223 #define __devexit_p(x) x 224 225 struct pci_mmio_region { 226 TAILQ_ENTRY(pci_mmio_region) next; 227 struct resource *res; 228 int rid; 229 int type; 230 }; 231 232 struct pci_dev { 233 struct device dev; 234 struct list_head links; 235 struct pci_driver *pdrv; 236 struct pci_bus *bus; 237 uint16_t device; 238 uint16_t vendor; 239 uint16_t subsystem_vendor; 240 uint16_t subsystem_device; 241 unsigned int irq; 242 unsigned int devfn; 243 uint32_t class; 244 uint8_t revision; 245 bool msi_enabled; 246 phys_addr_t rom; 247 size_t romlen; 248 249 TAILQ_HEAD(, pci_mmio_region) mmio; 250 }; 251 252 static inline struct resource_list_entry * 253 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 254 { 255 struct pci_devinfo *dinfo; 256 struct resource_list *rl; 257 258 dinfo = device_get_ivars(pdev->dev.bsddev); 259 rl = &dinfo->resources; 260 return resource_list_find(rl, type, rid); 261 } 262 263 static inline struct resource_list_entry * 264 linux_pci_get_bar(struct pci_dev *pdev, int bar) 265 { 266 struct resource_list_entry *rle; 267 268 bar = PCIR_BAR(bar); 269 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 270 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 271 return (rle); 272 } 273 274 static inline struct device * 275 linux_pci_find_irq_dev(unsigned int irq) 276 { 277 struct pci_dev *pdev; 278 struct device *found; 279 280 found = NULL; 281 spin_lock(&pci_lock); 282 list_for_each_entry(pdev, &pci_devices, links) { 283 if (irq == pdev->dev.irq || 284 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 285 found = &pdev->dev; 286 break; 287 } 288 } 289 spin_unlock(&pci_lock); 290 return (found); 291 } 292 293 static inline int 294 pci_resource_type(struct pci_dev *pdev, int bar) 295 { 296 struct pci_map *pm; 297 298 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 299 if (!pm) 300 return (-1); 301 302 if (PCI_BAR_IO(pm->pm_value)) 303 return (SYS_RES_IOPORT); 304 else 305 return (SYS_RES_MEMORY); 306 } 307 308 /* 309 * All drivers just seem to want to inspect the type not flags. 310 */ 311 static inline int 312 pci_resource_flags(struct pci_dev *pdev, int bar) 313 { 314 int type; 315 316 type = pci_resource_type(pdev, bar); 317 if (type < 0) 318 return (0); 319 return (1 << type); 320 } 321 322 static inline const char * 323 pci_name(struct pci_dev *d) 324 { 325 326 return device_get_desc(d->dev.bsddev); 327 } 328 329 static inline void * 330 pci_get_drvdata(struct pci_dev *pdev) 331 { 332 333 return dev_get_drvdata(&pdev->dev); 334 } 335 336 static inline void 337 pci_set_drvdata(struct pci_dev *pdev, void *data) 338 { 339 340 dev_set_drvdata(&pdev->dev, data); 341 } 342 343 static __inline void 344 pci_dev_put(struct pci_dev *pdev) 345 { 346 347 if (pdev != NULL) 348 put_device(&pdev->dev); 349 } 350 351 static inline int 352 pci_enable_device(struct pci_dev *pdev) 353 { 354 355 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 356 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 357 return (0); 358 } 359 360 static inline void 361 pci_disable_device(struct pci_dev *pdev) 362 { 363 364 pci_disable_busmaster(pdev->dev.bsddev); 365 } 366 367 static inline int 368 pci_set_master(struct pci_dev *pdev) 369 { 370 371 pci_enable_busmaster(pdev->dev.bsddev); 372 return (0); 373 } 374 375 static inline int 376 pci_set_power_state(struct pci_dev *pdev, int state) 377 { 378 379 pci_set_powerstate(pdev->dev.bsddev, state); 380 return (0); 381 } 382 383 static inline int 384 pci_clear_master(struct pci_dev *pdev) 385 { 386 387 pci_disable_busmaster(pdev->dev.bsddev); 388 return (0); 389 } 390 391 static inline int 392 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 393 { 394 int rid; 395 int type; 396 397 type = pci_resource_type(pdev, bar); 398 if (type < 0) 399 return (-ENODEV); 400 rid = PCIR_BAR(bar); 401 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 402 RF_ACTIVE) == NULL) 403 return (-EINVAL); 404 return (0); 405 } 406 407 static inline void 408 pci_release_region(struct pci_dev *pdev, int bar) 409 { 410 struct resource_list_entry *rle; 411 412 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 413 return; 414 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 415 } 416 417 static inline void 418 pci_release_regions(struct pci_dev *pdev) 419 { 420 int i; 421 422 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 423 pci_release_region(pdev, i); 424 } 425 426 static inline int 427 pci_request_regions(struct pci_dev *pdev, const char *res_name) 428 { 429 int error; 430 int i; 431 432 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 433 error = pci_request_region(pdev, i, res_name); 434 if (error && error != -ENODEV) { 435 pci_release_regions(pdev); 436 return (error); 437 } 438 } 439 return (0); 440 } 441 442 static inline void 443 pci_disable_msix(struct pci_dev *pdev) 444 { 445 446 pci_release_msi(pdev->dev.bsddev); 447 448 /* 449 * The MSIX IRQ numbers associated with this PCI device are no 450 * longer valid and might be re-assigned. Make sure 451 * linux_pci_find_irq_dev() does no longer see them by 452 * resetting their references to zero: 453 */ 454 pdev->dev.irq_start = 0; 455 pdev->dev.irq_end = 0; 456 } 457 458 #define pci_disable_msi(pdev) \ 459 linux_pci_disable_msi(pdev) 460 461 static inline void 462 linux_pci_disable_msi(struct pci_dev *pdev) 463 { 464 465 pci_release_msi(pdev->dev.bsddev); 466 467 pdev->dev.irq_start = 0; 468 pdev->dev.irq_end = 0; 469 pdev->irq = pdev->dev.irq; 470 pdev->msi_enabled = false; 471 } 472 473 #define pci_free_irq_vectors(pdev) \ 474 linux_pci_disable_msi(pdev) 475 476 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 477 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 478 479 static inline bus_addr_t 480 pci_bus_address(struct pci_dev *pdev, int bar) 481 { 482 483 return (pci_resource_start(pdev, bar)); 484 } 485 486 #define PCI_CAP_ID_EXP PCIY_EXPRESS 487 #define PCI_CAP_ID_PCIX PCIY_PCIX 488 #define PCI_CAP_ID_AGP PCIY_AGP 489 #define PCI_CAP_ID_PM PCIY_PMG 490 491 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 492 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 493 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 494 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 495 #define PCI_EXP_LNKSTA PCIER_LINK_STA 496 497 static inline int 498 pci_find_capability(struct pci_dev *pdev, int capid) 499 { 500 int reg; 501 502 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 503 return (0); 504 return (reg); 505 } 506 507 static inline int pci_pcie_cap(struct pci_dev *dev) 508 { 509 return pci_find_capability(dev, PCI_CAP_ID_EXP); 510 } 511 512 static inline int 513 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 514 { 515 516 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 517 return (0); 518 } 519 520 static inline int 521 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 522 { 523 524 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 525 return (0); 526 } 527 528 static inline int 529 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 530 { 531 532 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 533 return (0); 534 } 535 536 static inline int 537 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 538 { 539 540 pci_write_config(pdev->dev.bsddev, where, val, 1); 541 return (0); 542 } 543 544 static inline int 545 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 546 { 547 548 pci_write_config(pdev->dev.bsddev, where, val, 2); 549 return (0); 550 } 551 552 static inline int 553 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 554 { 555 556 pci_write_config(pdev->dev.bsddev, where, val, 4); 557 return (0); 558 } 559 560 int linux_pci_register_driver(struct pci_driver *pdrv); 561 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 562 void linux_pci_unregister_driver(struct pci_driver *pdrv); 563 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 564 565 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 566 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 567 568 struct msix_entry { 569 int entry; 570 int vector; 571 }; 572 573 /* 574 * Enable msix, positive errors indicate actual number of available 575 * vectors. Negative errors are failures. 576 * 577 * NB: define added to prevent this definition of pci_enable_msix from 578 * clashing with the native FreeBSD version. 579 */ 580 #define pci_enable_msix(...) \ 581 linux_pci_enable_msix(__VA_ARGS__) 582 583 static inline int 584 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 585 { 586 struct resource_list_entry *rle; 587 int error; 588 int avail; 589 int i; 590 591 avail = pci_msix_count(pdev->dev.bsddev); 592 if (avail < nreq) { 593 if (avail == 0) 594 return -EINVAL; 595 return avail; 596 } 597 avail = nreq; 598 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 599 return error; 600 /* 601 * Handle case where "pci_alloc_msix()" may allocate less 602 * interrupts than available and return with no error: 603 */ 604 if (avail < nreq) { 605 pci_release_msi(pdev->dev.bsddev); 606 return avail; 607 } 608 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 609 pdev->dev.irq_start = rle->start; 610 pdev->dev.irq_end = rle->start + avail; 611 for (i = 0; i < nreq; i++) 612 entries[i].vector = pdev->dev.irq_start + i; 613 return (0); 614 } 615 616 #define pci_enable_msix_range(...) \ 617 linux_pci_enable_msix_range(__VA_ARGS__) 618 619 static inline int 620 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 621 int minvec, int maxvec) 622 { 623 int nvec = maxvec; 624 int rc; 625 626 if (maxvec < minvec) 627 return (-ERANGE); 628 629 do { 630 rc = pci_enable_msix(dev, entries, nvec); 631 if (rc < 0) { 632 return (rc); 633 } else if (rc > 0) { 634 if (rc < minvec) 635 return (-ENOSPC); 636 nvec = rc; 637 } 638 } while (rc); 639 return (nvec); 640 } 641 642 #define pci_enable_msi(pdev) \ 643 linux_pci_enable_msi(pdev) 644 645 static inline int 646 pci_enable_msi(struct pci_dev *pdev) 647 { 648 struct resource_list_entry *rle; 649 int error; 650 int avail; 651 652 avail = pci_msi_count(pdev->dev.bsddev); 653 if (avail < 1) 654 return -EINVAL; 655 656 avail = 1; /* this function only enable one MSI IRQ */ 657 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 658 return error; 659 660 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 661 pdev->dev.irq_start = rle->start; 662 pdev->dev.irq_end = rle->start + avail; 663 pdev->irq = rle->start; 664 pdev->msi_enabled = true; 665 return (0); 666 } 667 668 static inline int 669 pci_channel_offline(struct pci_dev *pdev) 670 { 671 672 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 673 } 674 675 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 676 { 677 return -ENODEV; 678 } 679 static inline void pci_disable_sriov(struct pci_dev *dev) 680 { 681 } 682 683 static inline void * 684 pci_iomap(struct pci_dev *dev, int mmio_bar, int mmio_size __unused) 685 { 686 struct pci_mmio_region *mmio; 687 688 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 689 mmio->rid = PCIR_BAR(mmio_bar); 690 mmio->type = pci_resource_type(dev, mmio_bar); 691 mmio->res = bus_alloc_resource_any(dev->dev.bsddev, mmio->type, 692 &mmio->rid, RF_ACTIVE); 693 if (mmio->res == NULL) { 694 free(mmio, M_DEVBUF); 695 return (NULL); 696 } 697 TAILQ_INSERT_TAIL(&dev->mmio, mmio, next); 698 699 return ((void *)rman_get_bushandle(mmio->res)); 700 } 701 702 static inline void 703 pci_iounmap(struct pci_dev *dev, void *res) 704 { 705 struct pci_mmio_region *mmio, *p; 706 707 TAILQ_FOREACH_SAFE(mmio, &dev->mmio, next, p) { 708 if (res != (void *)rman_get_bushandle(mmio->res)) 709 continue; 710 bus_release_resource(dev->dev.bsddev, 711 mmio->type, mmio->rid, mmio->res); 712 TAILQ_REMOVE(&dev->mmio, mmio, next); 713 free(mmio, M_DEVBUF); 714 return; 715 } 716 } 717 718 static inline void 719 lkpi_pci_save_state(struct pci_dev *pdev) 720 { 721 722 pci_save_state(pdev->dev.bsddev); 723 } 724 725 static inline void 726 lkpi_pci_restore_state(struct pci_dev *pdev) 727 { 728 729 pci_restore_state(pdev->dev.bsddev); 730 } 731 732 #define pci_save_state(dev) lkpi_pci_save_state(dev) 733 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 734 735 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 736 const struct pci_device_id _table[] __devinitdata 737 738 /* XXX This should not be necessary. */ 739 #define pcix_set_mmrbc(d, v) 0 740 #define pcix_get_max_mmrbc(d) 0 741 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 742 743 #define PCI_DMA_BIDIRECTIONAL 0 744 #define PCI_DMA_TODEVICE 1 745 #define PCI_DMA_FROMDEVICE 2 746 #define PCI_DMA_NONE 3 747 748 #define pci_pool dma_pool 749 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 750 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 751 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 752 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 753 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 754 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 755 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 756 _size, _vaddr, _dma_handle) 757 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 758 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 759 _sg, _nents, (enum dma_data_direction)_dir) 760 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 761 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 762 (_ptr), (_size), (enum dma_data_direction)_dir) 763 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 764 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 765 _addr, _size, (enum dma_data_direction)_dir) 766 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 767 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 768 _sg, _nents, (enum dma_data_direction)_dir) 769 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 770 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 771 _offset, _size, (enum dma_data_direction)_dir) 772 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 773 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 774 _dma_address, _size, (enum dma_data_direction)_dir) 775 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 776 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 777 dma_mapping_error(&(_pdev)->dev, _dma_addr) 778 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 779 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 780 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 781 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 782 #define pci_unmap_addr dma_unmap_addr 783 #define pci_unmap_addr_set dma_unmap_addr_set 784 #define pci_unmap_len dma_unmap_len 785 #define pci_unmap_len_set dma_unmap_len_set 786 787 typedef unsigned int __bitwise pci_channel_state_t; 788 typedef unsigned int __bitwise pci_ers_result_t; 789 790 enum pci_channel_state { 791 pci_channel_io_normal = 1, 792 pci_channel_io_frozen = 2, 793 pci_channel_io_perm_failure = 3, 794 }; 795 796 enum pci_ers_result { 797 PCI_ERS_RESULT_NONE = 1, 798 PCI_ERS_RESULT_CAN_RECOVER = 2, 799 PCI_ERS_RESULT_NEED_RESET = 3, 800 PCI_ERS_RESULT_DISCONNECT = 4, 801 PCI_ERS_RESULT_RECOVERED = 5, 802 }; 803 804 /* PCI bus error event callbacks */ 805 struct pci_error_handlers { 806 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 807 enum pci_channel_state error); 808 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 809 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 810 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 811 void (*resume)(struct pci_dev *dev); 812 }; 813 814 /* FreeBSD does not support SRIOV - yet */ 815 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 816 { 817 return dev; 818 } 819 820 static inline bool pci_is_pcie(struct pci_dev *dev) 821 { 822 return !!pci_pcie_cap(dev); 823 } 824 825 static inline u16 pcie_flags_reg(struct pci_dev *dev) 826 { 827 int pos; 828 u16 reg16; 829 830 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 831 if (!pos) 832 return 0; 833 834 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 835 836 return reg16; 837 } 838 839 static inline int pci_pcie_type(struct pci_dev *dev) 840 { 841 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 842 } 843 844 static inline int pcie_cap_version(struct pci_dev *dev) 845 { 846 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 847 } 848 849 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 850 { 851 int type = pci_pcie_type(dev); 852 853 return pcie_cap_version(dev) > 1 || 854 type == PCI_EXP_TYPE_ROOT_PORT || 855 type == PCI_EXP_TYPE_ENDPOINT || 856 type == PCI_EXP_TYPE_LEG_END; 857 } 858 859 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 860 { 861 return true; 862 } 863 864 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 865 { 866 int type = pci_pcie_type(dev); 867 868 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 869 (type == PCI_EXP_TYPE_DOWNSTREAM && 870 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 871 } 872 873 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 874 { 875 int type = pci_pcie_type(dev); 876 877 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 878 type == PCI_EXP_TYPE_RC_EC; 879 } 880 881 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 882 { 883 if (!pci_is_pcie(dev)) 884 return false; 885 886 switch (pos) { 887 case PCI_EXP_FLAGS_TYPE: 888 return true; 889 case PCI_EXP_DEVCAP: 890 case PCI_EXP_DEVCTL: 891 case PCI_EXP_DEVSTA: 892 return pcie_cap_has_devctl(dev); 893 case PCI_EXP_LNKCAP: 894 case PCI_EXP_LNKCTL: 895 case PCI_EXP_LNKSTA: 896 return pcie_cap_has_lnkctl(dev); 897 case PCI_EXP_SLTCAP: 898 case PCI_EXP_SLTCTL: 899 case PCI_EXP_SLTSTA: 900 return pcie_cap_has_sltctl(dev); 901 case PCI_EXP_RTCTL: 902 case PCI_EXP_RTCAP: 903 case PCI_EXP_RTSTA: 904 return pcie_cap_has_rtctl(dev); 905 case PCI_EXP_DEVCAP2: 906 case PCI_EXP_DEVCTL2: 907 case PCI_EXP_LNKCAP2: 908 case PCI_EXP_LNKCTL2: 909 case PCI_EXP_LNKSTA2: 910 return pcie_cap_version(dev) > 1; 911 default: 912 return false; 913 } 914 } 915 916 static inline int 917 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 918 { 919 if (pos & 3) 920 return -EINVAL; 921 922 if (!pcie_capability_reg_implemented(dev, pos)) 923 return -EINVAL; 924 925 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 926 } 927 928 static inline int 929 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 930 { 931 if (pos & 3) 932 return -EINVAL; 933 934 if (!pcie_capability_reg_implemented(dev, pos)) 935 return -EINVAL; 936 937 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 938 } 939 940 static inline int 941 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 942 { 943 if (pos & 1) 944 return -EINVAL; 945 946 if (!pcie_capability_reg_implemented(dev, pos)) 947 return 0; 948 949 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 950 } 951 952 static inline int pcie_get_minimum_link(struct pci_dev *dev, 953 enum pci_bus_speed *speed, enum pcie_link_width *width) 954 { 955 *speed = PCI_SPEED_UNKNOWN; 956 *width = PCIE_LNK_WIDTH_UNKNOWN; 957 return (0); 958 } 959 960 static inline int 961 pci_num_vf(struct pci_dev *dev) 962 { 963 return (0); 964 } 965 966 static inline enum pci_bus_speed 967 pcie_get_speed_cap(struct pci_dev *dev) 968 { 969 device_t root; 970 uint32_t lnkcap, lnkcap2; 971 int error, pos; 972 973 root = device_get_parent(dev->dev.bsddev); 974 if (root == NULL) 975 return (PCI_SPEED_UNKNOWN); 976 root = device_get_parent(root); 977 if (root == NULL) 978 return (PCI_SPEED_UNKNOWN); 979 root = device_get_parent(root); 980 if (root == NULL) 981 return (PCI_SPEED_UNKNOWN); 982 983 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 984 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 985 return (PCI_SPEED_UNKNOWN); 986 987 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 988 return (PCI_SPEED_UNKNOWN); 989 990 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 991 992 if (lnkcap2) { /* PCIe r3.0-compliant */ 993 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 994 return (PCIE_SPEED_2_5GT); 995 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 996 return (PCIE_SPEED_5_0GT); 997 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 998 return (PCIE_SPEED_8_0GT); 999 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1000 return (PCIE_SPEED_16_0GT); 1001 } else { /* pre-r3.0 */ 1002 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1003 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1004 return (PCIE_SPEED_2_5GT); 1005 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1006 return (PCIE_SPEED_5_0GT); 1007 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1008 return (PCIE_SPEED_8_0GT); 1009 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1010 return (PCIE_SPEED_16_0GT); 1011 } 1012 return (PCI_SPEED_UNKNOWN); 1013 } 1014 1015 static inline enum pcie_link_width 1016 pcie_get_width_cap(struct pci_dev *dev) 1017 { 1018 uint32_t lnkcap; 1019 1020 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1021 if (lnkcap) 1022 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1023 1024 return (PCIE_LNK_WIDTH_UNKNOWN); 1025 } 1026 1027 static inline int 1028 pcie_get_mps(struct pci_dev *dev) 1029 { 1030 return (pci_get_max_payload(dev->dev.bsddev)); 1031 } 1032 1033 static inline uint32_t 1034 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1035 { 1036 1037 switch(spd) { 1038 case PCIE_SPEED_16_0GT: 1039 return (16000 * 128 / 130); 1040 case PCIE_SPEED_8_0GT: 1041 return (8000 * 128 / 130); 1042 case PCIE_SPEED_5_0GT: 1043 return (5000 * 8 / 10); 1044 case PCIE_SPEED_2_5GT: 1045 return (2500 * 8 / 10); 1046 default: 1047 return (0); 1048 } 1049 } 1050 1051 static inline uint32_t 1052 pcie_bandwidth_available(struct pci_dev *pdev, 1053 struct pci_dev **limiting, 1054 enum pci_bus_speed *speed, 1055 enum pcie_link_width *width) 1056 { 1057 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1058 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1059 1060 if (speed) 1061 *speed = nspeed; 1062 if (width) 1063 *width = nwidth; 1064 1065 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1066 } 1067 1068 /* 1069 * The following functions can be used to attach/detach the LinuxKPI's 1070 * PCI device runtime. The pci_driver and pci_device_id pointer is 1071 * allowed to be NULL. Other pointers must be all valid. 1072 * The pci_dev structure should be zero-initialized before passed 1073 * to the linux_pci_attach_device function. 1074 */ 1075 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1076 const struct pci_device_id *, struct pci_dev *); 1077 extern int linux_pci_detach_device(struct pci_dev *); 1078 1079 static inline int 1080 pci_dev_present(const struct pci_device_id *cur) 1081 { 1082 while (cur != NULL && (cur->vendor || cur->device)) { 1083 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1084 return (1); 1085 } 1086 cur++; 1087 } 1088 return (0); 1089 } 1090 1091 static inline bool 1092 pci_is_root_bus(struct pci_bus *pbus) 1093 { 1094 1095 return (pbus->self == NULL); 1096 } 1097 1098 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1099 unsigned int bus, unsigned int devfn); 1100 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1101 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1102 1103 static inline int 1104 pci_domain_nr(struct pci_bus *pbus) 1105 { 1106 1107 return (pbus->domain); 1108 } 1109 1110 static inline int 1111 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1112 int pos, uint32_t *val, int len) 1113 { 1114 1115 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1116 return (0); 1117 } 1118 1119 static inline int 1120 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1121 { 1122 uint32_t tmp; 1123 int ret; 1124 1125 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1126 *val = (u16)tmp; 1127 return (ret); 1128 } 1129 1130 static inline int 1131 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1132 { 1133 uint32_t tmp; 1134 int ret; 1135 1136 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1137 *val = (u8)tmp; 1138 return (ret); 1139 } 1140 1141 static inline int 1142 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1143 uint32_t val, int size) 1144 { 1145 1146 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1147 return (0); 1148 } 1149 1150 static inline int 1151 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1152 uint8_t val) 1153 { 1154 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1155 } 1156 1157 static inline int 1158 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1159 uint16_t val) 1160 { 1161 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1162 } 1163 1164 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1165 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1166 1167 #endif /* _LINUX_PCI_H_ */ 1168