1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <sys/rman.h> 47 #include <sys/bus.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 #define MODULE_DEVICE_TABLE(bus, table) 74 75 #define PCI_ANY_ID -1U 76 77 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 78 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 79 #define PCI_FUNC(devfn) ((devfn) & 0x07) 80 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 81 82 #define PCI_VDEVICE(_vendor, _device) \ 83 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 84 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 85 #define PCI_DEVICE(_vendor, _device) \ 86 .vendor = (_vendor), .device = (_device), \ 87 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 88 89 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 90 91 #define PCI_VENDOR_ID PCIR_DEVVENDOR 92 #define PCI_COMMAND PCIR_COMMAND 93 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 94 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 95 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 96 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 97 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 98 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC 99 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 100 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 101 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 102 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 103 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 104 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 105 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 106 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 107 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 108 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 109 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 110 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 111 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 112 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 113 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 114 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 115 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 116 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 117 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 118 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 119 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 120 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 121 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 122 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 123 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 124 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 125 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 126 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 127 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 128 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 129 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 130 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 131 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 132 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 133 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 134 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 135 #define PCI_EXP_LNKCTL2_TLS 0x000f 136 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 137 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 138 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 139 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 140 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 141 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 142 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 143 144 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 145 #define PCI_EXP_DEVSTA_TRPND 0x0020 146 147 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 148 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 149 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 150 151 enum pci_bus_speed { 152 PCI_SPEED_UNKNOWN = -1, 153 PCIE_SPEED_2_5GT, 154 PCIE_SPEED_5_0GT, 155 PCIE_SPEED_8_0GT, 156 PCIE_SPEED_16_0GT, 157 }; 158 159 enum pcie_link_width { 160 PCIE_LNK_WIDTH_RESRV = 0x00, 161 PCIE_LNK_X1 = 0x01, 162 PCIE_LNK_X2 = 0x02, 163 PCIE_LNK_X4 = 0x04, 164 PCIE_LNK_X8 = 0x08, 165 PCIE_LNK_X12 = 0x0c, 166 PCIE_LNK_X16 = 0x10, 167 PCIE_LNK_X32 = 0x20, 168 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 169 }; 170 171 #define PCIE_LINK_STATE_L0S 0x00000001 172 #define PCIE_LINK_STATE_L1 0x00000002 173 #define PCIE_LINK_STATE_CLKPM 0x00000004 174 175 typedef int pci_power_t; 176 177 #define PCI_D0 PCI_POWERSTATE_D0 178 #define PCI_D1 PCI_POWERSTATE_D1 179 #define PCI_D2 PCI_POWERSTATE_D2 180 #define PCI_D3hot PCI_POWERSTATE_D3 181 #define PCI_D3cold 4 182 183 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 184 185 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 186 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 187 188 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 189 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM 190 191 #define PCI_L1SS_CTL1 0x8 192 #define PCI_L1SS_CTL1_L1SS_MASK 0xf 193 194 #define PCI_IRQ_LEGACY 0x01 195 #define PCI_IRQ_MSI 0x02 196 #define PCI_IRQ_MSIX 0x04 197 198 struct pci_dev; 199 200 struct pci_driver { 201 struct list_head node; 202 char *name; 203 const struct pci_device_id *id_table; 204 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 205 void (*remove)(struct pci_dev *dev); 206 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 207 int (*resume) (struct pci_dev *dev); /* Device woken up */ 208 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 209 driver_t bsddriver; 210 devclass_t bsdclass; 211 struct device_driver driver; 212 const struct pci_error_handlers *err_handler; 213 bool isdrm; 214 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 215 const nvlist_t *pf_config); 216 void (*bsd_iov_uninit)(device_t dev); 217 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 218 const nvlist_t *vf_config); 219 }; 220 221 struct pci_bus { 222 struct pci_dev *self; 223 int domain; 224 int number; 225 }; 226 227 extern struct list_head pci_drivers; 228 extern struct list_head pci_devices; 229 extern spinlock_t pci_lock; 230 231 #define __devexit_p(x) x 232 233 #define module_pci_driver(_driver) \ 234 \ 235 static inline int \ 236 _pci_init(void) \ 237 { \ 238 \ 239 return (linux_pci_register_driver(&_driver)); \ 240 } \ 241 \ 242 static inline void \ 243 _pci_exit(void) \ 244 { \ 245 \ 246 linux_pci_unregister_driver(&_driver); \ 247 } \ 248 \ 249 module_init(_pci_init); \ 250 module_exit(_pci_exit) 251 252 /* 253 * If we find drivers accessing this from multiple KPIs we may have to 254 * refcount objects of this structure. 255 */ 256 struct pci_mmio_region { 257 TAILQ_ENTRY(pci_mmio_region) next; 258 struct resource *res; 259 int rid; 260 int type; 261 }; 262 263 struct pci_dev { 264 struct device dev; 265 struct list_head links; 266 struct pci_driver *pdrv; 267 struct pci_bus *bus; 268 uint16_t device; 269 uint16_t vendor; 270 uint16_t subsystem_vendor; 271 uint16_t subsystem_device; 272 unsigned int irq; 273 unsigned int devfn; 274 uint32_t class; 275 uint8_t revision; 276 bool msi_enabled; 277 278 TAILQ_HEAD(, pci_mmio_region) mmio; 279 280 /* Add all new items at the end of the list in 13 */ 281 struct pci_dev *root; 282 phys_addr_t rom; 283 size_t romlen; 284 bool managed; /* devres "pcim_*(). */ 285 bool want_iomap_res; 286 bool msix_enabled; 287 }; 288 289 /* XXX add kassert here on the mmio offset */ 290 291 /* We need some meta-struct to keep track of these for devres. */ 292 struct pci_devres { 293 bool enable_io; 294 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 295 uint8_t region_mask; 296 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 297 }; 298 struct pcim_iomap_devres { 299 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 300 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 301 }; 302 303 /* Internal helper function(s). */ 304 struct pci_dev *lkpinew_pci_dev(device_t); 305 void lkpi_pci_devres_release(struct device *, void *); 306 void lkpi_pcim_iomap_table_release(struct device *, void *); 307 308 static inline int 309 pci_resource_type(struct pci_dev *pdev, int bar) 310 { 311 struct pci_map *pm; 312 313 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 314 if (!pm) 315 return (-1); 316 317 if (PCI_BAR_IO(pm->pm_value)) 318 return (SYS_RES_IOPORT); 319 else 320 return (SYS_RES_MEMORY); 321 } 322 323 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 324 struct resource_list *rl, int type, int rid); 325 326 static inline struct resource_list_entry * 327 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 328 { 329 struct pci_devinfo *dinfo; 330 struct resource_list *rl; 331 struct resource_list_entry *rle; 332 333 dinfo = device_get_ivars(pdev->dev.bsddev); 334 rl = &dinfo->resources; 335 rle = resource_list_find(rl, type, rid); 336 /* Reserve resources for this BAR if needed. */ 337 if (rle == NULL && reserve_bar) 338 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 339 return (rle); 340 } 341 342 static inline struct resource_list_entry * 343 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 344 { 345 int type; 346 347 type = pci_resource_type(pdev, bar); 348 if (type < 0) 349 return (NULL); 350 bar = PCIR_BAR(bar); 351 return (linux_pci_get_rle(pdev, type, bar, reserve)); 352 } 353 354 static inline struct device * 355 linux_pci_find_irq_dev(unsigned int irq) 356 { 357 struct pci_dev *pdev; 358 struct device *found; 359 360 found = NULL; 361 spin_lock(&pci_lock); 362 list_for_each_entry(pdev, &pci_devices, links) { 363 if (irq == pdev->dev.irq || 364 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 365 found = &pdev->dev; 366 break; 367 } 368 } 369 spin_unlock(&pci_lock); 370 return (found); 371 } 372 373 /* 374 * All drivers just seem to want to inspect the type not flags. 375 */ 376 static inline int 377 pci_resource_flags(struct pci_dev *pdev, int bar) 378 { 379 int type; 380 381 type = pci_resource_type(pdev, bar); 382 if (type < 0) 383 return (0); 384 return (1 << type); 385 } 386 387 static inline const char * 388 pci_name(struct pci_dev *d) 389 { 390 391 return device_get_desc(d->dev.bsddev); 392 } 393 394 static inline void * 395 pci_get_drvdata(struct pci_dev *pdev) 396 { 397 398 return dev_get_drvdata(&pdev->dev); 399 } 400 401 static inline void 402 pci_set_drvdata(struct pci_dev *pdev, void *data) 403 { 404 405 dev_set_drvdata(&pdev->dev, data); 406 } 407 408 static inline struct pci_dev * 409 pci_dev_get(struct pci_dev *pdev) 410 { 411 412 if (pdev != NULL) 413 get_device(&pdev->dev); 414 return (pdev); 415 } 416 417 static __inline void 418 pci_dev_put(struct pci_dev *pdev) 419 { 420 421 if (pdev != NULL) 422 put_device(&pdev->dev); 423 } 424 425 static inline int 426 pci_enable_device(struct pci_dev *pdev) 427 { 428 429 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 430 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 431 return (0); 432 } 433 434 static inline void 435 pci_disable_device(struct pci_dev *pdev) 436 { 437 438 pci_disable_busmaster(pdev->dev.bsddev); 439 } 440 441 static inline int 442 pci_set_master(struct pci_dev *pdev) 443 { 444 445 pci_enable_busmaster(pdev->dev.bsddev); 446 return (0); 447 } 448 449 static inline int 450 pci_set_power_state(struct pci_dev *pdev, int state) 451 { 452 453 pci_set_powerstate(pdev->dev.bsddev, state); 454 return (0); 455 } 456 457 static inline int 458 pci_clear_master(struct pci_dev *pdev) 459 { 460 461 pci_disable_busmaster(pdev->dev.bsddev); 462 return (0); 463 } 464 465 static inline struct pci_devres * 466 lkpi_pci_devres_get_alloc(struct pci_dev *pdev) 467 { 468 struct pci_devres *dr; 469 470 dr = lkpi_devres_find(&pdev->dev, lkpi_pci_devres_release, NULL, NULL); 471 if (dr == NULL) { 472 dr = lkpi_devres_alloc(lkpi_pci_devres_release, sizeof(*dr), 473 GFP_KERNEL | __GFP_ZERO); 474 if (dr != NULL) 475 lkpi_devres_add(&pdev->dev, dr); 476 } 477 478 return (dr); 479 } 480 static inline struct pci_devres * 481 lkpi_pci_devres_find(struct pci_dev *pdev) 482 { 483 484 if (!pdev->managed) 485 return (NULL); 486 487 return (lkpi_pci_devres_get_alloc(pdev)); 488 } 489 490 static inline int 491 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 492 { 493 struct resource *res; 494 struct pci_devres *dr; 495 struct pci_mmio_region *mmio; 496 int rid; 497 int type; 498 499 type = pci_resource_type(pdev, bar); 500 if (type < 0) 501 return (-ENODEV); 502 rid = PCIR_BAR(bar); 503 res = bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 504 RF_ACTIVE|RF_SHAREABLE); 505 if (res == NULL) { 506 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 507 "bar %d type %d rid %d\n", 508 __func__, bar, type, PCIR_BAR(bar)); 509 return (-ENODEV); 510 } 511 512 /* 513 * It seems there is an implicit devres tracking on these if the device 514 * is managed; otherwise the resources are not automatiaclly freed on 515 * FreeBSD/LinuxKPI tough they should be/are expected to be by Linux 516 * drivers. 517 */ 518 dr = lkpi_pci_devres_find(pdev); 519 if (dr != NULL) { 520 dr->region_mask |= (1 << bar); 521 dr->region_table[bar] = res; 522 } 523 524 /* Even if the device is not managed we need to track it for iomap. */ 525 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 526 mmio->rid = PCIR_BAR(bar); 527 mmio->type = type; 528 mmio->res = res; 529 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 530 531 return (0); 532 } 533 534 static inline void 535 pci_release_region(struct pci_dev *pdev, int bar) 536 { 537 struct resource_list_entry *rle; 538 struct pci_devres *dr; 539 struct pci_mmio_region *mmio, *p; 540 541 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 542 return; 543 544 /* 545 * As we implicitly track the requests we also need to clear them on 546 * release. Do clear before resource release. 547 */ 548 dr = lkpi_pci_devres_find(pdev); 549 if (dr != NULL) { 550 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 551 " region_table res %p != rel->res %p\n", __func__, pdev, 552 bar, dr->region_table[bar], rle->res)); 553 dr->region_table[bar] = NULL; 554 dr->region_mask &= ~(1 << bar); 555 } 556 557 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 558 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 559 continue; 560 TAILQ_REMOVE(&pdev->mmio, mmio, next); 561 free(mmio, M_DEVBUF); 562 } 563 564 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 565 } 566 567 static inline void 568 pci_release_regions(struct pci_dev *pdev) 569 { 570 int i; 571 572 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 573 pci_release_region(pdev, i); 574 } 575 576 static inline int 577 pci_request_regions(struct pci_dev *pdev, const char *res_name) 578 { 579 int error; 580 int i; 581 582 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 583 error = pci_request_region(pdev, i, res_name); 584 if (error && error != -ENODEV) { 585 pci_release_regions(pdev); 586 return (error); 587 } 588 } 589 return (0); 590 } 591 592 static inline void 593 lkpi_pci_disable_msix(struct pci_dev *pdev) 594 { 595 596 pci_release_msi(pdev->dev.bsddev); 597 598 /* 599 * The MSIX IRQ numbers associated with this PCI device are no 600 * longer valid and might be re-assigned. Make sure 601 * linux_pci_find_irq_dev() does no longer see them by 602 * resetting their references to zero: 603 */ 604 pdev->dev.irq_start = 0; 605 pdev->dev.irq_end = 0; 606 pdev->msix_enabled = false; 607 } 608 /* Only for consistency. No conflict on that one. */ 609 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 610 611 static inline void 612 lkpi_pci_disable_msi(struct pci_dev *pdev) 613 { 614 615 pci_release_msi(pdev->dev.bsddev); 616 617 pdev->dev.irq_start = 0; 618 pdev->dev.irq_end = 0; 619 pdev->irq = pdev->dev.irq; 620 pdev->msi_enabled = false; 621 } 622 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 623 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 624 625 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 626 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 627 628 static inline bus_addr_t 629 pci_bus_address(struct pci_dev *pdev, int bar) 630 { 631 632 return (pci_resource_start(pdev, bar)); 633 } 634 635 #define PCI_CAP_ID_EXP PCIY_EXPRESS 636 #define PCI_CAP_ID_PCIX PCIY_PCIX 637 #define PCI_CAP_ID_AGP PCIY_AGP 638 #define PCI_CAP_ID_PM PCIY_PMG 639 640 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 641 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 642 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 643 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 644 #define PCI_EXP_LNKSTA PCIER_LINK_STA 645 646 static inline int 647 pci_find_capability(struct pci_dev *pdev, int capid) 648 { 649 int reg; 650 651 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 652 return (0); 653 return (reg); 654 } 655 656 static inline int pci_pcie_cap(struct pci_dev *dev) 657 { 658 return pci_find_capability(dev, PCI_CAP_ID_EXP); 659 } 660 661 static inline int 662 pci_find_ext_capability(struct pci_dev *pdev, int capid) 663 { 664 int reg; 665 666 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 667 return (0); 668 return (reg); 669 } 670 671 #define PCIM_PCAP_PME_SHIFT 11 672 static __inline bool 673 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 674 { 675 struct pci_devinfo *dinfo; 676 pcicfgregs *cfg; 677 678 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 679 return (false); 680 681 dinfo = device_get_ivars(pdev->dev.bsddev); 682 cfg = &dinfo->cfg; 683 684 if (cfg->pp.pp_cap == 0) 685 return (false); 686 687 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 688 return (true); 689 690 return (false); 691 } 692 693 static inline int 694 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 695 { 696 697 if (!pci_enable_aspm) 698 return (-EPERM); 699 700 return (-ENXIO); 701 } 702 703 static inline int 704 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 705 { 706 707 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 708 return (0); 709 } 710 711 static inline int 712 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 713 { 714 715 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 716 return (0); 717 } 718 719 static inline int 720 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 721 { 722 723 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 724 return (0); 725 } 726 727 static inline int 728 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 729 { 730 731 pci_write_config(pdev->dev.bsddev, where, val, 1); 732 return (0); 733 } 734 735 static inline int 736 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 737 { 738 739 pci_write_config(pdev->dev.bsddev, where, val, 2); 740 return (0); 741 } 742 743 static inline int 744 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 745 { 746 747 pci_write_config(pdev->dev.bsddev, where, val, 4); 748 return (0); 749 } 750 751 int linux_pci_register_driver(struct pci_driver *pdrv); 752 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 753 void linux_pci_unregister_driver(struct pci_driver *pdrv); 754 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 755 756 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 757 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 758 759 struct msix_entry { 760 int entry; 761 int vector; 762 }; 763 764 /* 765 * Enable msix, positive errors indicate actual number of available 766 * vectors. Negative errors are failures. 767 * 768 * NB: define added to prevent this definition of pci_enable_msix from 769 * clashing with the native FreeBSD version. 770 */ 771 #define pci_enable_msix(...) \ 772 linux_pci_enable_msix(__VA_ARGS__) 773 774 static inline int 775 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 776 { 777 struct resource_list_entry *rle; 778 int error; 779 int avail; 780 int i; 781 782 avail = pci_msix_count(pdev->dev.bsddev); 783 if (avail < nreq) { 784 if (avail == 0) 785 return -EINVAL; 786 return avail; 787 } 788 avail = nreq; 789 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 790 return error; 791 /* 792 * Handle case where "pci_alloc_msix()" may allocate less 793 * interrupts than available and return with no error: 794 */ 795 if (avail < nreq) { 796 pci_release_msi(pdev->dev.bsddev); 797 return avail; 798 } 799 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 800 pdev->dev.irq_start = rle->start; 801 pdev->dev.irq_end = rle->start + avail; 802 for (i = 0; i < nreq; i++) 803 entries[i].vector = pdev->dev.irq_start + i; 804 pdev->msix_enabled = true; 805 return (0); 806 } 807 808 #define pci_enable_msix_range(...) \ 809 linux_pci_enable_msix_range(__VA_ARGS__) 810 811 static inline int 812 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 813 int minvec, int maxvec) 814 { 815 int nvec = maxvec; 816 int rc; 817 818 if (maxvec < minvec) 819 return (-ERANGE); 820 821 do { 822 rc = pci_enable_msix(dev, entries, nvec); 823 if (rc < 0) { 824 return (rc); 825 } else if (rc > 0) { 826 if (rc < minvec) 827 return (-ENOSPC); 828 nvec = rc; 829 } 830 } while (rc); 831 return (nvec); 832 } 833 834 #define pci_enable_msi(pdev) \ 835 linux_pci_enable_msi(pdev) 836 837 static inline int 838 pci_enable_msi(struct pci_dev *pdev) 839 { 840 struct resource_list_entry *rle; 841 int error; 842 int avail; 843 844 avail = pci_msi_count(pdev->dev.bsddev); 845 if (avail < 1) 846 return -EINVAL; 847 848 avail = 1; /* this function only enable one MSI IRQ */ 849 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 850 return error; 851 852 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 853 pdev->dev.irq_start = rle->start; 854 pdev->dev.irq_end = rle->start + avail; 855 pdev->irq = rle->start; 856 pdev->msi_enabled = true; 857 return (0); 858 } 859 860 static inline int 861 pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 862 unsigned int flags) 863 { 864 int error; 865 866 if (flags & PCI_IRQ_MSIX) { 867 struct msix_entry *entries; 868 int i; 869 870 entries = kcalloc(maxv, sizeof(*entries), GFP_KERNEL); 871 if (entries == NULL) { 872 error = -ENOMEM; 873 goto out; 874 } 875 for (i = 0; i < maxv; ++i) 876 entries[i].entry = i; 877 error = pci_enable_msix(pdev, entries, maxv); 878 out: 879 kfree(entries); 880 if (error == 0 && pdev->msix_enabled) 881 return (pdev->dev.irq_end - pdev->dev.irq_start); 882 } 883 if (flags & PCI_IRQ_MSI) { 884 error = pci_enable_msi(pdev); 885 if (error == 0 && pdev->msi_enabled) 886 return (pdev->dev.irq_end - pdev->dev.irq_start); 887 } 888 if (flags & PCI_IRQ_LEGACY) { 889 if (pdev->irq) 890 return (1); 891 } 892 893 return (-EINVAL); 894 } 895 896 static inline int 897 pci_channel_offline(struct pci_dev *pdev) 898 { 899 900 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 901 } 902 903 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 904 { 905 return -ENODEV; 906 } 907 static inline void pci_disable_sriov(struct pci_dev *dev) 908 { 909 } 910 911 static inline struct resource * 912 _lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size __unused) 913 { 914 struct pci_mmio_region *mmio, *p; 915 int type; 916 917 type = pci_resource_type(pdev, bar); 918 if (type < 0) { 919 device_printf(pdev->dev.bsddev, "%s: bar %d type %d\n", 920 __func__, bar, type); 921 return (NULL); 922 } 923 924 /* 925 * Check for duplicate mappings. 926 * This can happen if a driver calls pci_request_region() first. 927 */ 928 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 929 if (mmio->type == type && mmio->rid == PCIR_BAR(bar)) { 930 return (mmio->res); 931 } 932 } 933 934 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 935 mmio->rid = PCIR_BAR(bar); 936 mmio->type = type; 937 mmio->res = bus_alloc_resource_any(pdev->dev.bsddev, mmio->type, 938 &mmio->rid, RF_ACTIVE|RF_SHAREABLE); 939 if (mmio->res == NULL) { 940 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 941 "bar %d type %d rid %d\n", 942 __func__, bar, type, PCIR_BAR(bar)); 943 free(mmio, M_DEVBUF); 944 return (NULL); 945 } 946 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 947 948 return (mmio->res); 949 } 950 951 static inline void * 952 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 953 { 954 struct resource *res; 955 956 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 957 if (res == NULL) 958 return (NULL); 959 /* This is a FreeBSD extension so we can use bus_*(). */ 960 if (pdev->want_iomap_res) 961 return (res); 962 return ((void *)rman_get_bushandle(res)); 963 } 964 965 static inline void 966 pci_iounmap(struct pci_dev *pdev, void *res) 967 { 968 struct pci_mmio_region *mmio, *p; 969 970 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 971 if (res != (void *)rman_get_bushandle(mmio->res)) 972 continue; 973 bus_release_resource(pdev->dev.bsddev, 974 mmio->type, mmio->rid, mmio->res); 975 TAILQ_REMOVE(&pdev->mmio, mmio, next); 976 free(mmio, M_DEVBUF); 977 return; 978 } 979 } 980 981 static inline void 982 lkpi_pci_save_state(struct pci_dev *pdev) 983 { 984 985 pci_save_state(pdev->dev.bsddev); 986 } 987 988 static inline void 989 lkpi_pci_restore_state(struct pci_dev *pdev) 990 { 991 992 pci_restore_state(pdev->dev.bsddev); 993 } 994 995 #define pci_save_state(dev) lkpi_pci_save_state(dev) 996 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 997 998 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 999 const struct pci_device_id _table[] __devinitdata 1000 1001 /* XXX This should not be necessary. */ 1002 #define pcix_set_mmrbc(d, v) 0 1003 #define pcix_get_max_mmrbc(d) 0 1004 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 1005 1006 #define PCI_DMA_BIDIRECTIONAL 0 1007 #define PCI_DMA_TODEVICE 1 1008 #define PCI_DMA_FROMDEVICE 2 1009 #define PCI_DMA_NONE 3 1010 1011 #define pci_pool dma_pool 1012 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 1013 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 1014 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 1015 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 1016 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 1017 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 1018 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1019 _size, _vaddr, _dma_handle) 1020 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1021 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1022 _sg, _nents, (enum dma_data_direction)_dir) 1023 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1024 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1025 (_ptr), (_size), (enum dma_data_direction)_dir) 1026 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1027 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1028 _addr, _size, (enum dma_data_direction)_dir) 1029 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1030 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1031 _sg, _nents, (enum dma_data_direction)_dir) 1032 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1033 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1034 _offset, _size, (enum dma_data_direction)_dir) 1035 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1036 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1037 _dma_address, _size, (enum dma_data_direction)_dir) 1038 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1039 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1040 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1041 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1042 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1043 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1044 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1045 #define pci_unmap_addr dma_unmap_addr 1046 #define pci_unmap_addr_set dma_unmap_addr_set 1047 #define pci_unmap_len dma_unmap_len 1048 #define pci_unmap_len_set dma_unmap_len_set 1049 1050 typedef unsigned int __bitwise pci_channel_state_t; 1051 typedef unsigned int __bitwise pci_ers_result_t; 1052 1053 enum pci_channel_state { 1054 pci_channel_io_normal = 1, 1055 pci_channel_io_frozen = 2, 1056 pci_channel_io_perm_failure = 3, 1057 }; 1058 1059 enum pci_ers_result { 1060 PCI_ERS_RESULT_NONE = 1, 1061 PCI_ERS_RESULT_CAN_RECOVER = 2, 1062 PCI_ERS_RESULT_NEED_RESET = 3, 1063 PCI_ERS_RESULT_DISCONNECT = 4, 1064 PCI_ERS_RESULT_RECOVERED = 5, 1065 }; 1066 1067 /* PCI bus error event callbacks */ 1068 struct pci_error_handlers { 1069 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1070 enum pci_channel_state error); 1071 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1072 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1073 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1074 void (*resume)(struct pci_dev *dev); 1075 }; 1076 1077 /* FreeBSD does not support SRIOV - yet */ 1078 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1079 { 1080 return dev; 1081 } 1082 1083 static inline bool pci_is_pcie(struct pci_dev *dev) 1084 { 1085 return !!pci_pcie_cap(dev); 1086 } 1087 1088 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1089 { 1090 int pos; 1091 u16 reg16; 1092 1093 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1094 if (!pos) 1095 return 0; 1096 1097 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1098 1099 return reg16; 1100 } 1101 1102 static inline int pci_pcie_type(struct pci_dev *dev) 1103 { 1104 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1105 } 1106 1107 static inline int pcie_cap_version(struct pci_dev *dev) 1108 { 1109 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1110 } 1111 1112 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1113 { 1114 int type = pci_pcie_type(dev); 1115 1116 return pcie_cap_version(dev) > 1 || 1117 type == PCI_EXP_TYPE_ROOT_PORT || 1118 type == PCI_EXP_TYPE_ENDPOINT || 1119 type == PCI_EXP_TYPE_LEG_END; 1120 } 1121 1122 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1123 { 1124 return true; 1125 } 1126 1127 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1128 { 1129 int type = pci_pcie_type(dev); 1130 1131 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1132 (type == PCI_EXP_TYPE_DOWNSTREAM && 1133 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1134 } 1135 1136 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1137 { 1138 int type = pci_pcie_type(dev); 1139 1140 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1141 type == PCI_EXP_TYPE_RC_EC; 1142 } 1143 1144 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1145 { 1146 if (!pci_is_pcie(dev)) 1147 return false; 1148 1149 switch (pos) { 1150 case PCI_EXP_FLAGS_TYPE: 1151 return true; 1152 case PCI_EXP_DEVCAP: 1153 case PCI_EXP_DEVCTL: 1154 case PCI_EXP_DEVSTA: 1155 return pcie_cap_has_devctl(dev); 1156 case PCI_EXP_LNKCAP: 1157 case PCI_EXP_LNKCTL: 1158 case PCI_EXP_LNKSTA: 1159 return pcie_cap_has_lnkctl(dev); 1160 case PCI_EXP_SLTCAP: 1161 case PCI_EXP_SLTCTL: 1162 case PCI_EXP_SLTSTA: 1163 return pcie_cap_has_sltctl(dev); 1164 case PCI_EXP_RTCTL: 1165 case PCI_EXP_RTCAP: 1166 case PCI_EXP_RTSTA: 1167 return pcie_cap_has_rtctl(dev); 1168 case PCI_EXP_DEVCAP2: 1169 case PCI_EXP_DEVCTL2: 1170 case PCI_EXP_LNKCAP2: 1171 case PCI_EXP_LNKCTL2: 1172 case PCI_EXP_LNKSTA2: 1173 return pcie_cap_version(dev) > 1; 1174 default: 1175 return false; 1176 } 1177 } 1178 1179 static inline int 1180 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1181 { 1182 if (pos & 3) 1183 return -EINVAL; 1184 1185 if (!pcie_capability_reg_implemented(dev, pos)) 1186 return -EINVAL; 1187 1188 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1189 } 1190 1191 static inline int 1192 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1193 { 1194 if (pos & 3) 1195 return -EINVAL; 1196 1197 if (!pcie_capability_reg_implemented(dev, pos)) 1198 return -EINVAL; 1199 1200 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1201 } 1202 1203 static inline int 1204 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1205 { 1206 if (pos & 1) 1207 return -EINVAL; 1208 1209 if (!pcie_capability_reg_implemented(dev, pos)) 1210 return 0; 1211 1212 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1213 } 1214 1215 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1216 enum pci_bus_speed *speed, enum pcie_link_width *width) 1217 { 1218 *speed = PCI_SPEED_UNKNOWN; 1219 *width = PCIE_LNK_WIDTH_UNKNOWN; 1220 return (0); 1221 } 1222 1223 static inline int 1224 pci_num_vf(struct pci_dev *dev) 1225 { 1226 return (0); 1227 } 1228 1229 static inline enum pci_bus_speed 1230 pcie_get_speed_cap(struct pci_dev *dev) 1231 { 1232 device_t root; 1233 uint32_t lnkcap, lnkcap2; 1234 int error, pos; 1235 1236 root = device_get_parent(dev->dev.bsddev); 1237 if (root == NULL) 1238 return (PCI_SPEED_UNKNOWN); 1239 root = device_get_parent(root); 1240 if (root == NULL) 1241 return (PCI_SPEED_UNKNOWN); 1242 root = device_get_parent(root); 1243 if (root == NULL) 1244 return (PCI_SPEED_UNKNOWN); 1245 1246 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1247 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1248 return (PCI_SPEED_UNKNOWN); 1249 1250 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1251 return (PCI_SPEED_UNKNOWN); 1252 1253 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1254 1255 if (lnkcap2) { /* PCIe r3.0-compliant */ 1256 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1257 return (PCIE_SPEED_2_5GT); 1258 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1259 return (PCIE_SPEED_5_0GT); 1260 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1261 return (PCIE_SPEED_8_0GT); 1262 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1263 return (PCIE_SPEED_16_0GT); 1264 } else { /* pre-r3.0 */ 1265 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1266 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1267 return (PCIE_SPEED_2_5GT); 1268 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1269 return (PCIE_SPEED_5_0GT); 1270 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1271 return (PCIE_SPEED_8_0GT); 1272 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1273 return (PCIE_SPEED_16_0GT); 1274 } 1275 return (PCI_SPEED_UNKNOWN); 1276 } 1277 1278 static inline enum pcie_link_width 1279 pcie_get_width_cap(struct pci_dev *dev) 1280 { 1281 uint32_t lnkcap; 1282 1283 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1284 if (lnkcap) 1285 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1286 1287 return (PCIE_LNK_WIDTH_UNKNOWN); 1288 } 1289 1290 static inline int 1291 pcie_get_mps(struct pci_dev *dev) 1292 { 1293 return (pci_get_max_payload(dev->dev.bsddev)); 1294 } 1295 1296 static inline uint32_t 1297 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1298 { 1299 1300 switch(spd) { 1301 case PCIE_SPEED_16_0GT: 1302 return (16000 * 128 / 130); 1303 case PCIE_SPEED_8_0GT: 1304 return (8000 * 128 / 130); 1305 case PCIE_SPEED_5_0GT: 1306 return (5000 * 8 / 10); 1307 case PCIE_SPEED_2_5GT: 1308 return (2500 * 8 / 10); 1309 default: 1310 return (0); 1311 } 1312 } 1313 1314 static inline uint32_t 1315 pcie_bandwidth_available(struct pci_dev *pdev, 1316 struct pci_dev **limiting, 1317 enum pci_bus_speed *speed, 1318 enum pcie_link_width *width) 1319 { 1320 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1321 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1322 1323 if (speed) 1324 *speed = nspeed; 1325 if (width) 1326 *width = nwidth; 1327 1328 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1329 } 1330 1331 static inline struct pci_dev * 1332 pcie_find_root_port(struct pci_dev *pdev) 1333 { 1334 device_t root; 1335 1336 if (pdev->root != NULL) 1337 return (pdev->root); 1338 1339 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1340 if (root == NULL) 1341 return (NULL); 1342 1343 pdev->root = lkpinew_pci_dev(root); 1344 return (pdev->root); 1345 } 1346 1347 /* This is needed when people rip out the device "HotPlug". */ 1348 static inline void 1349 pci_lock_rescan_remove(void) 1350 { 1351 } 1352 1353 static inline void 1354 pci_unlock_rescan_remove(void) 1355 { 1356 } 1357 1358 static __inline void 1359 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1360 { 1361 } 1362 1363 /* 1364 * The following functions can be used to attach/detach the LinuxKPI's 1365 * PCI device runtime. The pci_driver and pci_device_id pointer is 1366 * allowed to be NULL. Other pointers must be all valid. 1367 * The pci_dev structure should be zero-initialized before passed 1368 * to the linux_pci_attach_device function. 1369 */ 1370 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1371 const struct pci_device_id *, struct pci_dev *); 1372 extern int linux_pci_detach_device(struct pci_dev *); 1373 1374 static inline int 1375 pci_dev_present(const struct pci_device_id *cur) 1376 { 1377 while (cur != NULL && (cur->vendor || cur->device)) { 1378 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1379 return (1); 1380 } 1381 cur++; 1382 } 1383 return (0); 1384 } 1385 1386 static inline bool 1387 pci_is_root_bus(struct pci_bus *pbus) 1388 { 1389 1390 return (pbus->self == NULL); 1391 } 1392 1393 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1394 unsigned int bus, unsigned int devfn); 1395 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1396 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1397 1398 static inline int 1399 pci_domain_nr(struct pci_bus *pbus) 1400 { 1401 1402 return (pbus->domain); 1403 } 1404 1405 static inline int 1406 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1407 int pos, uint32_t *val, int len) 1408 { 1409 1410 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1411 return (0); 1412 } 1413 1414 static inline int 1415 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1416 { 1417 uint32_t tmp; 1418 int ret; 1419 1420 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1421 *val = (u16)tmp; 1422 return (ret); 1423 } 1424 1425 static inline int 1426 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1427 { 1428 uint32_t tmp; 1429 int ret; 1430 1431 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1432 *val = (u8)tmp; 1433 return (ret); 1434 } 1435 1436 static inline int 1437 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1438 uint32_t val, int size) 1439 { 1440 1441 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1442 return (0); 1443 } 1444 1445 static inline int 1446 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1447 uint8_t val) 1448 { 1449 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1450 } 1451 1452 static inline int 1453 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1454 uint16_t val) 1455 { 1456 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1457 } 1458 1459 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1460 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1461 1462 /* -------------------------------------------------------------------------- */ 1463 1464 static inline int 1465 pcim_enable_device(struct pci_dev *pdev) 1466 { 1467 struct pci_devres *dr; 1468 int error; 1469 1470 /* Here we cannot run through the pdev->managed check. */ 1471 dr = lkpi_pci_devres_get_alloc(pdev); 1472 if (dr == NULL) 1473 return (-ENOMEM); 1474 1475 /* If resources were enabled before do not do it again. */ 1476 if (dr->enable_io) 1477 return (0); 1478 1479 error = pci_enable_device(pdev); 1480 if (error == 0) 1481 dr->enable_io = true; 1482 1483 /* This device is not managed. */ 1484 pdev->managed = true; 1485 1486 return (error); 1487 } 1488 1489 static inline struct pcim_iomap_devres * 1490 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev) 1491 { 1492 struct pcim_iomap_devres *dr; 1493 1494 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release, 1495 NULL, NULL); 1496 if (dr == NULL) { 1497 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release, 1498 sizeof(*dr), GFP_KERNEL | __GFP_ZERO); 1499 if (dr != NULL) 1500 lkpi_devres_add(&pdev->dev, dr); 1501 } 1502 1503 if (dr == NULL) 1504 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__); 1505 1506 return (dr); 1507 } 1508 1509 static inline void __iomem ** 1510 pcim_iomap_table(struct pci_dev *pdev) 1511 { 1512 struct pcim_iomap_devres *dr; 1513 1514 dr = lkpi_pcim_iomap_devres_find(pdev); 1515 if (dr == NULL) 1516 return (NULL); 1517 1518 /* 1519 * If the driver has manually set a flag to be able to request the 1520 * resource to use bus_read/write_<n>, return the shadow table. 1521 */ 1522 if (pdev->want_iomap_res) 1523 return ((void **)dr->res_table); 1524 1525 /* This is the Linux default. */ 1526 return (dr->mmio_table); 1527 } 1528 1529 static inline int 1530 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1531 { 1532 struct pcim_iomap_devres *dr; 1533 void *res; 1534 uint32_t mappings, requests, req_mask; 1535 int bar, error; 1536 1537 dr = lkpi_pcim_iomap_devres_find(pdev); 1538 if (dr == NULL) 1539 return (-ENOMEM); 1540 1541 /* Request all the BARs ("regions") we do not iomap. */ 1542 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1543 for (bar = requests = 0; requests != req_mask; bar++) { 1544 if ((req_mask & (1 << bar)) == 0) 1545 continue; 1546 error = pci_request_region(pdev, bar, name); 1547 if (error != 0 && error != -ENODEV) 1548 goto err; 1549 requests |= (1 << bar); 1550 } 1551 1552 /* Now iomap all the requested (by "mask") ones. */ 1553 for (bar = mappings = 0; mappings != mask; bar++) { 1554 if ((mask & (1 << bar)) == 0) 1555 continue; 1556 1557 /* Request double is not allowed. */ 1558 if (dr->mmio_table[bar] != NULL) { 1559 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1560 __func__, bar, dr->mmio_table[bar]); 1561 goto err; 1562 } 1563 1564 res = _lkpi_pci_iomap(pdev, bar, 0); 1565 if (res == NULL) 1566 goto err; 1567 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1568 dr->res_table[bar] = res; 1569 1570 mappings |= (1 << bar); 1571 } 1572 1573 return (0); 1574 1575 err: 1576 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1577 if ((mappings & (1 << bar)) != 0) { 1578 res = dr->mmio_table[bar]; 1579 if (res == NULL) 1580 continue; 1581 pci_iounmap(pdev, res); 1582 } else if ((requests & (1 << bar)) != 0) { 1583 pci_release_region(pdev, bar); 1584 } 1585 } 1586 1587 return (-EINVAL); 1588 } 1589 1590 /* This is a FreeBSD extension so we can use bus_*(). */ 1591 static inline void 1592 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1593 { 1594 pdev->want_iomap_res = true; 1595 } 1596 1597 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1598