1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUXKPI_LINUX_PCI_H_ 36 #define _LINUXKPI_LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <sys/rman.h> 47 #include <sys/bus.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 #define MODULE_DEVICE_TABLE(bus, table) 74 75 #define PCI_ANY_ID -1U 76 77 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 78 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 79 #define PCI_FUNC(devfn) ((devfn) & 0x07) 80 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 81 82 #define PCI_VDEVICE(_vendor, _device) \ 83 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 84 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 85 #define PCI_DEVICE(_vendor, _device) \ 86 .vendor = (_vendor), .device = (_device), \ 87 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 88 89 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 90 91 #define PCI_VENDOR_ID PCIR_DEVVENDOR 92 #define PCI_COMMAND PCIR_COMMAND 93 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 94 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 95 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 96 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 97 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 98 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 99 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 100 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 101 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 102 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 103 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 104 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 105 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 106 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 107 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 108 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 109 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 110 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 111 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 112 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 113 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 114 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 115 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 116 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 117 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 118 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 119 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 120 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 121 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 122 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 123 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 124 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 125 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 126 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 127 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 128 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 129 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 130 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 131 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 132 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 133 #define PCI_EXP_LNKCTL2_TLS 0x000f 134 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 135 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 136 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 137 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 138 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 139 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 140 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 141 142 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 143 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 144 #define PCI_EXP_DEVSTA_TRPND 0x0020 145 146 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 147 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 148 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 149 150 enum pci_bus_speed { 151 PCI_SPEED_UNKNOWN = -1, 152 PCIE_SPEED_2_5GT, 153 PCIE_SPEED_5_0GT, 154 PCIE_SPEED_8_0GT, 155 PCIE_SPEED_16_0GT, 156 }; 157 158 enum pcie_link_width { 159 PCIE_LNK_WIDTH_RESRV = 0x00, 160 PCIE_LNK_X1 = 0x01, 161 PCIE_LNK_X2 = 0x02, 162 PCIE_LNK_X4 = 0x04, 163 PCIE_LNK_X8 = 0x08, 164 PCIE_LNK_X12 = 0x0c, 165 PCIE_LNK_X16 = 0x10, 166 PCIE_LNK_X32 = 0x20, 167 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 168 }; 169 170 #define PCIE_LINK_STATE_L0S 0x00000001 171 #define PCIE_LINK_STATE_L1 0x00000002 172 #define PCIE_LINK_STATE_CLKPM 0x00000004 173 174 typedef int pci_power_t; 175 176 #define PCI_D0 PCI_POWERSTATE_D0 177 #define PCI_D1 PCI_POWERSTATE_D1 178 #define PCI_D2 PCI_POWERSTATE_D2 179 #define PCI_D3hot PCI_POWERSTATE_D3 180 #define PCI_D3cold 4 181 182 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 183 184 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 185 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 186 187 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 188 189 #define PCI_IRQ_LEGACY 0x01 190 #define PCI_IRQ_MSI 0x02 191 #define PCI_IRQ_MSIX 0x04 192 193 struct pci_dev; 194 195 struct pci_driver { 196 struct list_head node; 197 char *name; 198 const struct pci_device_id *id_table; 199 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 200 void (*remove)(struct pci_dev *dev); 201 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 202 int (*resume) (struct pci_dev *dev); /* Device woken up */ 203 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 204 driver_t bsddriver; 205 devclass_t bsdclass; 206 struct device_driver driver; 207 const struct pci_error_handlers *err_handler; 208 bool isdrm; 209 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 210 const nvlist_t *pf_config); 211 void (*bsd_iov_uninit)(device_t dev); 212 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 213 const nvlist_t *vf_config); 214 }; 215 216 struct pci_bus { 217 struct pci_dev *self; 218 int domain; 219 int number; 220 }; 221 222 extern struct list_head pci_drivers; 223 extern struct list_head pci_devices; 224 extern spinlock_t pci_lock; 225 226 #define __devexit_p(x) x 227 228 #define module_pci_driver(_driver) \ 229 \ 230 static inline int \ 231 _pci_init(void) \ 232 { \ 233 \ 234 return (linux_pci_register_driver(&_driver)); \ 235 } \ 236 \ 237 static inline void \ 238 _pci_exit(void) \ 239 { \ 240 \ 241 linux_pci_unregister_driver(&_driver); \ 242 } \ 243 \ 244 module_init(_pci_init); \ 245 module_exit(_pci_exit) 246 247 /* 248 * If we find drivers accessing this from multiple KPIs we may have to 249 * refcount objects of this structure. 250 */ 251 struct pci_mmio_region { 252 TAILQ_ENTRY(pci_mmio_region) next; 253 struct resource *res; 254 int rid; 255 int type; 256 }; 257 258 struct pci_dev { 259 struct device dev; 260 struct list_head links; 261 struct pci_driver *pdrv; 262 struct pci_bus *bus; 263 uint16_t device; 264 uint16_t vendor; 265 uint16_t subsystem_vendor; 266 uint16_t subsystem_device; 267 unsigned int irq; 268 unsigned int devfn; 269 uint32_t class; 270 uint8_t revision; 271 bool msi_enabled; 272 273 TAILQ_HEAD(, pci_mmio_region) mmio; 274 275 /* Add all new items at the end of the list in 13 */ 276 struct pci_dev *root; 277 phys_addr_t rom; 278 size_t romlen; 279 bool managed; /* devres "pcim_*(). */ 280 bool want_iomap_res; 281 bool msix_enabled; 282 }; 283 284 /* XXX add kassert here on the mmio offset */ 285 286 /* We need some meta-struct to keep track of these for devres. */ 287 struct pci_devres { 288 bool enable_io; 289 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 290 uint8_t region_mask; 291 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 292 }; 293 struct pcim_iomap_devres { 294 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 295 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 296 }; 297 298 /* Internal helper function(s). */ 299 struct pci_dev *lkpinew_pci_dev(device_t); 300 void lkpi_pci_devres_release(struct device *, void *); 301 void lkpi_pcim_iomap_table_release(struct device *, void *); 302 303 static inline int 304 pci_resource_type(struct pci_dev *pdev, int bar) 305 { 306 struct pci_map *pm; 307 308 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 309 if (!pm) 310 return (-1); 311 312 if (PCI_BAR_IO(pm->pm_value)) 313 return (SYS_RES_IOPORT); 314 else 315 return (SYS_RES_MEMORY); 316 } 317 318 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 319 struct resource_list *rl, int type, int rid); 320 321 static inline struct resource_list_entry * 322 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 323 { 324 struct pci_devinfo *dinfo; 325 struct resource_list *rl; 326 struct resource_list_entry *rle; 327 328 dinfo = device_get_ivars(pdev->dev.bsddev); 329 rl = &dinfo->resources; 330 rle = resource_list_find(rl, type, rid); 331 /* Reserve resources for this BAR if needed. */ 332 if (rle == NULL && reserve_bar) 333 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 334 return (rle); 335 } 336 337 static inline struct resource_list_entry * 338 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 339 { 340 int type; 341 342 type = pci_resource_type(pdev, bar); 343 if (type < 0) 344 return (NULL); 345 bar = PCIR_BAR(bar); 346 return (linux_pci_get_rle(pdev, type, bar, reserve)); 347 } 348 349 static inline struct device * 350 linux_pci_find_irq_dev(unsigned int irq) 351 { 352 struct pci_dev *pdev; 353 struct device *found; 354 355 found = NULL; 356 spin_lock(&pci_lock); 357 list_for_each_entry(pdev, &pci_devices, links) { 358 if (irq == pdev->dev.irq || 359 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 360 found = &pdev->dev; 361 break; 362 } 363 } 364 spin_unlock(&pci_lock); 365 return (found); 366 } 367 368 /* 369 * All drivers just seem to want to inspect the type not flags. 370 */ 371 static inline int 372 pci_resource_flags(struct pci_dev *pdev, int bar) 373 { 374 int type; 375 376 type = pci_resource_type(pdev, bar); 377 if (type < 0) 378 return (0); 379 return (1 << type); 380 } 381 382 static inline const char * 383 pci_name(struct pci_dev *d) 384 { 385 386 return device_get_desc(d->dev.bsddev); 387 } 388 389 static inline void * 390 pci_get_drvdata(struct pci_dev *pdev) 391 { 392 393 return dev_get_drvdata(&pdev->dev); 394 } 395 396 static inline void 397 pci_set_drvdata(struct pci_dev *pdev, void *data) 398 { 399 400 dev_set_drvdata(&pdev->dev, data); 401 } 402 403 static inline struct pci_dev * 404 pci_dev_get(struct pci_dev *pdev) 405 { 406 407 if (pdev != NULL) 408 get_device(&pdev->dev); 409 return (pdev); 410 } 411 412 static __inline void 413 pci_dev_put(struct pci_dev *pdev) 414 { 415 416 if (pdev != NULL) 417 put_device(&pdev->dev); 418 } 419 420 static inline int 421 pci_enable_device(struct pci_dev *pdev) 422 { 423 424 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 425 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 426 return (0); 427 } 428 429 static inline void 430 pci_disable_device(struct pci_dev *pdev) 431 { 432 433 pci_disable_busmaster(pdev->dev.bsddev); 434 } 435 436 static inline int 437 pci_set_master(struct pci_dev *pdev) 438 { 439 440 pci_enable_busmaster(pdev->dev.bsddev); 441 return (0); 442 } 443 444 static inline int 445 pci_set_power_state(struct pci_dev *pdev, int state) 446 { 447 448 pci_set_powerstate(pdev->dev.bsddev, state); 449 return (0); 450 } 451 452 static inline int 453 pci_clear_master(struct pci_dev *pdev) 454 { 455 456 pci_disable_busmaster(pdev->dev.bsddev); 457 return (0); 458 } 459 460 static inline struct pci_devres * 461 lkpi_pci_devres_get_alloc(struct pci_dev *pdev) 462 { 463 struct pci_devres *dr; 464 465 dr = lkpi_devres_find(&pdev->dev, lkpi_pci_devres_release, NULL, NULL); 466 if (dr == NULL) { 467 dr = lkpi_devres_alloc(lkpi_pci_devres_release, sizeof(*dr), 468 GFP_KERNEL | __GFP_ZERO); 469 if (dr != NULL) 470 lkpi_devres_add(&pdev->dev, dr); 471 } 472 473 return (dr); 474 } 475 static inline struct pci_devres * 476 lkpi_pci_devres_find(struct pci_dev *pdev) 477 { 478 479 if (!pdev->managed) 480 return (NULL); 481 482 return (lkpi_pci_devres_get_alloc(pdev)); 483 } 484 485 static inline int 486 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 487 { 488 struct resource *res; 489 struct pci_devres *dr; 490 struct pci_mmio_region *mmio; 491 int rid; 492 int type; 493 494 type = pci_resource_type(pdev, bar); 495 if (type < 0) 496 return (-ENODEV); 497 rid = PCIR_BAR(bar); 498 res = bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 499 RF_ACTIVE|RF_SHAREABLE); 500 if (res == NULL) { 501 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 502 "bar %d type %d rid %d\n", 503 __func__, bar, type, PCIR_BAR(bar)); 504 return (-ENODEV); 505 } 506 507 /* 508 * It seems there is an implicit devres tracking on these if the device 509 * is managed; otherwise the resources are not automatiaclly freed on 510 * FreeBSD/LinuxKPI tough they should be/are expected to be by Linux 511 * drivers. 512 */ 513 dr = lkpi_pci_devres_find(pdev); 514 if (dr != NULL) { 515 dr->region_mask |= (1 << bar); 516 dr->region_table[bar] = res; 517 } 518 519 /* Even if the device is not managed we need to track it for iomap. */ 520 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 521 mmio->rid = PCIR_BAR(bar); 522 mmio->type = type; 523 mmio->res = res; 524 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 525 526 return (0); 527 } 528 529 static inline void 530 pci_release_region(struct pci_dev *pdev, int bar) 531 { 532 struct resource_list_entry *rle; 533 struct pci_devres *dr; 534 struct pci_mmio_region *mmio, *p; 535 536 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 537 return; 538 539 /* 540 * As we implicitly track the requests we also need to clear them on 541 * release. Do clear before resource release. 542 */ 543 dr = lkpi_pci_devres_find(pdev); 544 if (dr != NULL) { 545 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 546 " region_table res %p != rel->res %p\n", __func__, pdev, 547 bar, dr->region_table[bar], rle->res)); 548 dr->region_table[bar] = NULL; 549 dr->region_mask &= ~(1 << bar); 550 } 551 552 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 553 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 554 continue; 555 TAILQ_REMOVE(&pdev->mmio, mmio, next); 556 free(mmio, M_DEVBUF); 557 } 558 559 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 560 } 561 562 static inline void 563 pci_release_regions(struct pci_dev *pdev) 564 { 565 int i; 566 567 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 568 pci_release_region(pdev, i); 569 } 570 571 static inline int 572 pci_request_regions(struct pci_dev *pdev, const char *res_name) 573 { 574 int error; 575 int i; 576 577 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 578 error = pci_request_region(pdev, i, res_name); 579 if (error && error != -ENODEV) { 580 pci_release_regions(pdev); 581 return (error); 582 } 583 } 584 return (0); 585 } 586 587 static inline void 588 lkpi_pci_disable_msix(struct pci_dev *pdev) 589 { 590 591 pci_release_msi(pdev->dev.bsddev); 592 593 /* 594 * The MSIX IRQ numbers associated with this PCI device are no 595 * longer valid and might be re-assigned. Make sure 596 * linux_pci_find_irq_dev() does no longer see them by 597 * resetting their references to zero: 598 */ 599 pdev->dev.irq_start = 0; 600 pdev->dev.irq_end = 0; 601 pdev->msix_enabled = false; 602 } 603 /* Only for consistency. No conflict on that one. */ 604 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 605 606 static inline void 607 lkpi_pci_disable_msi(struct pci_dev *pdev) 608 { 609 610 pci_release_msi(pdev->dev.bsddev); 611 612 pdev->dev.irq_start = 0; 613 pdev->dev.irq_end = 0; 614 pdev->irq = pdev->dev.irq; 615 pdev->msi_enabled = false; 616 } 617 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 618 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 619 620 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 621 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 622 623 static inline bus_addr_t 624 pci_bus_address(struct pci_dev *pdev, int bar) 625 { 626 627 return (pci_resource_start(pdev, bar)); 628 } 629 630 #define PCI_CAP_ID_EXP PCIY_EXPRESS 631 #define PCI_CAP_ID_PCIX PCIY_PCIX 632 #define PCI_CAP_ID_AGP PCIY_AGP 633 #define PCI_CAP_ID_PM PCIY_PMG 634 635 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 636 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 637 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 638 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 639 #define PCI_EXP_LNKSTA PCIER_LINK_STA 640 641 static inline int 642 pci_find_capability(struct pci_dev *pdev, int capid) 643 { 644 int reg; 645 646 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 647 return (0); 648 return (reg); 649 } 650 651 static inline int pci_pcie_cap(struct pci_dev *dev) 652 { 653 return pci_find_capability(dev, PCI_CAP_ID_EXP); 654 } 655 656 static inline int 657 pci_find_ext_capability(struct pci_dev *pdev, int capid) 658 { 659 int reg; 660 661 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 662 return (0); 663 return (reg); 664 } 665 666 #define PCIM_PCAP_PME_SHIFT 11 667 static __inline bool 668 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 669 { 670 struct pci_devinfo *dinfo; 671 pcicfgregs *cfg; 672 673 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 674 return (false); 675 676 dinfo = device_get_ivars(pdev->dev.bsddev); 677 cfg = &dinfo->cfg; 678 679 if (cfg->pp.pp_cap == 0) 680 return (false); 681 682 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 683 return (true); 684 685 return (false); 686 } 687 688 static inline int 689 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 690 { 691 692 if (!pci_enable_aspm) 693 return (-EPERM); 694 695 return (-ENXIO); 696 } 697 698 static inline int 699 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val) 700 { 701 702 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 703 return (0); 704 } 705 706 static inline int 707 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val) 708 { 709 710 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 711 return (0); 712 } 713 714 static inline int 715 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val) 716 { 717 718 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 719 return (0); 720 } 721 722 static inline int 723 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val) 724 { 725 726 pci_write_config(pdev->dev.bsddev, where, val, 1); 727 return (0); 728 } 729 730 static inline int 731 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val) 732 { 733 734 pci_write_config(pdev->dev.bsddev, where, val, 2); 735 return (0); 736 } 737 738 static inline int 739 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val) 740 { 741 742 pci_write_config(pdev->dev.bsddev, where, val, 4); 743 return (0); 744 } 745 746 int linux_pci_register_driver(struct pci_driver *pdrv); 747 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 748 void linux_pci_unregister_driver(struct pci_driver *pdrv); 749 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 750 751 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 752 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 753 754 struct msix_entry { 755 int entry; 756 int vector; 757 }; 758 759 /* 760 * Enable msix, positive errors indicate actual number of available 761 * vectors. Negative errors are failures. 762 * 763 * NB: define added to prevent this definition of pci_enable_msix from 764 * clashing with the native FreeBSD version. 765 */ 766 #define pci_enable_msix(...) \ 767 linux_pci_enable_msix(__VA_ARGS__) 768 769 static inline int 770 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 771 { 772 struct resource_list_entry *rle; 773 int error; 774 int avail; 775 int i; 776 777 avail = pci_msix_count(pdev->dev.bsddev); 778 if (avail < nreq) { 779 if (avail == 0) 780 return -EINVAL; 781 return avail; 782 } 783 avail = nreq; 784 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 785 return error; 786 /* 787 * Handle case where "pci_alloc_msix()" may allocate less 788 * interrupts than available and return with no error: 789 */ 790 if (avail < nreq) { 791 pci_release_msi(pdev->dev.bsddev); 792 return avail; 793 } 794 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 795 pdev->dev.irq_start = rle->start; 796 pdev->dev.irq_end = rle->start + avail; 797 for (i = 0; i < nreq; i++) 798 entries[i].vector = pdev->dev.irq_start + i; 799 pdev->msix_enabled = true; 800 return (0); 801 } 802 803 #define pci_enable_msix_range(...) \ 804 linux_pci_enable_msix_range(__VA_ARGS__) 805 806 static inline int 807 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 808 int minvec, int maxvec) 809 { 810 int nvec = maxvec; 811 int rc; 812 813 if (maxvec < minvec) 814 return (-ERANGE); 815 816 do { 817 rc = pci_enable_msix(dev, entries, nvec); 818 if (rc < 0) { 819 return (rc); 820 } else if (rc > 0) { 821 if (rc < minvec) 822 return (-ENOSPC); 823 nvec = rc; 824 } 825 } while (rc); 826 return (nvec); 827 } 828 829 #define pci_enable_msi(pdev) \ 830 linux_pci_enable_msi(pdev) 831 832 static inline int 833 pci_enable_msi(struct pci_dev *pdev) 834 { 835 struct resource_list_entry *rle; 836 int error; 837 int avail; 838 839 avail = pci_msi_count(pdev->dev.bsddev); 840 if (avail < 1) 841 return -EINVAL; 842 843 avail = 1; /* this function only enable one MSI IRQ */ 844 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 845 return error; 846 847 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 848 pdev->dev.irq_start = rle->start; 849 pdev->dev.irq_end = rle->start + avail; 850 pdev->irq = rle->start; 851 pdev->msi_enabled = true; 852 return (0); 853 } 854 855 static inline int 856 pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv, 857 unsigned int flags) 858 { 859 int error; 860 861 if (flags & PCI_IRQ_MSIX) { 862 struct msix_entry *entries; 863 int i; 864 865 entries = kcalloc(maxv, sizeof(*entries), GFP_KERNEL); 866 if (entries == NULL) { 867 error = -ENOMEM; 868 goto out; 869 } 870 for (i = 0; i < maxv; ++i) 871 entries[i].entry = i; 872 error = pci_enable_msix(pdev, entries, maxv); 873 out: 874 kfree(entries); 875 if (error == 0 && pdev->msix_enabled) 876 return (pdev->dev.irq_end - pdev->dev.irq_start); 877 } 878 if (flags & PCI_IRQ_MSI) { 879 error = pci_enable_msi(pdev); 880 if (error == 0 && pdev->msi_enabled) 881 return (pdev->dev.irq_end - pdev->dev.irq_start); 882 } 883 if (flags & PCI_IRQ_LEGACY) { 884 if (pdev->irq) 885 return (1); 886 } 887 888 return (-EINVAL); 889 } 890 891 static inline int 892 pci_channel_offline(struct pci_dev *pdev) 893 { 894 895 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 896 } 897 898 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 899 { 900 return -ENODEV; 901 } 902 static inline void pci_disable_sriov(struct pci_dev *dev) 903 { 904 } 905 906 static inline struct resource * 907 _lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size __unused) 908 { 909 struct pci_mmio_region *mmio, *p; 910 int type; 911 912 type = pci_resource_type(pdev, bar); 913 if (type < 0) { 914 device_printf(pdev->dev.bsddev, "%s: bar %d type %d\n", 915 __func__, bar, type); 916 return (NULL); 917 } 918 919 /* 920 * Check for duplicate mappings. 921 * This can happen if a driver calls pci_request_region() first. 922 */ 923 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 924 if (mmio->type == type && mmio->rid == PCIR_BAR(bar)) { 925 return (mmio->res); 926 } 927 } 928 929 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 930 mmio->rid = PCIR_BAR(bar); 931 mmio->type = type; 932 mmio->res = bus_alloc_resource_any(pdev->dev.bsddev, mmio->type, 933 &mmio->rid, RF_ACTIVE|RF_SHAREABLE); 934 if (mmio->res == NULL) { 935 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 936 "bar %d type %d rid %d\n", 937 __func__, bar, type, PCIR_BAR(bar)); 938 free(mmio, M_DEVBUF); 939 return (NULL); 940 } 941 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 942 943 return (mmio->res); 944 } 945 946 static inline void * 947 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 948 { 949 struct resource *res; 950 951 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 952 if (res == NULL) 953 return (NULL); 954 /* This is a FreeBSD extension so we can use bus_*(). */ 955 if (pdev->want_iomap_res) 956 return (res); 957 return ((void *)rman_get_bushandle(res)); 958 } 959 960 static inline void 961 pci_iounmap(struct pci_dev *pdev, void *res) 962 { 963 struct pci_mmio_region *mmio, *p; 964 965 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 966 if (res != (void *)rman_get_bushandle(mmio->res)) 967 continue; 968 bus_release_resource(pdev->dev.bsddev, 969 mmio->type, mmio->rid, mmio->res); 970 TAILQ_REMOVE(&pdev->mmio, mmio, next); 971 free(mmio, M_DEVBUF); 972 return; 973 } 974 } 975 976 static inline void 977 lkpi_pci_save_state(struct pci_dev *pdev) 978 { 979 980 pci_save_state(pdev->dev.bsddev); 981 } 982 983 static inline void 984 lkpi_pci_restore_state(struct pci_dev *pdev) 985 { 986 987 pci_restore_state(pdev->dev.bsddev); 988 } 989 990 #define pci_save_state(dev) lkpi_pci_save_state(dev) 991 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 992 993 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 994 const struct pci_device_id _table[] __devinitdata 995 996 /* XXX This should not be necessary. */ 997 #define pcix_set_mmrbc(d, v) 0 998 #define pcix_get_max_mmrbc(d) 0 999 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 1000 1001 #define PCI_DMA_BIDIRECTIONAL 0 1002 #define PCI_DMA_TODEVICE 1 1003 #define PCI_DMA_FROMDEVICE 2 1004 #define PCI_DMA_NONE 3 1005 1006 #define pci_pool dma_pool 1007 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 1008 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 1009 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 1010 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 1011 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 1012 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 1013 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1014 _size, _vaddr, _dma_handle) 1015 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 1016 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1017 _sg, _nents, (enum dma_data_direction)_dir) 1018 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 1019 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 1020 (_ptr), (_size), (enum dma_data_direction)_dir) 1021 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 1022 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1023 _addr, _size, (enum dma_data_direction)_dir) 1024 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 1025 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1026 _sg, _nents, (enum dma_data_direction)_dir) 1027 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 1028 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 1029 _offset, _size, (enum dma_data_direction)_dir) 1030 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 1031 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 1032 _dma_address, _size, (enum dma_data_direction)_dir) 1033 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 1034 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 1035 dma_mapping_error(&(_pdev)->dev, _dma_addr) 1036 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 1037 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 1038 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 1039 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 1040 #define pci_unmap_addr dma_unmap_addr 1041 #define pci_unmap_addr_set dma_unmap_addr_set 1042 #define pci_unmap_len dma_unmap_len 1043 #define pci_unmap_len_set dma_unmap_len_set 1044 1045 typedef unsigned int __bitwise pci_channel_state_t; 1046 typedef unsigned int __bitwise pci_ers_result_t; 1047 1048 enum pci_channel_state { 1049 pci_channel_io_normal = 1, 1050 pci_channel_io_frozen = 2, 1051 pci_channel_io_perm_failure = 3, 1052 }; 1053 1054 enum pci_ers_result { 1055 PCI_ERS_RESULT_NONE = 1, 1056 PCI_ERS_RESULT_CAN_RECOVER = 2, 1057 PCI_ERS_RESULT_NEED_RESET = 3, 1058 PCI_ERS_RESULT_DISCONNECT = 4, 1059 PCI_ERS_RESULT_RECOVERED = 5, 1060 }; 1061 1062 /* PCI bus error event callbacks */ 1063 struct pci_error_handlers { 1064 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1065 enum pci_channel_state error); 1066 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1067 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1068 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1069 void (*resume)(struct pci_dev *dev); 1070 }; 1071 1072 /* FreeBSD does not support SRIOV - yet */ 1073 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1074 { 1075 return dev; 1076 } 1077 1078 static inline bool pci_is_pcie(struct pci_dev *dev) 1079 { 1080 return !!pci_pcie_cap(dev); 1081 } 1082 1083 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1084 { 1085 int pos; 1086 u16 reg16; 1087 1088 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1089 if (!pos) 1090 return 0; 1091 1092 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1093 1094 return reg16; 1095 } 1096 1097 static inline int pci_pcie_type(struct pci_dev *dev) 1098 { 1099 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1100 } 1101 1102 static inline int pcie_cap_version(struct pci_dev *dev) 1103 { 1104 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1105 } 1106 1107 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1108 { 1109 int type = pci_pcie_type(dev); 1110 1111 return pcie_cap_version(dev) > 1 || 1112 type == PCI_EXP_TYPE_ROOT_PORT || 1113 type == PCI_EXP_TYPE_ENDPOINT || 1114 type == PCI_EXP_TYPE_LEG_END; 1115 } 1116 1117 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1118 { 1119 return true; 1120 } 1121 1122 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1123 { 1124 int type = pci_pcie_type(dev); 1125 1126 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1127 (type == PCI_EXP_TYPE_DOWNSTREAM && 1128 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1129 } 1130 1131 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1132 { 1133 int type = pci_pcie_type(dev); 1134 1135 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1136 type == PCI_EXP_TYPE_RC_EC; 1137 } 1138 1139 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1140 { 1141 if (!pci_is_pcie(dev)) 1142 return false; 1143 1144 switch (pos) { 1145 case PCI_EXP_FLAGS_TYPE: 1146 return true; 1147 case PCI_EXP_DEVCAP: 1148 case PCI_EXP_DEVCTL: 1149 case PCI_EXP_DEVSTA: 1150 return pcie_cap_has_devctl(dev); 1151 case PCI_EXP_LNKCAP: 1152 case PCI_EXP_LNKCTL: 1153 case PCI_EXP_LNKSTA: 1154 return pcie_cap_has_lnkctl(dev); 1155 case PCI_EXP_SLTCAP: 1156 case PCI_EXP_SLTCTL: 1157 case PCI_EXP_SLTSTA: 1158 return pcie_cap_has_sltctl(dev); 1159 case PCI_EXP_RTCTL: 1160 case PCI_EXP_RTCAP: 1161 case PCI_EXP_RTSTA: 1162 return pcie_cap_has_rtctl(dev); 1163 case PCI_EXP_DEVCAP2: 1164 case PCI_EXP_DEVCTL2: 1165 case PCI_EXP_LNKCAP2: 1166 case PCI_EXP_LNKCTL2: 1167 case PCI_EXP_LNKSTA2: 1168 return pcie_cap_version(dev) > 1; 1169 default: 1170 return false; 1171 } 1172 } 1173 1174 static inline int 1175 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1176 { 1177 if (pos & 3) 1178 return -EINVAL; 1179 1180 if (!pcie_capability_reg_implemented(dev, pos)) 1181 return -EINVAL; 1182 1183 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1184 } 1185 1186 static inline int 1187 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1188 { 1189 if (pos & 3) 1190 return -EINVAL; 1191 1192 if (!pcie_capability_reg_implemented(dev, pos)) 1193 return -EINVAL; 1194 1195 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1196 } 1197 1198 static inline int 1199 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1200 { 1201 if (pos & 1) 1202 return -EINVAL; 1203 1204 if (!pcie_capability_reg_implemented(dev, pos)) 1205 return 0; 1206 1207 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1208 } 1209 1210 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1211 enum pci_bus_speed *speed, enum pcie_link_width *width) 1212 { 1213 *speed = PCI_SPEED_UNKNOWN; 1214 *width = PCIE_LNK_WIDTH_UNKNOWN; 1215 return (0); 1216 } 1217 1218 static inline int 1219 pci_num_vf(struct pci_dev *dev) 1220 { 1221 return (0); 1222 } 1223 1224 static inline enum pci_bus_speed 1225 pcie_get_speed_cap(struct pci_dev *dev) 1226 { 1227 device_t root; 1228 uint32_t lnkcap, lnkcap2; 1229 int error, pos; 1230 1231 root = device_get_parent(dev->dev.bsddev); 1232 if (root == NULL) 1233 return (PCI_SPEED_UNKNOWN); 1234 root = device_get_parent(root); 1235 if (root == NULL) 1236 return (PCI_SPEED_UNKNOWN); 1237 root = device_get_parent(root); 1238 if (root == NULL) 1239 return (PCI_SPEED_UNKNOWN); 1240 1241 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1242 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1243 return (PCI_SPEED_UNKNOWN); 1244 1245 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1246 return (PCI_SPEED_UNKNOWN); 1247 1248 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1249 1250 if (lnkcap2) { /* PCIe r3.0-compliant */ 1251 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1252 return (PCIE_SPEED_2_5GT); 1253 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1254 return (PCIE_SPEED_5_0GT); 1255 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1256 return (PCIE_SPEED_8_0GT); 1257 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1258 return (PCIE_SPEED_16_0GT); 1259 } else { /* pre-r3.0 */ 1260 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1261 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1262 return (PCIE_SPEED_2_5GT); 1263 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1264 return (PCIE_SPEED_5_0GT); 1265 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1266 return (PCIE_SPEED_8_0GT); 1267 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1268 return (PCIE_SPEED_16_0GT); 1269 } 1270 return (PCI_SPEED_UNKNOWN); 1271 } 1272 1273 static inline enum pcie_link_width 1274 pcie_get_width_cap(struct pci_dev *dev) 1275 { 1276 uint32_t lnkcap; 1277 1278 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1279 if (lnkcap) 1280 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1281 1282 return (PCIE_LNK_WIDTH_UNKNOWN); 1283 } 1284 1285 static inline int 1286 pcie_get_mps(struct pci_dev *dev) 1287 { 1288 return (pci_get_max_payload(dev->dev.bsddev)); 1289 } 1290 1291 static inline uint32_t 1292 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1293 { 1294 1295 switch(spd) { 1296 case PCIE_SPEED_16_0GT: 1297 return (16000 * 128 / 130); 1298 case PCIE_SPEED_8_0GT: 1299 return (8000 * 128 / 130); 1300 case PCIE_SPEED_5_0GT: 1301 return (5000 * 8 / 10); 1302 case PCIE_SPEED_2_5GT: 1303 return (2500 * 8 / 10); 1304 default: 1305 return (0); 1306 } 1307 } 1308 1309 static inline uint32_t 1310 pcie_bandwidth_available(struct pci_dev *pdev, 1311 struct pci_dev **limiting, 1312 enum pci_bus_speed *speed, 1313 enum pcie_link_width *width) 1314 { 1315 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1316 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1317 1318 if (speed) 1319 *speed = nspeed; 1320 if (width) 1321 *width = nwidth; 1322 1323 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1324 } 1325 1326 static inline struct pci_dev * 1327 pcie_find_root_port(struct pci_dev *pdev) 1328 { 1329 device_t root; 1330 1331 if (pdev->root != NULL) 1332 return (pdev->root); 1333 1334 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1335 if (root == NULL) 1336 return (NULL); 1337 1338 pdev->root = lkpinew_pci_dev(root); 1339 return (pdev->root); 1340 } 1341 1342 /* This is needed when people rip out the device "HotPlug". */ 1343 static inline void 1344 pci_lock_rescan_remove(void) 1345 { 1346 } 1347 1348 static inline void 1349 pci_unlock_rescan_remove(void) 1350 { 1351 } 1352 1353 static __inline void 1354 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1355 { 1356 } 1357 1358 /* 1359 * The following functions can be used to attach/detach the LinuxKPI's 1360 * PCI device runtime. The pci_driver and pci_device_id pointer is 1361 * allowed to be NULL. Other pointers must be all valid. 1362 * The pci_dev structure should be zero-initialized before passed 1363 * to the linux_pci_attach_device function. 1364 */ 1365 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1366 const struct pci_device_id *, struct pci_dev *); 1367 extern int linux_pci_detach_device(struct pci_dev *); 1368 1369 static inline int 1370 pci_dev_present(const struct pci_device_id *cur) 1371 { 1372 while (cur != NULL && (cur->vendor || cur->device)) { 1373 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1374 return (1); 1375 } 1376 cur++; 1377 } 1378 return (0); 1379 } 1380 1381 static inline bool 1382 pci_is_root_bus(struct pci_bus *pbus) 1383 { 1384 1385 return (pbus->self == NULL); 1386 } 1387 1388 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1389 unsigned int bus, unsigned int devfn); 1390 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1391 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1392 1393 static inline int 1394 pci_domain_nr(struct pci_bus *pbus) 1395 { 1396 1397 return (pbus->domain); 1398 } 1399 1400 static inline int 1401 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1402 int pos, uint32_t *val, int len) 1403 { 1404 1405 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1406 return (0); 1407 } 1408 1409 static inline int 1410 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1411 { 1412 uint32_t tmp; 1413 int ret; 1414 1415 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1416 *val = (u16)tmp; 1417 return (ret); 1418 } 1419 1420 static inline int 1421 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1422 { 1423 uint32_t tmp; 1424 int ret; 1425 1426 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1427 *val = (u8)tmp; 1428 return (ret); 1429 } 1430 1431 static inline int 1432 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1433 uint32_t val, int size) 1434 { 1435 1436 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1437 return (0); 1438 } 1439 1440 static inline int 1441 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1442 uint8_t val) 1443 { 1444 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1445 } 1446 1447 static inline int 1448 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1449 uint16_t val) 1450 { 1451 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1452 } 1453 1454 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1455 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1456 1457 /* -------------------------------------------------------------------------- */ 1458 1459 static inline int 1460 pcim_enable_device(struct pci_dev *pdev) 1461 { 1462 struct pci_devres *dr; 1463 int error; 1464 1465 /* Here we cannot run through the pdev->managed check. */ 1466 dr = lkpi_pci_devres_get_alloc(pdev); 1467 if (dr == NULL) 1468 return (-ENOMEM); 1469 1470 /* If resources were enabled before do not do it again. */ 1471 if (dr->enable_io) 1472 return (0); 1473 1474 error = pci_enable_device(pdev); 1475 if (error == 0) 1476 dr->enable_io = true; 1477 1478 /* This device is not managed. */ 1479 pdev->managed = true; 1480 1481 return (error); 1482 } 1483 1484 static inline struct pcim_iomap_devres * 1485 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev) 1486 { 1487 struct pcim_iomap_devres *dr; 1488 1489 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release, 1490 NULL, NULL); 1491 if (dr == NULL) { 1492 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release, 1493 sizeof(*dr), GFP_KERNEL | __GFP_ZERO); 1494 if (dr != NULL) 1495 lkpi_devres_add(&pdev->dev, dr); 1496 } 1497 1498 if (dr == NULL) 1499 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__); 1500 1501 return (dr); 1502 } 1503 1504 static inline void __iomem ** 1505 pcim_iomap_table(struct pci_dev *pdev) 1506 { 1507 struct pcim_iomap_devres *dr; 1508 1509 dr = lkpi_pcim_iomap_devres_find(pdev); 1510 if (dr == NULL) 1511 return (NULL); 1512 1513 /* 1514 * If the driver has manually set a flag to be able to request the 1515 * resource to use bus_read/write_<n>, return the shadow table. 1516 */ 1517 if (pdev->want_iomap_res) 1518 return ((void **)dr->res_table); 1519 1520 /* This is the Linux default. */ 1521 return (dr->mmio_table); 1522 } 1523 1524 static inline int 1525 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1526 { 1527 struct pcim_iomap_devres *dr; 1528 void *res; 1529 uint32_t mappings, requests, req_mask; 1530 int bar, error; 1531 1532 dr = lkpi_pcim_iomap_devres_find(pdev); 1533 if (dr == NULL) 1534 return (-ENOMEM); 1535 1536 /* Request all the BARs ("regions") we do not iomap. */ 1537 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1538 for (bar = requests = 0; requests != req_mask; bar++) { 1539 if ((req_mask & (1 << bar)) == 0) 1540 continue; 1541 error = pci_request_region(pdev, bar, name); 1542 if (error != 0 && error != -ENODEV) 1543 goto err; 1544 requests |= (1 << bar); 1545 } 1546 1547 /* Now iomap all the requested (by "mask") ones. */ 1548 for (bar = mappings = 0; mappings != mask; bar++) { 1549 if ((mask & (1 << bar)) == 0) 1550 continue; 1551 1552 /* Request double is not allowed. */ 1553 if (dr->mmio_table[bar] != NULL) { 1554 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1555 __func__, bar, dr->mmio_table[bar]); 1556 goto err; 1557 } 1558 1559 res = _lkpi_pci_iomap(pdev, bar, 0); 1560 if (res == NULL) 1561 goto err; 1562 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1563 dr->res_table[bar] = res; 1564 1565 mappings |= (1 << bar); 1566 } 1567 1568 return (0); 1569 1570 err: 1571 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1572 if ((mappings & (1 << bar)) != 0) { 1573 res = dr->mmio_table[bar]; 1574 if (res == NULL) 1575 continue; 1576 pci_iounmap(pdev, res); 1577 } else if ((requests & (1 << bar)) != 0) { 1578 pci_release_region(pdev, bar); 1579 } 1580 } 1581 1582 return (-EINVAL); 1583 } 1584 1585 /* This is a FreeBSD extension so we can use bus_*(). */ 1586 static inline void 1587 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1588 { 1589 pdev->want_iomap_res = true; 1590 } 1591 1592 #endif /* _LINUXKPI_LINUX_PCI_H_ */ 1593