1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUX_PCI_H_ 36 #define _LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <sys/rman.h> 47 #include <sys/bus.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 #define MODULE_DEVICE_TABLE(bus, table) 74 75 #define PCI_ANY_ID -1U 76 77 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 78 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 79 #define PCI_FUNC(devfn) ((devfn) & 0x07) 80 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 81 82 #define PCI_VDEVICE(_vendor, _device) \ 83 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 84 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 85 #define PCI_DEVICE(_vendor, _device) \ 86 .vendor = (_vendor), .device = (_device), \ 87 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 88 89 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 90 91 #define PCI_VENDOR_ID PCIR_DEVVENDOR 92 #define PCI_COMMAND PCIR_COMMAND 93 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 94 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 95 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 96 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 97 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 98 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 99 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 100 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 101 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 102 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 103 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 104 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 105 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 106 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 107 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 108 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 109 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 110 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 111 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 112 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 113 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 114 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 115 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 116 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 117 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 118 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 119 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 120 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 121 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 122 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 123 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 124 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 125 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 126 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 127 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 128 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 129 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 130 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 131 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 132 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 133 #define PCI_EXP_LNKCTL2_TLS 0x000f 134 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 135 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 136 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 137 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 138 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 139 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 140 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 141 142 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 143 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 144 #define PCI_EXP_DEVSTA_TRPND 0x0020 145 146 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 147 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 148 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 149 150 enum pci_bus_speed { 151 PCI_SPEED_UNKNOWN = -1, 152 PCIE_SPEED_2_5GT, 153 PCIE_SPEED_5_0GT, 154 PCIE_SPEED_8_0GT, 155 PCIE_SPEED_16_0GT, 156 }; 157 158 enum pcie_link_width { 159 PCIE_LNK_WIDTH_RESRV = 0x00, 160 PCIE_LNK_X1 = 0x01, 161 PCIE_LNK_X2 = 0x02, 162 PCIE_LNK_X4 = 0x04, 163 PCIE_LNK_X8 = 0x08, 164 PCIE_LNK_X12 = 0x0c, 165 PCIE_LNK_X16 = 0x10, 166 PCIE_LNK_X32 = 0x20, 167 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 168 }; 169 170 #define PCIE_LINK_STATE_L0S 0x00000001 171 #define PCIE_LINK_STATE_L1 0x00000002 172 #define PCIE_LINK_STATE_CLKPM 0x00000004 173 174 typedef int pci_power_t; 175 176 #define PCI_D0 PCI_POWERSTATE_D0 177 #define PCI_D1 PCI_POWERSTATE_D1 178 #define PCI_D2 PCI_POWERSTATE_D2 179 #define PCI_D3hot PCI_POWERSTATE_D3 180 #define PCI_D3cold 4 181 182 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 183 184 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 185 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 186 187 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 188 189 struct pci_dev; 190 191 struct pci_driver { 192 struct list_head links; 193 char *name; 194 const struct pci_device_id *id_table; 195 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 196 void (*remove)(struct pci_dev *dev); 197 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 198 int (*resume) (struct pci_dev *dev); /* Device woken up */ 199 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 200 driver_t bsddriver; 201 devclass_t bsdclass; 202 struct device_driver driver; 203 const struct pci_error_handlers *err_handler; 204 bool isdrm; 205 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 206 const nvlist_t *pf_config); 207 void (*bsd_iov_uninit)(device_t dev); 208 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 209 const nvlist_t *vf_config); 210 }; 211 212 struct pci_bus { 213 struct pci_dev *self; 214 int domain; 215 int number; 216 }; 217 218 extern struct list_head pci_drivers; 219 extern struct list_head pci_devices; 220 extern spinlock_t pci_lock; 221 222 #define __devexit_p(x) x 223 224 /* 225 * If we find drivers accessing this from multiple KPIs we may have to 226 * refcount objects of this structure. 227 */ 228 struct pci_mmio_region { 229 TAILQ_ENTRY(pci_mmio_region) next; 230 struct resource *res; 231 int rid; 232 int type; 233 }; 234 235 struct pci_dev { 236 struct device dev; 237 struct list_head links; 238 struct pci_driver *pdrv; 239 struct pci_bus *bus; 240 uint16_t device; 241 uint16_t vendor; 242 uint16_t subsystem_vendor; 243 uint16_t subsystem_device; 244 unsigned int irq; 245 unsigned int devfn; 246 uint32_t class; 247 uint8_t revision; 248 bool msi_enabled; 249 250 TAILQ_HEAD(, pci_mmio_region) mmio; 251 252 /* Add all new items at the end of the list in 13 */ 253 struct pci_dev *root; 254 phys_addr_t rom; 255 size_t romlen; 256 bool managed; /* devres "pcim_*(). */ 257 bool want_iomap_res; 258 bool msix_enabled; 259 }; 260 261 /* XXX add kassert here on the mmio offset */ 262 263 /* We need some meta-struct to keep track of these for devres. */ 264 struct pci_devres { 265 bool enable_io; 266 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 267 uint8_t region_mask; 268 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 269 }; 270 struct pcim_iomap_devres { 271 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 272 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 273 }; 274 275 /* Internal helper function(s). */ 276 struct pci_dev *lkpinew_pci_dev(device_t); 277 void lkpi_pci_devres_release(struct device *, void *); 278 void lkpi_pcim_iomap_table_release(struct device *, void *); 279 280 static inline int 281 pci_resource_type(struct pci_dev *pdev, int bar) 282 { 283 struct pci_map *pm; 284 285 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 286 if (!pm) 287 return (-1); 288 289 if (PCI_BAR_IO(pm->pm_value)) 290 return (SYS_RES_IOPORT); 291 else 292 return (SYS_RES_MEMORY); 293 } 294 295 static inline struct resource_list_entry * 296 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 297 { 298 struct pci_devinfo *dinfo; 299 struct resource_list *rl; 300 301 dinfo = device_get_ivars(pdev->dev.bsddev); 302 rl = &dinfo->resources; 303 return resource_list_find(rl, type, rid); 304 } 305 306 static inline struct resource_list_entry * 307 linux_pci_get_bar(struct pci_dev *pdev, int bar) 308 { 309 int type; 310 311 type = pci_resource_type(pdev, bar); 312 if (type < 0) 313 return (NULL); 314 bar = PCIR_BAR(bar); 315 return (linux_pci_get_rle(pdev, type, bar)); 316 } 317 318 static inline struct device * 319 linux_pci_find_irq_dev(unsigned int irq) 320 { 321 struct pci_dev *pdev; 322 struct device *found; 323 324 found = NULL; 325 spin_lock(&pci_lock); 326 list_for_each_entry(pdev, &pci_devices, links) { 327 if (irq == pdev->dev.irq || 328 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 329 found = &pdev->dev; 330 break; 331 } 332 } 333 spin_unlock(&pci_lock); 334 return (found); 335 } 336 337 /* 338 * All drivers just seem to want to inspect the type not flags. 339 */ 340 static inline int 341 pci_resource_flags(struct pci_dev *pdev, int bar) 342 { 343 int type; 344 345 type = pci_resource_type(pdev, bar); 346 if (type < 0) 347 return (0); 348 return (1 << type); 349 } 350 351 static inline const char * 352 pci_name(struct pci_dev *d) 353 { 354 355 return device_get_desc(d->dev.bsddev); 356 } 357 358 static inline void * 359 pci_get_drvdata(struct pci_dev *pdev) 360 { 361 362 return dev_get_drvdata(&pdev->dev); 363 } 364 365 static inline void 366 pci_set_drvdata(struct pci_dev *pdev, void *data) 367 { 368 369 dev_set_drvdata(&pdev->dev, data); 370 } 371 372 static inline struct pci_dev * 373 pci_dev_get(struct pci_dev *pdev) 374 { 375 376 if (pdev != NULL) 377 get_device(&pdev->dev); 378 return (pdev); 379 } 380 381 static __inline void 382 pci_dev_put(struct pci_dev *pdev) 383 { 384 385 if (pdev != NULL) 386 put_device(&pdev->dev); 387 } 388 389 static inline int 390 pci_enable_device(struct pci_dev *pdev) 391 { 392 393 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 394 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 395 return (0); 396 } 397 398 static inline void 399 pci_disable_device(struct pci_dev *pdev) 400 { 401 402 pci_disable_busmaster(pdev->dev.bsddev); 403 } 404 405 static inline int 406 pci_set_master(struct pci_dev *pdev) 407 { 408 409 pci_enable_busmaster(pdev->dev.bsddev); 410 return (0); 411 } 412 413 static inline int 414 pci_set_power_state(struct pci_dev *pdev, int state) 415 { 416 417 pci_set_powerstate(pdev->dev.bsddev, state); 418 return (0); 419 } 420 421 static inline int 422 pci_clear_master(struct pci_dev *pdev) 423 { 424 425 pci_disable_busmaster(pdev->dev.bsddev); 426 return (0); 427 } 428 429 static inline struct pci_devres * 430 lkpi_pci_devres_get_alloc(struct pci_dev *pdev) 431 { 432 struct pci_devres *dr; 433 434 dr = lkpi_devres_find(&pdev->dev, lkpi_pci_devres_release, NULL, NULL); 435 if (dr == NULL) { 436 dr = lkpi_devres_alloc(lkpi_pci_devres_release, sizeof(*dr), 437 GFP_KERNEL | __GFP_ZERO); 438 if (dr != NULL) 439 lkpi_devres_add(&pdev->dev, dr); 440 } 441 442 return (dr); 443 } 444 static inline struct pci_devres * 445 lkpi_pci_devres_find(struct pci_dev *pdev) 446 { 447 448 if (!pdev->managed) 449 return (NULL); 450 451 return (lkpi_pci_devres_get_alloc(pdev)); 452 } 453 454 static inline int 455 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 456 { 457 struct resource *res; 458 struct pci_devres *dr; 459 struct pci_mmio_region *mmio; 460 int rid; 461 int type; 462 463 type = pci_resource_type(pdev, bar); 464 if (type < 0) 465 return (-ENODEV); 466 rid = PCIR_BAR(bar); 467 res = bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 468 RF_ACTIVE|RF_SHAREABLE); 469 if (res == NULL) { 470 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 471 "bar %d type %d rid %d\n", 472 __func__, bar, type, PCIR_BAR(bar)); 473 return (-ENODEV); 474 } 475 476 /* 477 * It seems there is an implicit devres tracking on these if the device 478 * is managed; otherwise the resources are not automatiaclly freed on 479 * FreeBSD/LinuxKPI tough they should be/are expected to be by Linux 480 * drivers. 481 */ 482 dr = lkpi_pci_devres_find(pdev); 483 if (dr != NULL) { 484 dr->region_mask |= (1 << bar); 485 dr->region_table[bar] = res; 486 } 487 488 /* Even if the device is not managed we need to track it for iomap. */ 489 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 490 mmio->rid = PCIR_BAR(bar); 491 mmio->type = type; 492 mmio->res = res; 493 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 494 495 return (0); 496 } 497 498 static inline void 499 pci_release_region(struct pci_dev *pdev, int bar) 500 { 501 struct resource_list_entry *rle; 502 struct pci_devres *dr; 503 struct pci_mmio_region *mmio, *p; 504 505 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 506 return; 507 508 /* 509 * As we implicitly track the requests we also need to clear them on 510 * release. Do clear before resource release. 511 */ 512 dr = lkpi_pci_devres_find(pdev); 513 if (dr != NULL) { 514 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 515 " region_table res %p != rel->res %p\n", __func__, pdev, 516 bar, dr->region_table[bar], rle->res)); 517 dr->region_table[bar] = NULL; 518 dr->region_mask &= ~(1 << bar); 519 } 520 521 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 522 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 523 continue; 524 TAILQ_REMOVE(&pdev->mmio, mmio, next); 525 free(mmio, M_DEVBUF); 526 } 527 528 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 529 } 530 531 static inline void 532 pci_release_regions(struct pci_dev *pdev) 533 { 534 int i; 535 536 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 537 pci_release_region(pdev, i); 538 } 539 540 static inline int 541 pci_request_regions(struct pci_dev *pdev, const char *res_name) 542 { 543 int error; 544 int i; 545 546 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 547 error = pci_request_region(pdev, i, res_name); 548 if (error && error != -ENODEV) { 549 pci_release_regions(pdev); 550 return (error); 551 } 552 } 553 return (0); 554 } 555 556 static inline void 557 lkpi_pci_disable_msix(struct pci_dev *pdev) 558 { 559 560 pci_release_msi(pdev->dev.bsddev); 561 562 /* 563 * The MSIX IRQ numbers associated with this PCI device are no 564 * longer valid and might be re-assigned. Make sure 565 * linux_pci_find_irq_dev() does no longer see them by 566 * resetting their references to zero: 567 */ 568 pdev->dev.irq_start = 0; 569 pdev->dev.irq_end = 0; 570 pdev->msix_enabled = false; 571 } 572 /* Only for consistency. No conflict on that one. */ 573 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 574 575 static inline void 576 lkpi_pci_disable_msi(struct pci_dev *pdev) 577 { 578 579 pci_release_msi(pdev->dev.bsddev); 580 581 pdev->dev.irq_start = 0; 582 pdev->dev.irq_end = 0; 583 pdev->irq = pdev->dev.irq; 584 pdev->msi_enabled = false; 585 } 586 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 587 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 588 589 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 590 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 591 592 static inline bus_addr_t 593 pci_bus_address(struct pci_dev *pdev, int bar) 594 { 595 596 return (pci_resource_start(pdev, bar)); 597 } 598 599 #define PCI_CAP_ID_EXP PCIY_EXPRESS 600 #define PCI_CAP_ID_PCIX PCIY_PCIX 601 #define PCI_CAP_ID_AGP PCIY_AGP 602 #define PCI_CAP_ID_PM PCIY_PMG 603 604 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 605 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 606 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 607 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 608 #define PCI_EXP_LNKSTA PCIER_LINK_STA 609 610 static inline int 611 pci_find_capability(struct pci_dev *pdev, int capid) 612 { 613 int reg; 614 615 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 616 return (0); 617 return (reg); 618 } 619 620 static inline int pci_pcie_cap(struct pci_dev *dev) 621 { 622 return pci_find_capability(dev, PCI_CAP_ID_EXP); 623 } 624 625 static inline int 626 pci_find_ext_capability(struct pci_dev *pdev, int capid) 627 { 628 int reg; 629 630 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 631 return (0); 632 return (reg); 633 } 634 635 #define PCIM_PCAP_PME_SHIFT 11 636 static __inline bool 637 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 638 { 639 struct pci_devinfo *dinfo; 640 pcicfgregs *cfg; 641 642 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 643 return (false); 644 645 dinfo = device_get_ivars(pdev->dev.bsddev); 646 cfg = &dinfo->cfg; 647 648 if (cfg->pp.pp_cap == 0) 649 return (false); 650 651 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 652 return (true); 653 654 return (false); 655 } 656 657 static inline int 658 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 659 { 660 661 if (!pci_enable_aspm) 662 return (-EPERM); 663 664 return (-ENXIO); 665 } 666 667 static inline int 668 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 669 { 670 671 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 672 return (0); 673 } 674 675 static inline int 676 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 677 { 678 679 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 680 return (0); 681 } 682 683 static inline int 684 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 685 { 686 687 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 688 return (0); 689 } 690 691 static inline int 692 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 693 { 694 695 pci_write_config(pdev->dev.bsddev, where, val, 1); 696 return (0); 697 } 698 699 static inline int 700 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 701 { 702 703 pci_write_config(pdev->dev.bsddev, where, val, 2); 704 return (0); 705 } 706 707 static inline int 708 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 709 { 710 711 pci_write_config(pdev->dev.bsddev, where, val, 4); 712 return (0); 713 } 714 715 int linux_pci_register_driver(struct pci_driver *pdrv); 716 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 717 void linux_pci_unregister_driver(struct pci_driver *pdrv); 718 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 719 720 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 721 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 722 723 struct msix_entry { 724 int entry; 725 int vector; 726 }; 727 728 /* 729 * Enable msix, positive errors indicate actual number of available 730 * vectors. Negative errors are failures. 731 * 732 * NB: define added to prevent this definition of pci_enable_msix from 733 * clashing with the native FreeBSD version. 734 */ 735 #define pci_enable_msix(...) \ 736 linux_pci_enable_msix(__VA_ARGS__) 737 738 static inline int 739 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 740 { 741 struct resource_list_entry *rle; 742 int error; 743 int avail; 744 int i; 745 746 avail = pci_msix_count(pdev->dev.bsddev); 747 if (avail < nreq) { 748 if (avail == 0) 749 return -EINVAL; 750 return avail; 751 } 752 avail = nreq; 753 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 754 return error; 755 /* 756 * Handle case where "pci_alloc_msix()" may allocate less 757 * interrupts than available and return with no error: 758 */ 759 if (avail < nreq) { 760 pci_release_msi(pdev->dev.bsddev); 761 return avail; 762 } 763 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 764 pdev->dev.irq_start = rle->start; 765 pdev->dev.irq_end = rle->start + avail; 766 for (i = 0; i < nreq; i++) 767 entries[i].vector = pdev->dev.irq_start + i; 768 pdev->msix_enabled = true; 769 return (0); 770 } 771 772 #define pci_enable_msix_range(...) \ 773 linux_pci_enable_msix_range(__VA_ARGS__) 774 775 static inline int 776 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 777 int minvec, int maxvec) 778 { 779 int nvec = maxvec; 780 int rc; 781 782 if (maxvec < minvec) 783 return (-ERANGE); 784 785 do { 786 rc = pci_enable_msix(dev, entries, nvec); 787 if (rc < 0) { 788 return (rc); 789 } else if (rc > 0) { 790 if (rc < minvec) 791 return (-ENOSPC); 792 nvec = rc; 793 } 794 } while (rc); 795 return (nvec); 796 } 797 798 #define pci_enable_msi(pdev) \ 799 linux_pci_enable_msi(pdev) 800 801 static inline int 802 pci_enable_msi(struct pci_dev *pdev) 803 { 804 struct resource_list_entry *rle; 805 int error; 806 int avail; 807 808 avail = pci_msi_count(pdev->dev.bsddev); 809 if (avail < 1) 810 return -EINVAL; 811 812 avail = 1; /* this function only enable one MSI IRQ */ 813 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 814 return error; 815 816 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 817 pdev->dev.irq_start = rle->start; 818 pdev->dev.irq_end = rle->start + avail; 819 pdev->irq = rle->start; 820 pdev->msi_enabled = true; 821 return (0); 822 } 823 824 static inline int 825 pci_channel_offline(struct pci_dev *pdev) 826 { 827 828 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 829 } 830 831 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 832 { 833 return -ENODEV; 834 } 835 static inline void pci_disable_sriov(struct pci_dev *dev) 836 { 837 } 838 839 static inline struct resource * 840 _lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size __unused) 841 { 842 struct pci_mmio_region *mmio, *p; 843 int type; 844 845 type = pci_resource_type(pdev, bar); 846 if (type < 0) { 847 device_printf(pdev->dev.bsddev, "%s: bar %d type %d\n", 848 __func__, bar, type); 849 return (NULL); 850 } 851 852 /* 853 * Check for duplicate mappings. 854 * This can happen if a driver calls pci_request_region() first. 855 */ 856 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 857 if (mmio->type == type && mmio->rid == PCIR_BAR(bar)) { 858 return (mmio->res); 859 } 860 } 861 862 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 863 mmio->rid = PCIR_BAR(bar); 864 mmio->type = type; 865 mmio->res = bus_alloc_resource_any(pdev->dev.bsddev, mmio->type, 866 &mmio->rid, RF_ACTIVE|RF_SHAREABLE); 867 if (mmio->res == NULL) { 868 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 869 "bar %d type %d rid %d\n", 870 __func__, bar, type, PCIR_BAR(bar)); 871 free(mmio, M_DEVBUF); 872 return (NULL); 873 } 874 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 875 876 return (mmio->res); 877 } 878 879 static inline void * 880 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 881 { 882 struct resource *res; 883 884 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 885 if (res == NULL) 886 return (NULL); 887 /* This is a FreeBSD extension so we can use bus_*(). */ 888 if (pdev->want_iomap_res) 889 return (res); 890 return ((void *)rman_get_bushandle(res)); 891 } 892 893 static inline void 894 pci_iounmap(struct pci_dev *pdev, void *res) 895 { 896 struct pci_mmio_region *mmio, *p; 897 898 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 899 if (res != (void *)rman_get_bushandle(mmio->res)) 900 continue; 901 bus_release_resource(pdev->dev.bsddev, 902 mmio->type, mmio->rid, mmio->res); 903 TAILQ_REMOVE(&pdev->mmio, mmio, next); 904 free(mmio, M_DEVBUF); 905 return; 906 } 907 } 908 909 static inline void 910 lkpi_pci_save_state(struct pci_dev *pdev) 911 { 912 913 pci_save_state(pdev->dev.bsddev); 914 } 915 916 static inline void 917 lkpi_pci_restore_state(struct pci_dev *pdev) 918 { 919 920 pci_restore_state(pdev->dev.bsddev); 921 } 922 923 #define pci_save_state(dev) lkpi_pci_save_state(dev) 924 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 925 926 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 927 const struct pci_device_id _table[] __devinitdata 928 929 /* XXX This should not be necessary. */ 930 #define pcix_set_mmrbc(d, v) 0 931 #define pcix_get_max_mmrbc(d) 0 932 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 933 934 #define PCI_DMA_BIDIRECTIONAL 0 935 #define PCI_DMA_TODEVICE 1 936 #define PCI_DMA_FROMDEVICE 2 937 #define PCI_DMA_NONE 3 938 939 #define pci_pool dma_pool 940 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 941 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 942 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 943 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 944 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 945 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 946 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 947 _size, _vaddr, _dma_handle) 948 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 949 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 950 _sg, _nents, (enum dma_data_direction)_dir) 951 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 952 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 953 (_ptr), (_size), (enum dma_data_direction)_dir) 954 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 955 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 956 _addr, _size, (enum dma_data_direction)_dir) 957 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 958 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 959 _sg, _nents, (enum dma_data_direction)_dir) 960 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 961 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 962 _offset, _size, (enum dma_data_direction)_dir) 963 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 964 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 965 _dma_address, _size, (enum dma_data_direction)_dir) 966 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 967 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 968 dma_mapping_error(&(_pdev)->dev, _dma_addr) 969 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 970 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 971 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 972 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 973 #define pci_unmap_addr dma_unmap_addr 974 #define pci_unmap_addr_set dma_unmap_addr_set 975 #define pci_unmap_len dma_unmap_len 976 #define pci_unmap_len_set dma_unmap_len_set 977 978 typedef unsigned int __bitwise pci_channel_state_t; 979 typedef unsigned int __bitwise pci_ers_result_t; 980 981 enum pci_channel_state { 982 pci_channel_io_normal = 1, 983 pci_channel_io_frozen = 2, 984 pci_channel_io_perm_failure = 3, 985 }; 986 987 enum pci_ers_result { 988 PCI_ERS_RESULT_NONE = 1, 989 PCI_ERS_RESULT_CAN_RECOVER = 2, 990 PCI_ERS_RESULT_NEED_RESET = 3, 991 PCI_ERS_RESULT_DISCONNECT = 4, 992 PCI_ERS_RESULT_RECOVERED = 5, 993 }; 994 995 /* PCI bus error event callbacks */ 996 struct pci_error_handlers { 997 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 998 enum pci_channel_state error); 999 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1000 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1001 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1002 void (*resume)(struct pci_dev *dev); 1003 }; 1004 1005 /* FreeBSD does not support SRIOV - yet */ 1006 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1007 { 1008 return dev; 1009 } 1010 1011 static inline bool pci_is_pcie(struct pci_dev *dev) 1012 { 1013 return !!pci_pcie_cap(dev); 1014 } 1015 1016 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1017 { 1018 int pos; 1019 u16 reg16; 1020 1021 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1022 if (!pos) 1023 return 0; 1024 1025 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1026 1027 return reg16; 1028 } 1029 1030 static inline int pci_pcie_type(struct pci_dev *dev) 1031 { 1032 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1033 } 1034 1035 static inline int pcie_cap_version(struct pci_dev *dev) 1036 { 1037 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1038 } 1039 1040 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1041 { 1042 int type = pci_pcie_type(dev); 1043 1044 return pcie_cap_version(dev) > 1 || 1045 type == PCI_EXP_TYPE_ROOT_PORT || 1046 type == PCI_EXP_TYPE_ENDPOINT || 1047 type == PCI_EXP_TYPE_LEG_END; 1048 } 1049 1050 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1051 { 1052 return true; 1053 } 1054 1055 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1056 { 1057 int type = pci_pcie_type(dev); 1058 1059 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1060 (type == PCI_EXP_TYPE_DOWNSTREAM && 1061 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1062 } 1063 1064 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1065 { 1066 int type = pci_pcie_type(dev); 1067 1068 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1069 type == PCI_EXP_TYPE_RC_EC; 1070 } 1071 1072 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1073 { 1074 if (!pci_is_pcie(dev)) 1075 return false; 1076 1077 switch (pos) { 1078 case PCI_EXP_FLAGS_TYPE: 1079 return true; 1080 case PCI_EXP_DEVCAP: 1081 case PCI_EXP_DEVCTL: 1082 case PCI_EXP_DEVSTA: 1083 return pcie_cap_has_devctl(dev); 1084 case PCI_EXP_LNKCAP: 1085 case PCI_EXP_LNKCTL: 1086 case PCI_EXP_LNKSTA: 1087 return pcie_cap_has_lnkctl(dev); 1088 case PCI_EXP_SLTCAP: 1089 case PCI_EXP_SLTCTL: 1090 case PCI_EXP_SLTSTA: 1091 return pcie_cap_has_sltctl(dev); 1092 case PCI_EXP_RTCTL: 1093 case PCI_EXP_RTCAP: 1094 case PCI_EXP_RTSTA: 1095 return pcie_cap_has_rtctl(dev); 1096 case PCI_EXP_DEVCAP2: 1097 case PCI_EXP_DEVCTL2: 1098 case PCI_EXP_LNKCAP2: 1099 case PCI_EXP_LNKCTL2: 1100 case PCI_EXP_LNKSTA2: 1101 return pcie_cap_version(dev) > 1; 1102 default: 1103 return false; 1104 } 1105 } 1106 1107 static inline int 1108 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1109 { 1110 if (pos & 3) 1111 return -EINVAL; 1112 1113 if (!pcie_capability_reg_implemented(dev, pos)) 1114 return -EINVAL; 1115 1116 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1117 } 1118 1119 static inline int 1120 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1121 { 1122 if (pos & 3) 1123 return -EINVAL; 1124 1125 if (!pcie_capability_reg_implemented(dev, pos)) 1126 return -EINVAL; 1127 1128 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1129 } 1130 1131 static inline int 1132 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1133 { 1134 if (pos & 1) 1135 return -EINVAL; 1136 1137 if (!pcie_capability_reg_implemented(dev, pos)) 1138 return 0; 1139 1140 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1141 } 1142 1143 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1144 enum pci_bus_speed *speed, enum pcie_link_width *width) 1145 { 1146 *speed = PCI_SPEED_UNKNOWN; 1147 *width = PCIE_LNK_WIDTH_UNKNOWN; 1148 return (0); 1149 } 1150 1151 static inline int 1152 pci_num_vf(struct pci_dev *dev) 1153 { 1154 return (0); 1155 } 1156 1157 static inline enum pci_bus_speed 1158 pcie_get_speed_cap(struct pci_dev *dev) 1159 { 1160 device_t root; 1161 uint32_t lnkcap, lnkcap2; 1162 int error, pos; 1163 1164 root = device_get_parent(dev->dev.bsddev); 1165 if (root == NULL) 1166 return (PCI_SPEED_UNKNOWN); 1167 root = device_get_parent(root); 1168 if (root == NULL) 1169 return (PCI_SPEED_UNKNOWN); 1170 root = device_get_parent(root); 1171 if (root == NULL) 1172 return (PCI_SPEED_UNKNOWN); 1173 1174 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1175 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1176 return (PCI_SPEED_UNKNOWN); 1177 1178 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1179 return (PCI_SPEED_UNKNOWN); 1180 1181 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1182 1183 if (lnkcap2) { /* PCIe r3.0-compliant */ 1184 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1185 return (PCIE_SPEED_2_5GT); 1186 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1187 return (PCIE_SPEED_5_0GT); 1188 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1189 return (PCIE_SPEED_8_0GT); 1190 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1191 return (PCIE_SPEED_16_0GT); 1192 } else { /* pre-r3.0 */ 1193 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1194 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1195 return (PCIE_SPEED_2_5GT); 1196 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1197 return (PCIE_SPEED_5_0GT); 1198 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1199 return (PCIE_SPEED_8_0GT); 1200 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1201 return (PCIE_SPEED_16_0GT); 1202 } 1203 return (PCI_SPEED_UNKNOWN); 1204 } 1205 1206 static inline enum pcie_link_width 1207 pcie_get_width_cap(struct pci_dev *dev) 1208 { 1209 uint32_t lnkcap; 1210 1211 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1212 if (lnkcap) 1213 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1214 1215 return (PCIE_LNK_WIDTH_UNKNOWN); 1216 } 1217 1218 static inline int 1219 pcie_get_mps(struct pci_dev *dev) 1220 { 1221 return (pci_get_max_payload(dev->dev.bsddev)); 1222 } 1223 1224 static inline uint32_t 1225 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1226 { 1227 1228 switch(spd) { 1229 case PCIE_SPEED_16_0GT: 1230 return (16000 * 128 / 130); 1231 case PCIE_SPEED_8_0GT: 1232 return (8000 * 128 / 130); 1233 case PCIE_SPEED_5_0GT: 1234 return (5000 * 8 / 10); 1235 case PCIE_SPEED_2_5GT: 1236 return (2500 * 8 / 10); 1237 default: 1238 return (0); 1239 } 1240 } 1241 1242 static inline uint32_t 1243 pcie_bandwidth_available(struct pci_dev *pdev, 1244 struct pci_dev **limiting, 1245 enum pci_bus_speed *speed, 1246 enum pcie_link_width *width) 1247 { 1248 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1249 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1250 1251 if (speed) 1252 *speed = nspeed; 1253 if (width) 1254 *width = nwidth; 1255 1256 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1257 } 1258 1259 static inline struct pci_dev * 1260 pcie_find_root_port(struct pci_dev *pdev) 1261 { 1262 device_t root; 1263 1264 if (pdev->root != NULL) 1265 return (pdev->root); 1266 1267 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1268 if (root == NULL) 1269 return (NULL); 1270 1271 pdev->root = lkpinew_pci_dev(root); 1272 return (pdev->root); 1273 } 1274 1275 /* This is needed when people rip out the device "HotPlug". */ 1276 static inline void 1277 pci_lock_rescan_remove(void) 1278 { 1279 } 1280 1281 static inline void 1282 pci_unlock_rescan_remove(void) 1283 { 1284 } 1285 1286 static __inline void 1287 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1288 { 1289 } 1290 1291 /* 1292 * The following functions can be used to attach/detach the LinuxKPI's 1293 * PCI device runtime. The pci_driver and pci_device_id pointer is 1294 * allowed to be NULL. Other pointers must be all valid. 1295 * The pci_dev structure should be zero-initialized before passed 1296 * to the linux_pci_attach_device function. 1297 */ 1298 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1299 const struct pci_device_id *, struct pci_dev *); 1300 extern int linux_pci_detach_device(struct pci_dev *); 1301 1302 static inline int 1303 pci_dev_present(const struct pci_device_id *cur) 1304 { 1305 while (cur != NULL && (cur->vendor || cur->device)) { 1306 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1307 return (1); 1308 } 1309 cur++; 1310 } 1311 return (0); 1312 } 1313 1314 static inline bool 1315 pci_is_root_bus(struct pci_bus *pbus) 1316 { 1317 1318 return (pbus->self == NULL); 1319 } 1320 1321 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1322 unsigned int bus, unsigned int devfn); 1323 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1324 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1325 1326 static inline int 1327 pci_domain_nr(struct pci_bus *pbus) 1328 { 1329 1330 return (pbus->domain); 1331 } 1332 1333 static inline int 1334 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1335 int pos, uint32_t *val, int len) 1336 { 1337 1338 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1339 return (0); 1340 } 1341 1342 static inline int 1343 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1344 { 1345 uint32_t tmp; 1346 int ret; 1347 1348 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1349 *val = (u16)tmp; 1350 return (ret); 1351 } 1352 1353 static inline int 1354 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1355 { 1356 uint32_t tmp; 1357 int ret; 1358 1359 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1360 *val = (u8)tmp; 1361 return (ret); 1362 } 1363 1364 static inline int 1365 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1366 uint32_t val, int size) 1367 { 1368 1369 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1370 return (0); 1371 } 1372 1373 static inline int 1374 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1375 uint8_t val) 1376 { 1377 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1378 } 1379 1380 static inline int 1381 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1382 uint16_t val) 1383 { 1384 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1385 } 1386 1387 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1388 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1389 1390 /* -------------------------------------------------------------------------- */ 1391 1392 static inline int 1393 pcim_enable_device(struct pci_dev *pdev) 1394 { 1395 struct pci_devres *dr; 1396 int error; 1397 1398 /* Here we cannot run through the pdev->managed check. */ 1399 dr = lkpi_pci_devres_get_alloc(pdev); 1400 if (dr == NULL) 1401 return (-ENOMEM); 1402 1403 /* If resources were enabled before do not do it again. */ 1404 if (dr->enable_io) 1405 return (0); 1406 1407 error = pci_enable_device(pdev); 1408 if (error == 0) 1409 dr->enable_io = true; 1410 1411 /* This device is not managed. */ 1412 pdev->managed = true; 1413 1414 return (error); 1415 } 1416 1417 static inline struct pcim_iomap_devres * 1418 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev) 1419 { 1420 struct pcim_iomap_devres *dr; 1421 1422 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release, 1423 NULL, NULL); 1424 if (dr == NULL) { 1425 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release, 1426 sizeof(*dr), GFP_KERNEL | __GFP_ZERO); 1427 if (dr != NULL) 1428 lkpi_devres_add(&pdev->dev, dr); 1429 } 1430 1431 if (dr == NULL) 1432 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__); 1433 1434 return (dr); 1435 } 1436 1437 static inline void __iomem ** 1438 pcim_iomap_table(struct pci_dev *pdev) 1439 { 1440 struct pcim_iomap_devres *dr; 1441 1442 dr = lkpi_pcim_iomap_devres_find(pdev); 1443 if (dr == NULL) 1444 return (NULL); 1445 1446 /* 1447 * If the driver has manually set a flag to be able to request the 1448 * resource to use bus_read/write_<n>, return the shadow table. 1449 */ 1450 if (pdev->want_iomap_res) 1451 return ((void **)dr->res_table); 1452 1453 /* This is the Linux default. */ 1454 return (dr->mmio_table); 1455 } 1456 1457 static inline int 1458 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1459 { 1460 struct pcim_iomap_devres *dr; 1461 void *res; 1462 uint32_t mappings, requests, req_mask; 1463 int bar, error; 1464 1465 dr = lkpi_pcim_iomap_devres_find(pdev); 1466 if (dr == NULL) 1467 return (-ENOMEM); 1468 1469 /* Request all the BARs ("regions") we do not iomap. */ 1470 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1471 for (bar = requests = 0; requests != req_mask; bar++) { 1472 if ((req_mask & (1 << bar)) == 0) 1473 continue; 1474 error = pci_request_region(pdev, bar, name); 1475 if (error != 0 && error != -ENODEV) 1476 goto err; 1477 requests |= (1 << bar); 1478 } 1479 1480 /* Now iomap all the requested (by "mask") ones. */ 1481 for (bar = mappings = 0; mappings != mask; bar++) { 1482 if ((mask & (1 << bar)) == 0) 1483 continue; 1484 1485 /* Request double is not allowed. */ 1486 if (dr->mmio_table[bar] != NULL) { 1487 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1488 __func__, bar, dr->mmio_table[bar]); 1489 goto err; 1490 } 1491 1492 res = _lkpi_pci_iomap(pdev, bar, 0); 1493 if (res == NULL) 1494 goto err; 1495 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1496 dr->res_table[bar] = res; 1497 1498 mappings |= (1 << bar); 1499 } 1500 1501 return (0); 1502 1503 err: 1504 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1505 if ((mappings & (1 << bar)) != 0) { 1506 res = dr->mmio_table[bar]; 1507 if (res == NULL) 1508 continue; 1509 pci_iounmap(pdev, res); 1510 } else if ((requests & (1 << bar)) != 0) { 1511 pci_release_region(pdev, bar); 1512 } 1513 } 1514 1515 return (-EINVAL); 1516 } 1517 1518 /* This is a FreeBSD extension so we can use bus_*(). */ 1519 static inline void 1520 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1521 { 1522 pdev->want_iomap_res = true; 1523 } 1524 1525 #endif /* _LINUX_PCI_H_ */ 1526