1 /*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * Copyright (c) 2020-2021 The FreeBSD Foundation 8 * 9 * Portions of this software were developed by Björn Zeeb 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice unmodified, this list of conditions, and the following 17 * disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 #ifndef _LINUX_PCI_H_ 36 #define _LINUX_PCI_H_ 37 38 #define CONFIG_PCI_MSI 39 40 #include <linux/types.h> 41 42 #include <sys/param.h> 43 #include <sys/bus.h> 44 #include <sys/nv.h> 45 #include <sys/pciio.h> 46 #include <sys/rman.h> 47 #include <sys/bus.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pci_private.h> 51 52 #include <machine/resource.h> 53 54 #include <linux/list.h> 55 #include <linux/dmapool.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/compiler.h> 58 #include <linux/errno.h> 59 #include <asm/atomic.h> 60 #include <linux/device.h> 61 #include <linux/pci_ids.h> 62 63 struct pci_device_id { 64 uint32_t vendor; 65 uint32_t device; 66 uint32_t subvendor; 67 uint32_t subdevice; 68 uint32_t class; 69 uint32_t class_mask; 70 uintptr_t driver_data; 71 }; 72 73 #define MODULE_DEVICE_TABLE(bus, table) 74 75 #define PCI_ANY_ID -1U 76 77 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 78 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 79 #define PCI_FUNC(devfn) ((devfn) & 0x07) 80 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 81 82 #define PCI_VDEVICE(_vendor, _device) \ 83 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 84 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 85 #define PCI_DEVICE(_vendor, _device) \ 86 .vendor = (_vendor), .device = (_device), \ 87 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 88 89 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 90 91 #define PCI_VENDOR_ID PCIR_DEVVENDOR 92 #define PCI_COMMAND PCIR_COMMAND 93 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS 94 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 95 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 96 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S 97 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1 98 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */ 99 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 100 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 101 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 102 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 103 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 104 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 105 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 106 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 107 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 108 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 109 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 110 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 111 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 112 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE 113 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 114 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 115 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 116 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 117 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 118 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 119 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 120 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 121 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 122 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 123 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 124 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 125 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 126 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 127 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 128 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 129 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 130 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 131 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 132 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 133 #define PCI_EXP_LNKCTL2_TLS 0x000f 134 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ 135 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ 136 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 137 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 138 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 139 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 140 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 141 142 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 143 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 144 #define PCI_EXP_DEVSTA_TRPND 0x0020 145 146 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 147 #define IORESOURCE_IO (1 << SYS_RES_IOPORT) 148 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 149 150 enum pci_bus_speed { 151 PCI_SPEED_UNKNOWN = -1, 152 PCIE_SPEED_2_5GT, 153 PCIE_SPEED_5_0GT, 154 PCIE_SPEED_8_0GT, 155 PCIE_SPEED_16_0GT, 156 }; 157 158 enum pcie_link_width { 159 PCIE_LNK_WIDTH_RESRV = 0x00, 160 PCIE_LNK_X1 = 0x01, 161 PCIE_LNK_X2 = 0x02, 162 PCIE_LNK_X4 = 0x04, 163 PCIE_LNK_X8 = 0x08, 164 PCIE_LNK_X12 = 0x0c, 165 PCIE_LNK_X16 = 0x10, 166 PCIE_LNK_X32 = 0x20, 167 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 168 }; 169 170 #define PCIE_LINK_STATE_L0S 0x00000001 171 #define PCIE_LINK_STATE_L1 0x00000002 172 #define PCIE_LINK_STATE_CLKPM 0x00000004 173 174 typedef int pci_power_t; 175 176 #define PCI_D0 PCI_POWERSTATE_D0 177 #define PCI_D1 PCI_POWERSTATE_D1 178 #define PCI_D2 PCI_POWERSTATE_D2 179 #define PCI_D3hot PCI_POWERSTATE_D3 180 #define PCI_D3cold 4 181 182 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 183 184 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD 185 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID 186 187 #define PCI_EXT_CAP_ID_ERR PCIZ_AER 188 189 struct pci_dev; 190 191 struct pci_driver { 192 struct list_head links; 193 char *name; 194 const struct pci_device_id *id_table; 195 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 196 void (*remove)(struct pci_dev *dev); 197 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 198 int (*resume) (struct pci_dev *dev); /* Device woken up */ 199 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 200 driver_t bsddriver; 201 devclass_t bsdclass; 202 struct device_driver driver; 203 const struct pci_error_handlers *err_handler; 204 bool isdrm; 205 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 206 const nvlist_t *pf_config); 207 void (*bsd_iov_uninit)(device_t dev); 208 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 209 const nvlist_t *vf_config); 210 }; 211 212 struct pci_bus { 213 struct pci_dev *self; 214 int domain; 215 int number; 216 }; 217 218 extern struct list_head pci_drivers; 219 extern struct list_head pci_devices; 220 extern spinlock_t pci_lock; 221 222 #define __devexit_p(x) x 223 224 /* 225 * If we find drivers accessing this from multiple KPIs we may have to 226 * refcount objects of this structure. 227 */ 228 struct pci_mmio_region { 229 TAILQ_ENTRY(pci_mmio_region) next; 230 struct resource *res; 231 int rid; 232 int type; 233 }; 234 235 struct pci_dev { 236 struct device dev; 237 struct list_head links; 238 struct pci_driver *pdrv; 239 struct pci_bus *bus; 240 uint16_t device; 241 uint16_t vendor; 242 uint16_t subsystem_vendor; 243 uint16_t subsystem_device; 244 unsigned int irq; 245 unsigned int devfn; 246 uint32_t class; 247 uint8_t revision; 248 bool msi_enabled; 249 250 TAILQ_HEAD(, pci_mmio_region) mmio; 251 252 /* Add all new items at the end of the list in 13 */ 253 struct pci_dev *root; 254 phys_addr_t rom; 255 size_t romlen; 256 bool managed; /* devres "pcim_*(). */ 257 bool want_iomap_res; 258 bool msix_enabled; 259 }; 260 261 /* XXX add kassert here on the mmio offset */ 262 263 /* We need some meta-struct to keep track of these for devres. */ 264 struct pci_devres { 265 bool enable_io; 266 /* PCIR_MAX_BAR_0 + 1 = 6 => BIT(0..5). */ 267 uint8_t region_mask; 268 struct resource *region_table[PCIR_MAX_BAR_0 + 1]; /* Not needed. */ 269 }; 270 struct pcim_iomap_devres { 271 void *mmio_table[PCIR_MAX_BAR_0 + 1]; 272 struct resource *res_table[PCIR_MAX_BAR_0 + 1]; 273 }; 274 275 /* Internal helper function(s). */ 276 struct pci_dev *lkpinew_pci_dev(device_t); 277 void lkpi_pci_devres_release(struct device *, void *); 278 void lkpi_pcim_iomap_table_release(struct device *, void *); 279 280 static inline int 281 pci_resource_type(struct pci_dev *pdev, int bar) 282 { 283 struct pci_map *pm; 284 285 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 286 if (!pm) 287 return (-1); 288 289 if (PCI_BAR_IO(pm->pm_value)) 290 return (SYS_RES_IOPORT); 291 else 292 return (SYS_RES_MEMORY); 293 } 294 295 struct resource_list_entry *linux_pci_reserve_bar(struct pci_dev *pdev, 296 struct resource_list *rl, int type, int rid); 297 298 static inline struct resource_list_entry * 299 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid, bool reserve_bar) 300 { 301 struct pci_devinfo *dinfo; 302 struct resource_list *rl; 303 struct resource_list_entry *rle; 304 305 dinfo = device_get_ivars(pdev->dev.bsddev); 306 rl = &dinfo->resources; 307 rle = resource_list_find(rl, type, rid); 308 /* Reserve resources for this BAR if needed. */ 309 if (rle == NULL && reserve_bar) 310 rle = linux_pci_reserve_bar(pdev, rl, type, rid); 311 return (rle); 312 } 313 314 static inline struct resource_list_entry * 315 linux_pci_get_bar(struct pci_dev *pdev, int bar, bool reserve) 316 { 317 int type; 318 319 type = pci_resource_type(pdev, bar); 320 if (type < 0) 321 return (NULL); 322 bar = PCIR_BAR(bar); 323 return (linux_pci_get_rle(pdev, type, bar, reserve)); 324 } 325 326 static inline struct device * 327 linux_pci_find_irq_dev(unsigned int irq) 328 { 329 struct pci_dev *pdev; 330 struct device *found; 331 332 found = NULL; 333 spin_lock(&pci_lock); 334 list_for_each_entry(pdev, &pci_devices, links) { 335 if (irq == pdev->dev.irq || 336 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 337 found = &pdev->dev; 338 break; 339 } 340 } 341 spin_unlock(&pci_lock); 342 return (found); 343 } 344 345 /* 346 * All drivers just seem to want to inspect the type not flags. 347 */ 348 static inline int 349 pci_resource_flags(struct pci_dev *pdev, int bar) 350 { 351 int type; 352 353 type = pci_resource_type(pdev, bar); 354 if (type < 0) 355 return (0); 356 return (1 << type); 357 } 358 359 static inline const char * 360 pci_name(struct pci_dev *d) 361 { 362 363 return device_get_desc(d->dev.bsddev); 364 } 365 366 static inline void * 367 pci_get_drvdata(struct pci_dev *pdev) 368 { 369 370 return dev_get_drvdata(&pdev->dev); 371 } 372 373 static inline void 374 pci_set_drvdata(struct pci_dev *pdev, void *data) 375 { 376 377 dev_set_drvdata(&pdev->dev, data); 378 } 379 380 static inline struct pci_dev * 381 pci_dev_get(struct pci_dev *pdev) 382 { 383 384 if (pdev != NULL) 385 get_device(&pdev->dev); 386 return (pdev); 387 } 388 389 static __inline void 390 pci_dev_put(struct pci_dev *pdev) 391 { 392 393 if (pdev != NULL) 394 put_device(&pdev->dev); 395 } 396 397 static inline int 398 pci_enable_device(struct pci_dev *pdev) 399 { 400 401 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 402 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 403 return (0); 404 } 405 406 static inline void 407 pci_disable_device(struct pci_dev *pdev) 408 { 409 410 pci_disable_busmaster(pdev->dev.bsddev); 411 } 412 413 static inline int 414 pci_set_master(struct pci_dev *pdev) 415 { 416 417 pci_enable_busmaster(pdev->dev.bsddev); 418 return (0); 419 } 420 421 static inline int 422 pci_set_power_state(struct pci_dev *pdev, int state) 423 { 424 425 pci_set_powerstate(pdev->dev.bsddev, state); 426 return (0); 427 } 428 429 static inline int 430 pci_clear_master(struct pci_dev *pdev) 431 { 432 433 pci_disable_busmaster(pdev->dev.bsddev); 434 return (0); 435 } 436 437 static inline struct pci_devres * 438 lkpi_pci_devres_get_alloc(struct pci_dev *pdev) 439 { 440 struct pci_devres *dr; 441 442 dr = lkpi_devres_find(&pdev->dev, lkpi_pci_devres_release, NULL, NULL); 443 if (dr == NULL) { 444 dr = lkpi_devres_alloc(lkpi_pci_devres_release, sizeof(*dr), 445 GFP_KERNEL | __GFP_ZERO); 446 if (dr != NULL) 447 lkpi_devres_add(&pdev->dev, dr); 448 } 449 450 return (dr); 451 } 452 static inline struct pci_devres * 453 lkpi_pci_devres_find(struct pci_dev *pdev) 454 { 455 456 if (!pdev->managed) 457 return (NULL); 458 459 return (lkpi_pci_devres_get_alloc(pdev)); 460 } 461 462 static inline int 463 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 464 { 465 struct resource *res; 466 struct pci_devres *dr; 467 struct pci_mmio_region *mmio; 468 int rid; 469 int type; 470 471 type = pci_resource_type(pdev, bar); 472 if (type < 0) 473 return (-ENODEV); 474 rid = PCIR_BAR(bar); 475 res = bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 476 RF_ACTIVE|RF_SHAREABLE); 477 if (res == NULL) { 478 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 479 "bar %d type %d rid %d\n", 480 __func__, bar, type, PCIR_BAR(bar)); 481 return (-ENODEV); 482 } 483 484 /* 485 * It seems there is an implicit devres tracking on these if the device 486 * is managed; otherwise the resources are not automatiaclly freed on 487 * FreeBSD/LinuxKPI tough they should be/are expected to be by Linux 488 * drivers. 489 */ 490 dr = lkpi_pci_devres_find(pdev); 491 if (dr != NULL) { 492 dr->region_mask |= (1 << bar); 493 dr->region_table[bar] = res; 494 } 495 496 /* Even if the device is not managed we need to track it for iomap. */ 497 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 498 mmio->rid = PCIR_BAR(bar); 499 mmio->type = type; 500 mmio->res = res; 501 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 502 503 return (0); 504 } 505 506 static inline void 507 pci_release_region(struct pci_dev *pdev, int bar) 508 { 509 struct resource_list_entry *rle; 510 struct pci_devres *dr; 511 struct pci_mmio_region *mmio, *p; 512 513 if ((rle = linux_pci_get_bar(pdev, bar, false)) == NULL) 514 return; 515 516 /* 517 * As we implicitly track the requests we also need to clear them on 518 * release. Do clear before resource release. 519 */ 520 dr = lkpi_pci_devres_find(pdev); 521 if (dr != NULL) { 522 KASSERT(dr->region_table[bar] == rle->res, ("%s: pdev %p bar %d" 523 " region_table res %p != rel->res %p\n", __func__, pdev, 524 bar, dr->region_table[bar], rle->res)); 525 dr->region_table[bar] = NULL; 526 dr->region_mask &= ~(1 << bar); 527 } 528 529 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 530 if (rle->res != (void *)rman_get_bushandle(mmio->res)) 531 continue; 532 TAILQ_REMOVE(&pdev->mmio, mmio, next); 533 free(mmio, M_DEVBUF); 534 } 535 536 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 537 } 538 539 static inline void 540 pci_release_regions(struct pci_dev *pdev) 541 { 542 int i; 543 544 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 545 pci_release_region(pdev, i); 546 } 547 548 static inline int 549 pci_request_regions(struct pci_dev *pdev, const char *res_name) 550 { 551 int error; 552 int i; 553 554 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 555 error = pci_request_region(pdev, i, res_name); 556 if (error && error != -ENODEV) { 557 pci_release_regions(pdev); 558 return (error); 559 } 560 } 561 return (0); 562 } 563 564 static inline void 565 lkpi_pci_disable_msix(struct pci_dev *pdev) 566 { 567 568 pci_release_msi(pdev->dev.bsddev); 569 570 /* 571 * The MSIX IRQ numbers associated with this PCI device are no 572 * longer valid and might be re-assigned. Make sure 573 * linux_pci_find_irq_dev() does no longer see them by 574 * resetting their references to zero: 575 */ 576 pdev->dev.irq_start = 0; 577 pdev->dev.irq_end = 0; 578 pdev->msix_enabled = false; 579 } 580 /* Only for consistency. No conflict on that one. */ 581 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev) 582 583 static inline void 584 lkpi_pci_disable_msi(struct pci_dev *pdev) 585 { 586 587 pci_release_msi(pdev->dev.bsddev); 588 589 pdev->dev.irq_start = 0; 590 pdev->dev.irq_end = 0; 591 pdev->irq = pdev->dev.irq; 592 pdev->msi_enabled = false; 593 } 594 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev) 595 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev) 596 597 unsigned long pci_resource_start(struct pci_dev *pdev, int bar); 598 unsigned long pci_resource_len(struct pci_dev *pdev, int bar); 599 600 static inline bus_addr_t 601 pci_bus_address(struct pci_dev *pdev, int bar) 602 { 603 604 return (pci_resource_start(pdev, bar)); 605 } 606 607 #define PCI_CAP_ID_EXP PCIY_EXPRESS 608 #define PCI_CAP_ID_PCIX PCIY_PCIX 609 #define PCI_CAP_ID_AGP PCIY_AGP 610 #define PCI_CAP_ID_PM PCIY_PMG 611 612 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 613 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 614 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 615 #define PCI_EXP_LNKCTL PCIER_LINK_CTL 616 #define PCI_EXP_LNKSTA PCIER_LINK_STA 617 618 static inline int 619 pci_find_capability(struct pci_dev *pdev, int capid) 620 { 621 int reg; 622 623 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 624 return (0); 625 return (reg); 626 } 627 628 static inline int pci_pcie_cap(struct pci_dev *dev) 629 { 630 return pci_find_capability(dev, PCI_CAP_ID_EXP); 631 } 632 633 static inline int 634 pci_find_ext_capability(struct pci_dev *pdev, int capid) 635 { 636 int reg; 637 638 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 639 return (0); 640 return (reg); 641 } 642 643 #define PCIM_PCAP_PME_SHIFT 11 644 static __inline bool 645 pci_pme_capable(struct pci_dev *pdev, uint32_t flag) 646 { 647 struct pci_devinfo *dinfo; 648 pcicfgregs *cfg; 649 650 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT)) 651 return (false); 652 653 dinfo = device_get_ivars(pdev->dev.bsddev); 654 cfg = &dinfo->cfg; 655 656 if (cfg->pp.pp_cap == 0) 657 return (false); 658 659 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0) 660 return (true); 661 662 return (false); 663 } 664 665 static inline int 666 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags) 667 { 668 669 if (!pci_enable_aspm) 670 return (-EPERM); 671 672 return (-ENXIO); 673 } 674 675 static inline int 676 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 677 { 678 679 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 680 return (0); 681 } 682 683 static inline int 684 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 685 { 686 687 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 688 return (0); 689 } 690 691 static inline int 692 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 693 { 694 695 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 696 return (0); 697 } 698 699 static inline int 700 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 701 { 702 703 pci_write_config(pdev->dev.bsddev, where, val, 1); 704 return (0); 705 } 706 707 static inline int 708 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 709 { 710 711 pci_write_config(pdev->dev.bsddev, where, val, 2); 712 return (0); 713 } 714 715 static inline int 716 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 717 { 718 719 pci_write_config(pdev->dev.bsddev, where, val, 4); 720 return (0); 721 } 722 723 int linux_pci_register_driver(struct pci_driver *pdrv); 724 int linux_pci_register_drm_driver(struct pci_driver *pdrv); 725 void linux_pci_unregister_driver(struct pci_driver *pdrv); 726 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv); 727 728 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 729 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 730 731 struct msix_entry { 732 int entry; 733 int vector; 734 }; 735 736 /* 737 * Enable msix, positive errors indicate actual number of available 738 * vectors. Negative errors are failures. 739 * 740 * NB: define added to prevent this definition of pci_enable_msix from 741 * clashing with the native FreeBSD version. 742 */ 743 #define pci_enable_msix(...) \ 744 linux_pci_enable_msix(__VA_ARGS__) 745 746 static inline int 747 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 748 { 749 struct resource_list_entry *rle; 750 int error; 751 int avail; 752 int i; 753 754 avail = pci_msix_count(pdev->dev.bsddev); 755 if (avail < nreq) { 756 if (avail == 0) 757 return -EINVAL; 758 return avail; 759 } 760 avail = nreq; 761 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 762 return error; 763 /* 764 * Handle case where "pci_alloc_msix()" may allocate less 765 * interrupts than available and return with no error: 766 */ 767 if (avail < nreq) { 768 pci_release_msi(pdev->dev.bsddev); 769 return avail; 770 } 771 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 772 pdev->dev.irq_start = rle->start; 773 pdev->dev.irq_end = rle->start + avail; 774 for (i = 0; i < nreq; i++) 775 entries[i].vector = pdev->dev.irq_start + i; 776 pdev->msix_enabled = true; 777 return (0); 778 } 779 780 #define pci_enable_msix_range(...) \ 781 linux_pci_enable_msix_range(__VA_ARGS__) 782 783 static inline int 784 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 785 int minvec, int maxvec) 786 { 787 int nvec = maxvec; 788 int rc; 789 790 if (maxvec < minvec) 791 return (-ERANGE); 792 793 do { 794 rc = pci_enable_msix(dev, entries, nvec); 795 if (rc < 0) { 796 return (rc); 797 } else if (rc > 0) { 798 if (rc < minvec) 799 return (-ENOSPC); 800 nvec = rc; 801 } 802 } while (rc); 803 return (nvec); 804 } 805 806 #define pci_enable_msi(pdev) \ 807 linux_pci_enable_msi(pdev) 808 809 static inline int 810 pci_enable_msi(struct pci_dev *pdev) 811 { 812 struct resource_list_entry *rle; 813 int error; 814 int avail; 815 816 avail = pci_msi_count(pdev->dev.bsddev); 817 if (avail < 1) 818 return -EINVAL; 819 820 avail = 1; /* this function only enable one MSI IRQ */ 821 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 822 return error; 823 824 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1, false); 825 pdev->dev.irq_start = rle->start; 826 pdev->dev.irq_end = rle->start + avail; 827 pdev->irq = rle->start; 828 pdev->msi_enabled = true; 829 return (0); 830 } 831 832 static inline int 833 pci_channel_offline(struct pci_dev *pdev) 834 { 835 836 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID); 837 } 838 839 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 840 { 841 return -ENODEV; 842 } 843 static inline void pci_disable_sriov(struct pci_dev *dev) 844 { 845 } 846 847 static inline struct resource * 848 _lkpi_pci_iomap(struct pci_dev *pdev, int bar, int mmio_size __unused) 849 { 850 struct pci_mmio_region *mmio, *p; 851 int type; 852 853 type = pci_resource_type(pdev, bar); 854 if (type < 0) { 855 device_printf(pdev->dev.bsddev, "%s: bar %d type %d\n", 856 __func__, bar, type); 857 return (NULL); 858 } 859 860 /* 861 * Check for duplicate mappings. 862 * This can happen if a driver calls pci_request_region() first. 863 */ 864 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 865 if (mmio->type == type && mmio->rid == PCIR_BAR(bar)) { 866 return (mmio->res); 867 } 868 } 869 870 mmio = malloc(sizeof(*mmio), M_DEVBUF, M_WAITOK | M_ZERO); 871 mmio->rid = PCIR_BAR(bar); 872 mmio->type = type; 873 mmio->res = bus_alloc_resource_any(pdev->dev.bsddev, mmio->type, 874 &mmio->rid, RF_ACTIVE|RF_SHAREABLE); 875 if (mmio->res == NULL) { 876 device_printf(pdev->dev.bsddev, "%s: failed to alloc " 877 "bar %d type %d rid %d\n", 878 __func__, bar, type, PCIR_BAR(bar)); 879 free(mmio, M_DEVBUF); 880 return (NULL); 881 } 882 TAILQ_INSERT_TAIL(&pdev->mmio, mmio, next); 883 884 return (mmio->res); 885 } 886 887 static inline void * 888 pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size) 889 { 890 struct resource *res; 891 892 res = _lkpi_pci_iomap(pdev, mmio_bar, mmio_size); 893 if (res == NULL) 894 return (NULL); 895 /* This is a FreeBSD extension so we can use bus_*(). */ 896 if (pdev->want_iomap_res) 897 return (res); 898 return ((void *)rman_get_bushandle(res)); 899 } 900 901 static inline void 902 pci_iounmap(struct pci_dev *pdev, void *res) 903 { 904 struct pci_mmio_region *mmio, *p; 905 906 TAILQ_FOREACH_SAFE(mmio, &pdev->mmio, next, p) { 907 if (res != (void *)rman_get_bushandle(mmio->res)) 908 continue; 909 bus_release_resource(pdev->dev.bsddev, 910 mmio->type, mmio->rid, mmio->res); 911 TAILQ_REMOVE(&pdev->mmio, mmio, next); 912 free(mmio, M_DEVBUF); 913 return; 914 } 915 } 916 917 static inline void 918 lkpi_pci_save_state(struct pci_dev *pdev) 919 { 920 921 pci_save_state(pdev->dev.bsddev); 922 } 923 924 static inline void 925 lkpi_pci_restore_state(struct pci_dev *pdev) 926 { 927 928 pci_restore_state(pdev->dev.bsddev); 929 } 930 931 #define pci_save_state(dev) lkpi_pci_save_state(dev) 932 #define pci_restore_state(dev) lkpi_pci_restore_state(dev) 933 934 #define DEFINE_PCI_DEVICE_TABLE(_table) \ 935 const struct pci_device_id _table[] __devinitdata 936 937 /* XXX This should not be necessary. */ 938 #define pcix_set_mmrbc(d, v) 0 939 #define pcix_get_max_mmrbc(d) 0 940 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v)) 941 942 #define PCI_DMA_BIDIRECTIONAL 0 943 #define PCI_DMA_TODEVICE 1 944 #define PCI_DMA_FROMDEVICE 2 945 #define PCI_DMA_NONE 3 946 947 #define pci_pool dma_pool 948 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 949 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 950 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 951 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 952 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 953 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 954 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 955 _size, _vaddr, _dma_handle) 956 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 957 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 958 _sg, _nents, (enum dma_data_direction)_dir) 959 #define pci_map_single(_hwdev, _ptr, _size, _dir) \ 960 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 961 (_ptr), (_size), (enum dma_data_direction)_dir) 962 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 963 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 964 _addr, _size, (enum dma_data_direction)_dir) 965 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 966 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 967 _sg, _nents, (enum dma_data_direction)_dir) 968 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 969 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 970 _offset, _size, (enum dma_data_direction)_dir) 971 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 972 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 973 _dma_address, _size, (enum dma_data_direction)_dir) 974 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 975 #define pci_dma_mapping_error(_pdev, _dma_addr) \ 976 dma_mapping_error(&(_pdev)->dev, _dma_addr) 977 #define pci_set_consistent_dma_mask(_pdev, _mask) \ 978 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 979 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 980 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 981 #define pci_unmap_addr dma_unmap_addr 982 #define pci_unmap_addr_set dma_unmap_addr_set 983 #define pci_unmap_len dma_unmap_len 984 #define pci_unmap_len_set dma_unmap_len_set 985 986 typedef unsigned int __bitwise pci_channel_state_t; 987 typedef unsigned int __bitwise pci_ers_result_t; 988 989 enum pci_channel_state { 990 pci_channel_io_normal = 1, 991 pci_channel_io_frozen = 2, 992 pci_channel_io_perm_failure = 3, 993 }; 994 995 enum pci_ers_result { 996 PCI_ERS_RESULT_NONE = 1, 997 PCI_ERS_RESULT_CAN_RECOVER = 2, 998 PCI_ERS_RESULT_NEED_RESET = 3, 999 PCI_ERS_RESULT_DISCONNECT = 4, 1000 PCI_ERS_RESULT_RECOVERED = 5, 1001 }; 1002 1003 /* PCI bus error event callbacks */ 1004 struct pci_error_handlers { 1005 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 1006 enum pci_channel_state error); 1007 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 1008 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 1009 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 1010 void (*resume)(struct pci_dev *dev); 1011 }; 1012 1013 /* FreeBSD does not support SRIOV - yet */ 1014 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 1015 { 1016 return dev; 1017 } 1018 1019 static inline bool pci_is_pcie(struct pci_dev *dev) 1020 { 1021 return !!pci_pcie_cap(dev); 1022 } 1023 1024 static inline u16 pcie_flags_reg(struct pci_dev *dev) 1025 { 1026 int pos; 1027 u16 reg16; 1028 1029 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 1030 if (!pos) 1031 return 0; 1032 1033 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 1034 1035 return reg16; 1036 } 1037 1038 static inline int pci_pcie_type(struct pci_dev *dev) 1039 { 1040 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 1041 } 1042 1043 static inline int pcie_cap_version(struct pci_dev *dev) 1044 { 1045 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 1046 } 1047 1048 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 1049 { 1050 int type = pci_pcie_type(dev); 1051 1052 return pcie_cap_version(dev) > 1 || 1053 type == PCI_EXP_TYPE_ROOT_PORT || 1054 type == PCI_EXP_TYPE_ENDPOINT || 1055 type == PCI_EXP_TYPE_LEG_END; 1056 } 1057 1058 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 1059 { 1060 return true; 1061 } 1062 1063 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 1064 { 1065 int type = pci_pcie_type(dev); 1066 1067 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1068 (type == PCI_EXP_TYPE_DOWNSTREAM && 1069 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 1070 } 1071 1072 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 1073 { 1074 int type = pci_pcie_type(dev); 1075 1076 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 1077 type == PCI_EXP_TYPE_RC_EC; 1078 } 1079 1080 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 1081 { 1082 if (!pci_is_pcie(dev)) 1083 return false; 1084 1085 switch (pos) { 1086 case PCI_EXP_FLAGS_TYPE: 1087 return true; 1088 case PCI_EXP_DEVCAP: 1089 case PCI_EXP_DEVCTL: 1090 case PCI_EXP_DEVSTA: 1091 return pcie_cap_has_devctl(dev); 1092 case PCI_EXP_LNKCAP: 1093 case PCI_EXP_LNKCTL: 1094 case PCI_EXP_LNKSTA: 1095 return pcie_cap_has_lnkctl(dev); 1096 case PCI_EXP_SLTCAP: 1097 case PCI_EXP_SLTCTL: 1098 case PCI_EXP_SLTSTA: 1099 return pcie_cap_has_sltctl(dev); 1100 case PCI_EXP_RTCTL: 1101 case PCI_EXP_RTCAP: 1102 case PCI_EXP_RTSTA: 1103 return pcie_cap_has_rtctl(dev); 1104 case PCI_EXP_DEVCAP2: 1105 case PCI_EXP_DEVCTL2: 1106 case PCI_EXP_LNKCAP2: 1107 case PCI_EXP_LNKCTL2: 1108 case PCI_EXP_LNKSTA2: 1109 return pcie_cap_version(dev) > 1; 1110 default: 1111 return false; 1112 } 1113 } 1114 1115 static inline int 1116 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 1117 { 1118 if (pos & 3) 1119 return -EINVAL; 1120 1121 if (!pcie_capability_reg_implemented(dev, pos)) 1122 return -EINVAL; 1123 1124 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 1125 } 1126 1127 static inline int 1128 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 1129 { 1130 if (pos & 3) 1131 return -EINVAL; 1132 1133 if (!pcie_capability_reg_implemented(dev, pos)) 1134 return -EINVAL; 1135 1136 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 1137 } 1138 1139 static inline int 1140 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 1141 { 1142 if (pos & 1) 1143 return -EINVAL; 1144 1145 if (!pcie_capability_reg_implemented(dev, pos)) 1146 return 0; 1147 1148 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 1149 } 1150 1151 static inline int pcie_get_minimum_link(struct pci_dev *dev, 1152 enum pci_bus_speed *speed, enum pcie_link_width *width) 1153 { 1154 *speed = PCI_SPEED_UNKNOWN; 1155 *width = PCIE_LNK_WIDTH_UNKNOWN; 1156 return (0); 1157 } 1158 1159 static inline int 1160 pci_num_vf(struct pci_dev *dev) 1161 { 1162 return (0); 1163 } 1164 1165 static inline enum pci_bus_speed 1166 pcie_get_speed_cap(struct pci_dev *dev) 1167 { 1168 device_t root; 1169 uint32_t lnkcap, lnkcap2; 1170 int error, pos; 1171 1172 root = device_get_parent(dev->dev.bsddev); 1173 if (root == NULL) 1174 return (PCI_SPEED_UNKNOWN); 1175 root = device_get_parent(root); 1176 if (root == NULL) 1177 return (PCI_SPEED_UNKNOWN); 1178 root = device_get_parent(root); 1179 if (root == NULL) 1180 return (PCI_SPEED_UNKNOWN); 1181 1182 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 1183 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 1184 return (PCI_SPEED_UNKNOWN); 1185 1186 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 1187 return (PCI_SPEED_UNKNOWN); 1188 1189 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 1190 1191 if (lnkcap2) { /* PCIe r3.0-compliant */ 1192 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 1193 return (PCIE_SPEED_2_5GT); 1194 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 1195 return (PCIE_SPEED_5_0GT); 1196 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 1197 return (PCIE_SPEED_8_0GT); 1198 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 1199 return (PCIE_SPEED_16_0GT); 1200 } else { /* pre-r3.0 */ 1201 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 1202 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 1203 return (PCIE_SPEED_2_5GT); 1204 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 1205 return (PCIE_SPEED_5_0GT); 1206 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 1207 return (PCIE_SPEED_8_0GT); 1208 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 1209 return (PCIE_SPEED_16_0GT); 1210 } 1211 return (PCI_SPEED_UNKNOWN); 1212 } 1213 1214 static inline enum pcie_link_width 1215 pcie_get_width_cap(struct pci_dev *dev) 1216 { 1217 uint32_t lnkcap; 1218 1219 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 1220 if (lnkcap) 1221 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 1222 1223 return (PCIE_LNK_WIDTH_UNKNOWN); 1224 } 1225 1226 static inline int 1227 pcie_get_mps(struct pci_dev *dev) 1228 { 1229 return (pci_get_max_payload(dev->dev.bsddev)); 1230 } 1231 1232 static inline uint32_t 1233 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 1234 { 1235 1236 switch(spd) { 1237 case PCIE_SPEED_16_0GT: 1238 return (16000 * 128 / 130); 1239 case PCIE_SPEED_8_0GT: 1240 return (8000 * 128 / 130); 1241 case PCIE_SPEED_5_0GT: 1242 return (5000 * 8 / 10); 1243 case PCIE_SPEED_2_5GT: 1244 return (2500 * 8 / 10); 1245 default: 1246 return (0); 1247 } 1248 } 1249 1250 static inline uint32_t 1251 pcie_bandwidth_available(struct pci_dev *pdev, 1252 struct pci_dev **limiting, 1253 enum pci_bus_speed *speed, 1254 enum pcie_link_width *width) 1255 { 1256 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1257 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1258 1259 if (speed) 1260 *speed = nspeed; 1261 if (width) 1262 *width = nwidth; 1263 1264 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1265 } 1266 1267 static inline struct pci_dev * 1268 pcie_find_root_port(struct pci_dev *pdev) 1269 { 1270 device_t root; 1271 1272 if (pdev->root != NULL) 1273 return (pdev->root); 1274 1275 root = pci_find_pcie_root_port(pdev->dev.bsddev); 1276 if (root == NULL) 1277 return (NULL); 1278 1279 pdev->root = lkpinew_pci_dev(root); 1280 return (pdev->root); 1281 } 1282 1283 /* This is needed when people rip out the device "HotPlug". */ 1284 static inline void 1285 pci_lock_rescan_remove(void) 1286 { 1287 } 1288 1289 static inline void 1290 pci_unlock_rescan_remove(void) 1291 { 1292 } 1293 1294 static __inline void 1295 pci_stop_and_remove_bus_device(struct pci_dev *pdev) 1296 { 1297 } 1298 1299 /* 1300 * The following functions can be used to attach/detach the LinuxKPI's 1301 * PCI device runtime. The pci_driver and pci_device_id pointer is 1302 * allowed to be NULL. Other pointers must be all valid. 1303 * The pci_dev structure should be zero-initialized before passed 1304 * to the linux_pci_attach_device function. 1305 */ 1306 extern int linux_pci_attach_device(device_t, struct pci_driver *, 1307 const struct pci_device_id *, struct pci_dev *); 1308 extern int linux_pci_detach_device(struct pci_dev *); 1309 1310 static inline int 1311 pci_dev_present(const struct pci_device_id *cur) 1312 { 1313 while (cur != NULL && (cur->vendor || cur->device)) { 1314 if (pci_find_device(cur->vendor, cur->device) != NULL) { 1315 return (1); 1316 } 1317 cur++; 1318 } 1319 return (0); 1320 } 1321 1322 static inline bool 1323 pci_is_root_bus(struct pci_bus *pbus) 1324 { 1325 1326 return (pbus->self == NULL); 1327 } 1328 1329 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain, 1330 unsigned int bus, unsigned int devfn); 1331 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \ 1332 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn) 1333 1334 static inline int 1335 pci_domain_nr(struct pci_bus *pbus) 1336 { 1337 1338 return (pbus->domain); 1339 } 1340 1341 static inline int 1342 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn, 1343 int pos, uint32_t *val, int len) 1344 { 1345 1346 *val = pci_read_config(bus->self->dev.bsddev, pos, len); 1347 return (0); 1348 } 1349 1350 static inline int 1351 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val) 1352 { 1353 uint32_t tmp; 1354 int ret; 1355 1356 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2); 1357 *val = (u16)tmp; 1358 return (ret); 1359 } 1360 1361 static inline int 1362 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val) 1363 { 1364 uint32_t tmp; 1365 int ret; 1366 1367 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1); 1368 *val = (u8)tmp; 1369 return (ret); 1370 } 1371 1372 static inline int 1373 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos, 1374 uint32_t val, int size) 1375 { 1376 1377 pci_write_config(bus->self->dev.bsddev, pos, val, size); 1378 return (0); 1379 } 1380 1381 static inline int 1382 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, 1383 uint8_t val) 1384 { 1385 return (pci_bus_write_config(bus, devfn, pos, val, 1)); 1386 } 1387 1388 static inline int 1389 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos, 1390 uint16_t val) 1391 { 1392 return (pci_bus_write_config(bus, devfn, pos, val, 2)); 1393 } 1394 1395 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from); 1396 #define pci_get_class(class, from) lkpi_pci_get_class(class, from) 1397 1398 /* -------------------------------------------------------------------------- */ 1399 1400 static inline int 1401 pcim_enable_device(struct pci_dev *pdev) 1402 { 1403 struct pci_devres *dr; 1404 int error; 1405 1406 /* Here we cannot run through the pdev->managed check. */ 1407 dr = lkpi_pci_devres_get_alloc(pdev); 1408 if (dr == NULL) 1409 return (-ENOMEM); 1410 1411 /* If resources were enabled before do not do it again. */ 1412 if (dr->enable_io) 1413 return (0); 1414 1415 error = pci_enable_device(pdev); 1416 if (error == 0) 1417 dr->enable_io = true; 1418 1419 /* This device is not managed. */ 1420 pdev->managed = true; 1421 1422 return (error); 1423 } 1424 1425 static inline struct pcim_iomap_devres * 1426 lkpi_pcim_iomap_devres_find(struct pci_dev *pdev) 1427 { 1428 struct pcim_iomap_devres *dr; 1429 1430 dr = lkpi_devres_find(&pdev->dev, lkpi_pcim_iomap_table_release, 1431 NULL, NULL); 1432 if (dr == NULL) { 1433 dr = lkpi_devres_alloc(lkpi_pcim_iomap_table_release, 1434 sizeof(*dr), GFP_KERNEL | __GFP_ZERO); 1435 if (dr != NULL) 1436 lkpi_devres_add(&pdev->dev, dr); 1437 } 1438 1439 if (dr == NULL) 1440 device_printf(pdev->dev.bsddev, "%s: NULL\n", __func__); 1441 1442 return (dr); 1443 } 1444 1445 static inline void __iomem ** 1446 pcim_iomap_table(struct pci_dev *pdev) 1447 { 1448 struct pcim_iomap_devres *dr; 1449 1450 dr = lkpi_pcim_iomap_devres_find(pdev); 1451 if (dr == NULL) 1452 return (NULL); 1453 1454 /* 1455 * If the driver has manually set a flag to be able to request the 1456 * resource to use bus_read/write_<n>, return the shadow table. 1457 */ 1458 if (pdev->want_iomap_res) 1459 return ((void **)dr->res_table); 1460 1461 /* This is the Linux default. */ 1462 return (dr->mmio_table); 1463 } 1464 1465 static inline int 1466 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name) 1467 { 1468 struct pcim_iomap_devres *dr; 1469 void *res; 1470 uint32_t mappings, requests, req_mask; 1471 int bar, error; 1472 1473 dr = lkpi_pcim_iomap_devres_find(pdev); 1474 if (dr == NULL) 1475 return (-ENOMEM); 1476 1477 /* Request all the BARs ("regions") we do not iomap. */ 1478 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask; 1479 for (bar = requests = 0; requests != req_mask; bar++) { 1480 if ((req_mask & (1 << bar)) == 0) 1481 continue; 1482 error = pci_request_region(pdev, bar, name); 1483 if (error != 0 && error != -ENODEV) 1484 goto err; 1485 requests |= (1 << bar); 1486 } 1487 1488 /* Now iomap all the requested (by "mask") ones. */ 1489 for (bar = mappings = 0; mappings != mask; bar++) { 1490 if ((mask & (1 << bar)) == 0) 1491 continue; 1492 1493 /* Request double is not allowed. */ 1494 if (dr->mmio_table[bar] != NULL) { 1495 device_printf(pdev->dev.bsddev, "%s: bar %d %p\n", 1496 __func__, bar, dr->mmio_table[bar]); 1497 goto err; 1498 } 1499 1500 res = _lkpi_pci_iomap(pdev, bar, 0); 1501 if (res == NULL) 1502 goto err; 1503 dr->mmio_table[bar] = (void *)rman_get_bushandle(res); 1504 dr->res_table[bar] = res; 1505 1506 mappings |= (1 << bar); 1507 } 1508 1509 return (0); 1510 1511 err: 1512 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) { 1513 if ((mappings & (1 << bar)) != 0) { 1514 res = dr->mmio_table[bar]; 1515 if (res == NULL) 1516 continue; 1517 pci_iounmap(pdev, res); 1518 } else if ((requests & (1 << bar)) != 0) { 1519 pci_release_region(pdev, bar); 1520 } 1521 } 1522 1523 return (-EINVAL); 1524 } 1525 1526 /* This is a FreeBSD extension so we can use bus_*(). */ 1527 static inline void 1528 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev) 1529 { 1530 pdev->want_iomap_res = true; 1531 } 1532 1533 #endif /* _LINUX_PCI_H_ */ 1534