1*0b57cec5SDimitry Andric //===--- WebAssemblyOptimizeLiveIntervals.cpp - LiveInterval processing ---===//
2*0b57cec5SDimitry Andric //
3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0b57cec5SDimitry Andric //
7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
8*0b57cec5SDimitry Andric ///
9*0b57cec5SDimitry Andric /// \file
10*0b57cec5SDimitry Andric /// Optimize LiveIntervals for use in a post-RA context.
11*0b57cec5SDimitry Andric //
12*0b57cec5SDimitry Andric /// LiveIntervals normally runs before register allocation when the code is
13*0b57cec5SDimitry Andric /// only recently lowered out of SSA form, so it's uncommon for registers to
14*0b57cec5SDimitry Andric /// have multiple defs, and when they do, the defs are usually closely related.
15*0b57cec5SDimitry Andric /// Later, after coalescing, tail duplication, and other optimizations, it's
16*0b57cec5SDimitry Andric /// more common to see registers with multiple unrelated defs. This pass
17*0b57cec5SDimitry Andric /// updates LiveIntervals to distribute the value numbers across separate
18*0b57cec5SDimitry Andric /// LiveIntervals.
19*0b57cec5SDimitry Andric ///
20*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
21*0b57cec5SDimitry Andric 
22*0b57cec5SDimitry Andric #include "WebAssembly.h"
23*0b57cec5SDimitry Andric #include "WebAssemblySubtarget.h"
24*0b57cec5SDimitry Andric #include "llvm/CodeGen/LiveIntervals.h"
25*0b57cec5SDimitry Andric #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
26*0b57cec5SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h"
27*0b57cec5SDimitry Andric #include "llvm/CodeGen/Passes.h"
28*0b57cec5SDimitry Andric #include "llvm/Support/Debug.h"
29*0b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h"
30*0b57cec5SDimitry Andric using namespace llvm;
31*0b57cec5SDimitry Andric 
32*0b57cec5SDimitry Andric #define DEBUG_TYPE "wasm-optimize-live-intervals"
33*0b57cec5SDimitry Andric 
34*0b57cec5SDimitry Andric namespace {
35*0b57cec5SDimitry Andric class WebAssemblyOptimizeLiveIntervals final : public MachineFunctionPass {
36*0b57cec5SDimitry Andric   StringRef getPassName() const override {
37*0b57cec5SDimitry Andric     return "WebAssembly Optimize Live Intervals";
38*0b57cec5SDimitry Andric   }
39*0b57cec5SDimitry Andric 
40*0b57cec5SDimitry Andric   void getAnalysisUsage(AnalysisUsage &AU) const override {
41*0b57cec5SDimitry Andric     AU.setPreservesCFG();
42*0b57cec5SDimitry Andric     AU.addRequired<LiveIntervals>();
43*0b57cec5SDimitry Andric     AU.addPreserved<MachineBlockFrequencyInfo>();
44*0b57cec5SDimitry Andric     AU.addPreserved<SlotIndexes>();
45*0b57cec5SDimitry Andric     AU.addPreserved<LiveIntervals>();
46*0b57cec5SDimitry Andric     AU.addPreservedID(LiveVariablesID);
47*0b57cec5SDimitry Andric     AU.addPreservedID(MachineDominatorsID);
48*0b57cec5SDimitry Andric     MachineFunctionPass::getAnalysisUsage(AU);
49*0b57cec5SDimitry Andric   }
50*0b57cec5SDimitry Andric 
51*0b57cec5SDimitry Andric   bool runOnMachineFunction(MachineFunction &MF) override;
52*0b57cec5SDimitry Andric 
53*0b57cec5SDimitry Andric public:
54*0b57cec5SDimitry Andric   static char ID; // Pass identification, replacement for typeid
55*0b57cec5SDimitry Andric   WebAssemblyOptimizeLiveIntervals() : MachineFunctionPass(ID) {}
56*0b57cec5SDimitry Andric };
57*0b57cec5SDimitry Andric } // end anonymous namespace
58*0b57cec5SDimitry Andric 
59*0b57cec5SDimitry Andric char WebAssemblyOptimizeLiveIntervals::ID = 0;
60*0b57cec5SDimitry Andric INITIALIZE_PASS(WebAssemblyOptimizeLiveIntervals, DEBUG_TYPE,
61*0b57cec5SDimitry Andric                 "Optimize LiveIntervals for WebAssembly", false, false)
62*0b57cec5SDimitry Andric 
63*0b57cec5SDimitry Andric FunctionPass *llvm::createWebAssemblyOptimizeLiveIntervals() {
64*0b57cec5SDimitry Andric   return new WebAssemblyOptimizeLiveIntervals();
65*0b57cec5SDimitry Andric }
66*0b57cec5SDimitry Andric 
67*0b57cec5SDimitry Andric bool WebAssemblyOptimizeLiveIntervals::runOnMachineFunction(
68*0b57cec5SDimitry Andric     MachineFunction &MF) {
69*0b57cec5SDimitry Andric   LLVM_DEBUG(dbgs() << "********** Optimize LiveIntervals **********\n"
70*0b57cec5SDimitry Andric                        "********** Function: "
71*0b57cec5SDimitry Andric                     << MF.getName() << '\n');
72*0b57cec5SDimitry Andric 
73*0b57cec5SDimitry Andric   MachineRegisterInfo &MRI = MF.getRegInfo();
74*0b57cec5SDimitry Andric   auto &LIS = getAnalysis<LiveIntervals>();
75*0b57cec5SDimitry Andric 
76*0b57cec5SDimitry Andric   // We don't preserve SSA form.
77*0b57cec5SDimitry Andric   MRI.leaveSSA();
78*0b57cec5SDimitry Andric 
79*0b57cec5SDimitry Andric   assert(MRI.tracksLiveness() && "OptimizeLiveIntervals expects liveness");
80*0b57cec5SDimitry Andric 
81*0b57cec5SDimitry Andric   // Split multiple-VN LiveIntervals into multiple LiveIntervals.
82*0b57cec5SDimitry Andric   SmallVector<LiveInterval *, 4> SplitLIs;
83*0b57cec5SDimitry Andric   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I < E; ++I) {
84*0b57cec5SDimitry Andric     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
85*0b57cec5SDimitry Andric     if (MRI.reg_nodbg_empty(Reg))
86*0b57cec5SDimitry Andric       continue;
87*0b57cec5SDimitry Andric 
88*0b57cec5SDimitry Andric     LIS.splitSeparateComponents(LIS.getInterval(Reg), SplitLIs);
89*0b57cec5SDimitry Andric     SplitLIs.clear();
90*0b57cec5SDimitry Andric   }
91*0b57cec5SDimitry Andric 
92*0b57cec5SDimitry Andric   // In PrepareForLiveIntervals, we conservatively inserted IMPLICIT_DEF
93*0b57cec5SDimitry Andric   // instructions to satisfy LiveIntervals' requirement that all uses be
94*0b57cec5SDimitry Andric   // dominated by defs. Now that LiveIntervals has computed which of these
95*0b57cec5SDimitry Andric   // defs are actually needed and which are dead, remove the dead ones.
96*0b57cec5SDimitry Andric   for (auto MII = MF.begin()->begin(), MIE = MF.begin()->end(); MII != MIE;) {
97*0b57cec5SDimitry Andric     MachineInstr *MI = &*MII++;
98*0b57cec5SDimitry Andric     if (MI->isImplicitDef() && MI->getOperand(0).isDead()) {
99*0b57cec5SDimitry Andric       LiveInterval &LI = LIS.getInterval(MI->getOperand(0).getReg());
100*0b57cec5SDimitry Andric       LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(*MI).getRegSlot());
101*0b57cec5SDimitry Andric       LIS.RemoveMachineInstrFromMaps(*MI);
102*0b57cec5SDimitry Andric       MI->eraseFromParent();
103*0b57cec5SDimitry Andric     }
104*0b57cec5SDimitry Andric   }
105*0b57cec5SDimitry Andric 
106*0b57cec5SDimitry Andric   return false;
107*0b57cec5SDimitry Andric }
108