1*af732203SDimitry Andric //===-- SIProgramInfo.cpp ----------------------------------------------===//
2*af732203SDimitry Andric //
3*af732203SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*af732203SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*af732203SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*af732203SDimitry Andric //
7*af732203SDimitry Andric //===----------------------------------------------------------------------===//
8*af732203SDimitry Andric //
9*af732203SDimitry Andric /// \file
10*af732203SDimitry Andric ///
11*af732203SDimitry Andric /// The SIProgramInfo tracks resource usage and hardware flags for kernels and
12*af732203SDimitry Andric /// entry functions.
13*af732203SDimitry Andric //
14*af732203SDimitry Andric //===----------------------------------------------------------------------===//
15*af732203SDimitry Andric //
16*af732203SDimitry Andric 
17*af732203SDimitry Andric #include "SIProgramInfo.h"
18*af732203SDimitry Andric #include "SIDefines.h"
19*af732203SDimitry Andric #include "Utils/AMDGPUBaseInfo.h"
20*af732203SDimitry Andric 
21*af732203SDimitry Andric using namespace llvm;
22*af732203SDimitry Andric 
getComputePGMRSrc1() const23*af732203SDimitry Andric uint64_t SIProgramInfo::getComputePGMRSrc1() const {
24*af732203SDimitry Andric   return S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) |
25*af732203SDimitry Andric          S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) |
26*af732203SDimitry Andric          S_00B848_PRIV(Priv) | S_00B848_DX10_CLAMP(DX10Clamp) |
27*af732203SDimitry Andric          S_00B848_DEBUG_MODE(DebugMode) | S_00B848_IEEE_MODE(IEEEMode) |
28*af732203SDimitry Andric          S_00B848_WGP_MODE(WgpMode) | S_00B848_MEM_ORDERED(MemOrdered);
29*af732203SDimitry Andric }
30*af732203SDimitry Andric 
getPGMRSrc1(CallingConv::ID CC) const31*af732203SDimitry Andric uint64_t SIProgramInfo::getPGMRSrc1(CallingConv::ID CC) const {
32*af732203SDimitry Andric   if (AMDGPU::isCompute(CC)) {
33*af732203SDimitry Andric     return getComputePGMRSrc1();
34*af732203SDimitry Andric   }
35*af732203SDimitry Andric   uint64_t Reg = S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) |
36*af732203SDimitry Andric                  S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) |
37*af732203SDimitry Andric                  S_00B848_PRIV(Priv) | S_00B848_DX10_CLAMP(DX10Clamp) |
38*af732203SDimitry Andric                  S_00B848_DEBUG_MODE(DebugMode) | S_00B848_IEEE_MODE(IEEEMode);
39*af732203SDimitry Andric   switch (CC) {
40*af732203SDimitry Andric   case CallingConv::AMDGPU_PS:
41*af732203SDimitry Andric     Reg |= S_00B028_MEM_ORDERED(MemOrdered);
42*af732203SDimitry Andric     break;
43*af732203SDimitry Andric   case CallingConv::AMDGPU_VS:
44*af732203SDimitry Andric     Reg |= S_00B128_MEM_ORDERED(MemOrdered);
45*af732203SDimitry Andric     break;
46*af732203SDimitry Andric   case CallingConv::AMDGPU_GS:
47*af732203SDimitry Andric     Reg |= S_00B228_WGP_MODE(WgpMode) | S_00B228_MEM_ORDERED(MemOrdered);
48*af732203SDimitry Andric     break;
49*af732203SDimitry Andric   case CallingConv::AMDGPU_HS:
50*af732203SDimitry Andric     Reg |= S_00B428_WGP_MODE(WgpMode) | S_00B428_MEM_ORDERED(MemOrdered);
51*af732203SDimitry Andric     break;
52*af732203SDimitry Andric   default:
53*af732203SDimitry Andric     break;
54*af732203SDimitry Andric   }
55*af732203SDimitry Andric   return Reg;
56*af732203SDimitry Andric }
57