1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the operating system Host concept. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Support/Host.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringMap.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/llvm-config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/X86TargetParser.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <assert.h> 27 #include <string.h> 28 29 // Include the platform-specific parts of this class. 30 #ifdef LLVM_ON_UNIX 31 #include "Unix/Host.inc" 32 #include <sched.h> 33 #endif 34 #ifdef _WIN32 35 #include "Windows/Host.inc" 36 #endif 37 #ifdef _MSC_VER 38 #include <intrin.h> 39 #endif 40 #if defined(__APPLE__) && (!defined(__x86_64__)) 41 #include <mach/host_info.h> 42 #include <mach/mach.h> 43 #include <mach/mach_host.h> 44 #include <mach/machine.h> 45 #endif 46 47 #define DEBUG_TYPE "host-detection" 48 49 //===----------------------------------------------------------------------===// 50 // 51 // Implementations of the CPU detection routines 52 // 53 //===----------------------------------------------------------------------===// 54 55 using namespace llvm; 56 57 static std::unique_ptr<llvm::MemoryBuffer> 58 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 59 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 60 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 61 if (std::error_code EC = Text.getError()) { 62 llvm::errs() << "Can't read " 63 << "/proc/cpuinfo: " << EC.message() << "\n"; 64 return nullptr; 65 } 66 return std::move(*Text); 67 } 68 69 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { 70 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 71 // and so we must use an operating-system interface to determine the current 72 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 73 const char *generic = "generic"; 74 75 // The cpu line is second (after the 'processor: 0' line), so if this 76 // buffer is too small then something has changed (or is wrong). 77 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 78 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 79 80 StringRef::const_iterator CIP = CPUInfoStart; 81 82 StringRef::const_iterator CPUStart = 0; 83 size_t CPULen = 0; 84 85 // We need to find the first line which starts with cpu, spaces, and a colon. 86 // After the colon, there may be some additional spaces and then the cpu type. 87 while (CIP < CPUInfoEnd && CPUStart == 0) { 88 if (CIP < CPUInfoEnd && *CIP == '\n') 89 ++CIP; 90 91 if (CIP < CPUInfoEnd && *CIP == 'c') { 92 ++CIP; 93 if (CIP < CPUInfoEnd && *CIP == 'p') { 94 ++CIP; 95 if (CIP < CPUInfoEnd && *CIP == 'u') { 96 ++CIP; 97 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 98 ++CIP; 99 100 if (CIP < CPUInfoEnd && *CIP == ':') { 101 ++CIP; 102 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 103 ++CIP; 104 105 if (CIP < CPUInfoEnd) { 106 CPUStart = CIP; 107 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 108 *CIP != ',' && *CIP != '\n')) 109 ++CIP; 110 CPULen = CIP - CPUStart; 111 } 112 } 113 } 114 } 115 } 116 117 if (CPUStart == 0) 118 while (CIP < CPUInfoEnd && *CIP != '\n') 119 ++CIP; 120 } 121 122 if (CPUStart == 0) 123 return generic; 124 125 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 126 .Case("604e", "604e") 127 .Case("604", "604") 128 .Case("7400", "7400") 129 .Case("7410", "7400") 130 .Case("7447", "7400") 131 .Case("7455", "7450") 132 .Case("G4", "g4") 133 .Case("POWER4", "970") 134 .Case("PPC970FX", "970") 135 .Case("PPC970MP", "970") 136 .Case("G5", "g5") 137 .Case("POWER5", "g5") 138 .Case("A2", "a2") 139 .Case("POWER6", "pwr6") 140 .Case("POWER7", "pwr7") 141 .Case("POWER8", "pwr8") 142 .Case("POWER8E", "pwr8") 143 .Case("POWER8NVL", "pwr8") 144 .Case("POWER9", "pwr9") 145 .Case("POWER10", "pwr10") 146 // FIXME: If we get a simulator or machine with the capabilities of 147 // mcpu=future, we should revisit this and add the name reported by the 148 // simulator/machine. 149 .Default(generic); 150 } 151 152 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { 153 // The cpuid register on arm is not accessible from user space. On Linux, 154 // it is exposed through the /proc/cpuinfo file. 155 156 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 157 // in all cases. 158 SmallVector<StringRef, 32> Lines; 159 ProcCpuinfoContent.split(Lines, "\n"); 160 161 // Look for the CPU implementer line. 162 StringRef Implementer; 163 StringRef Hardware; 164 StringRef Part; 165 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 166 if (Lines[I].startswith("CPU implementer")) 167 Implementer = Lines[I].substr(15).ltrim("\t :"); 168 if (Lines[I].startswith("Hardware")) 169 Hardware = Lines[I].substr(8).ltrim("\t :"); 170 if (Lines[I].startswith("CPU part")) 171 Part = Lines[I].substr(8).ltrim("\t :"); 172 } 173 174 if (Implementer == "0x41") { // ARM Ltd. 175 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 176 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 177 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 178 return "cortex-a53"; 179 180 181 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 182 // values correspond to the "Part number" in the CP15/c0 register. The 183 // contents are specified in the various processor manuals. 184 // This corresponds to the Main ID Register in Technical Reference Manuals. 185 // and is used in programs like sys-utils 186 return StringSwitch<const char *>(Part) 187 .Case("0x926", "arm926ej-s") 188 .Case("0xb02", "mpcore") 189 .Case("0xb36", "arm1136j-s") 190 .Case("0xb56", "arm1156t2-s") 191 .Case("0xb76", "arm1176jz-s") 192 .Case("0xc08", "cortex-a8") 193 .Case("0xc09", "cortex-a9") 194 .Case("0xc0f", "cortex-a15") 195 .Case("0xc20", "cortex-m0") 196 .Case("0xc23", "cortex-m3") 197 .Case("0xc24", "cortex-m4") 198 .Case("0xd22", "cortex-m55") 199 .Case("0xd02", "cortex-a34") 200 .Case("0xd04", "cortex-a35") 201 .Case("0xd03", "cortex-a53") 202 .Case("0xd07", "cortex-a57") 203 .Case("0xd08", "cortex-a72") 204 .Case("0xd09", "cortex-a73") 205 .Case("0xd0a", "cortex-a75") 206 .Case("0xd0b", "cortex-a76") 207 .Case("0xd0d", "cortex-a77") 208 .Case("0xd41", "cortex-a78") 209 .Case("0xd44", "cortex-x1") 210 .Case("0xd0c", "neoverse-n1") 211 .Case("0xd49", "neoverse-n2") 212 .Default("generic"); 213 } 214 215 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. 216 return StringSwitch<const char *>(Part) 217 .Case("0x516", "thunderx2t99") 218 .Case("0x0516", "thunderx2t99") 219 .Case("0xaf", "thunderx2t99") 220 .Case("0x0af", "thunderx2t99") 221 .Case("0xa1", "thunderxt88") 222 .Case("0x0a1", "thunderxt88") 223 .Default("generic"); 224 } 225 226 if (Implementer == "0x46") { // Fujitsu Ltd. 227 return StringSwitch<const char *>(Part) 228 .Case("0x001", "a64fx") 229 .Default("generic"); 230 } 231 232 if (Implementer == "0x4e") { // NVIDIA Corporation 233 return StringSwitch<const char *>(Part) 234 .Case("0x004", "carmel") 235 .Default("generic"); 236 } 237 238 if (Implementer == "0x48") // HiSilicon Technologies, Inc. 239 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 240 // values correspond to the "Part number" in the CP15/c0 register. The 241 // contents are specified in the various processor manuals. 242 return StringSwitch<const char *>(Part) 243 .Case("0xd01", "tsv110") 244 .Default("generic"); 245 246 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 247 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 248 // values correspond to the "Part number" in the CP15/c0 register. The 249 // contents are specified in the various processor manuals. 250 return StringSwitch<const char *>(Part) 251 .Case("0x06f", "krait") // APQ8064 252 .Case("0x201", "kryo") 253 .Case("0x205", "kryo") 254 .Case("0x211", "kryo") 255 .Case("0x800", "cortex-a73") // Kryo 2xx Gold 256 .Case("0x801", "cortex-a73") // Kryo 2xx Silver 257 .Case("0x802", "cortex-a75") // Kryo 3xx Gold 258 .Case("0x803", "cortex-a75") // Kryo 3xx Silver 259 .Case("0x804", "cortex-a76") // Kryo 4xx Gold 260 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver 261 .Case("0xc00", "falkor") 262 .Case("0xc01", "saphira") 263 .Default("generic"); 264 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. 265 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow 266 // any predictive pattern across variants and parts. 267 unsigned Variant = 0, Part = 0; 268 269 // Look for the CPU variant line, whose value is a 1 digit hexadecimal 270 // number, corresponding to the Variant bits in the CP15/C0 register. 271 for (auto I : Lines) 272 if (I.consume_front("CPU variant")) 273 I.ltrim("\t :").getAsInteger(0, Variant); 274 275 // Look for the CPU part line, whose value is a 3 digit hexadecimal 276 // number, corresponding to the PartNum bits in the CP15/C0 register. 277 for (auto I : Lines) 278 if (I.consume_front("CPU part")) 279 I.ltrim("\t :").getAsInteger(0, Part); 280 281 unsigned Exynos = (Variant << 12) | Part; 282 switch (Exynos) { 283 default: 284 // Default by falling through to Exynos M3. 285 LLVM_FALLTHROUGH; 286 case 0x1002: 287 return "exynos-m3"; 288 case 0x1003: 289 return "exynos-m4"; 290 } 291 } 292 293 return "generic"; 294 } 295 296 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { 297 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 298 299 // The "processor 0:" line comes after a fair amount of other information, 300 // including a cache breakdown, but this should be plenty. 301 SmallVector<StringRef, 32> Lines; 302 ProcCpuinfoContent.split(Lines, "\n"); 303 304 // Look for the CPU features. 305 SmallVector<StringRef, 32> CPUFeatures; 306 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 307 if (Lines[I].startswith("features")) { 308 size_t Pos = Lines[I].find(':'); 309 if (Pos != StringRef::npos) { 310 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 311 break; 312 } 313 } 314 315 // We need to check for the presence of vector support independently of 316 // the machine type, since we may only use the vector register set when 317 // supported by the kernel (and hypervisor). 318 bool HaveVectorSupport = false; 319 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 320 if (CPUFeatures[I] == "vx") 321 HaveVectorSupport = true; 322 } 323 324 // Now check the processor machine type. 325 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 326 if (Lines[I].startswith("processor ")) { 327 size_t Pos = Lines[I].find("machine = "); 328 if (Pos != StringRef::npos) { 329 Pos += sizeof("machine = ") - 1; 330 unsigned int Id; 331 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 332 if (Id >= 8561 && HaveVectorSupport) 333 return "z15"; 334 if (Id >= 3906 && HaveVectorSupport) 335 return "z14"; 336 if (Id >= 2964 && HaveVectorSupport) 337 return "z13"; 338 if (Id >= 2827) 339 return "zEC12"; 340 if (Id >= 2817) 341 return "z196"; 342 } 343 } 344 break; 345 } 346 } 347 348 return "generic"; 349 } 350 351 StringRef sys::detail::getHostCPUNameForBPF() { 352 #if !defined(__linux__) || !defined(__x86_64__) 353 return "generic"; 354 #else 355 uint8_t v3_insns[40] __attribute__ ((aligned (8))) = 356 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 357 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 358 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 359 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 360 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 361 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 362 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 363 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 364 /* BPF_EXIT_INSN() */ 365 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 366 367 uint8_t v2_insns[40] __attribute__ ((aligned (8))) = 368 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ 369 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 370 /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 371 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 372 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 373 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 374 /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 375 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 376 /* BPF_EXIT_INSN() */ 377 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; 378 379 struct bpf_prog_load_attr { 380 uint32_t prog_type; 381 uint32_t insn_cnt; 382 uint64_t insns; 383 uint64_t license; 384 uint32_t log_level; 385 uint32_t log_size; 386 uint64_t log_buf; 387 uint32_t kern_version; 388 uint32_t prog_flags; 389 } attr = {}; 390 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 391 attr.insn_cnt = 5; 392 attr.insns = (uint64_t)v3_insns; 393 attr.license = (uint64_t)"DUMMY"; 394 395 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, 396 sizeof(attr)); 397 if (fd >= 0) { 398 close(fd); 399 return "v3"; 400 } 401 402 /* Clear the whole attr in case its content changed by syscall. */ 403 memset(&attr, 0, sizeof(attr)); 404 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ 405 attr.insn_cnt = 5; 406 attr.insns = (uint64_t)v2_insns; 407 attr.license = (uint64_t)"DUMMY"; 408 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); 409 if (fd >= 0) { 410 close(fd); 411 return "v2"; 412 } 413 return "v1"; 414 #endif 415 } 416 417 #if defined(__i386__) || defined(_M_IX86) || \ 418 defined(__x86_64__) || defined(_M_X64) 419 420 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 421 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 422 // support. Consequently, for i386, the presence of CPUID is checked first 423 // via the corresponding eflags bit. 424 // Removal of cpuid.h header motivated by PR30384 425 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 426 // or test-suite, but are used in external projects e.g. libstdcxx 427 static bool isCpuIdSupported() { 428 #if defined(__GNUC__) || defined(__clang__) 429 #if defined(__i386__) 430 int __cpuid_supported; 431 __asm__(" pushfl\n" 432 " popl %%eax\n" 433 " movl %%eax,%%ecx\n" 434 " xorl $0x00200000,%%eax\n" 435 " pushl %%eax\n" 436 " popfl\n" 437 " pushfl\n" 438 " popl %%eax\n" 439 " movl $0,%0\n" 440 " cmpl %%eax,%%ecx\n" 441 " je 1f\n" 442 " movl $1,%0\n" 443 "1:" 444 : "=r"(__cpuid_supported) 445 : 446 : "eax", "ecx"); 447 if (!__cpuid_supported) 448 return false; 449 #endif 450 return true; 451 #endif 452 return true; 453 } 454 455 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 456 /// the specified arguments. If we can't run cpuid on the host, return true. 457 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 458 unsigned *rECX, unsigned *rEDX) { 459 #if defined(__GNUC__) || defined(__clang__) 460 #if defined(__x86_64__) 461 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 462 // FIXME: should we save this for Clang? 463 __asm__("movq\t%%rbx, %%rsi\n\t" 464 "cpuid\n\t" 465 "xchgq\t%%rbx, %%rsi\n\t" 466 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 467 : "a"(value)); 468 return false; 469 #elif defined(__i386__) 470 __asm__("movl\t%%ebx, %%esi\n\t" 471 "cpuid\n\t" 472 "xchgl\t%%ebx, %%esi\n\t" 473 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 474 : "a"(value)); 475 return false; 476 #else 477 return true; 478 #endif 479 #elif defined(_MSC_VER) 480 // The MSVC intrinsic is portable across x86 and x64. 481 int registers[4]; 482 __cpuid(registers, value); 483 *rEAX = registers[0]; 484 *rEBX = registers[1]; 485 *rECX = registers[2]; 486 *rEDX = registers[3]; 487 return false; 488 #else 489 return true; 490 #endif 491 } 492 493 namespace llvm { 494 namespace sys { 495 namespace detail { 496 namespace x86 { 497 498 VendorSignatures getVendorSignature(unsigned *MaxLeaf) { 499 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 500 if (MaxLeaf == nullptr) 501 MaxLeaf = &EAX; 502 else 503 *MaxLeaf = 0; 504 505 if (!isCpuIdSupported()) 506 return VendorSignatures::UNKNOWN; 507 508 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1) 509 return VendorSignatures::UNKNOWN; 510 511 // "Genu ineI ntel" 512 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e) 513 return VendorSignatures::GENUINE_INTEL; 514 515 // "Auth enti cAMD" 516 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163) 517 return VendorSignatures::AUTHENTIC_AMD; 518 519 return VendorSignatures::UNKNOWN; 520 } 521 522 } // namespace x86 523 } // namespace detail 524 } // namespace sys 525 } // namespace llvm 526 527 using namespace llvm::sys::detail::x86; 528 529 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 530 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 531 /// return true. 532 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 533 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 534 unsigned *rEDX) { 535 #if defined(__GNUC__) || defined(__clang__) 536 #if defined(__x86_64__) 537 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 538 // FIXME: should we save this for Clang? 539 __asm__("movq\t%%rbx, %%rsi\n\t" 540 "cpuid\n\t" 541 "xchgq\t%%rbx, %%rsi\n\t" 542 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 543 : "a"(value), "c"(subleaf)); 544 return false; 545 #elif defined(__i386__) 546 __asm__("movl\t%%ebx, %%esi\n\t" 547 "cpuid\n\t" 548 "xchgl\t%%ebx, %%esi\n\t" 549 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 550 : "a"(value), "c"(subleaf)); 551 return false; 552 #else 553 return true; 554 #endif 555 #elif defined(_MSC_VER) 556 int registers[4]; 557 __cpuidex(registers, value, subleaf); 558 *rEAX = registers[0]; 559 *rEBX = registers[1]; 560 *rECX = registers[2]; 561 *rEDX = registers[3]; 562 return false; 563 #else 564 return true; 565 #endif 566 } 567 568 // Read control register 0 (XCR0). Used to detect features such as AVX. 569 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 570 #if defined(__GNUC__) || defined(__clang__) 571 // Check xgetbv; this uses a .byte sequence instead of the instruction 572 // directly because older assemblers do not include support for xgetbv and 573 // there is no easy way to conditionally compile based on the assembler used. 574 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 575 return false; 576 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 577 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 578 *rEAX = Result; 579 *rEDX = Result >> 32; 580 return false; 581 #else 582 return true; 583 #endif 584 } 585 586 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 587 unsigned *Model) { 588 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 589 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 590 if (*Family == 6 || *Family == 0xf) { 591 if (*Family == 0xf) 592 // Examine extended family ID if family ID is F. 593 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 594 // Examine extended model ID if family ID is 6 or F. 595 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 596 } 597 } 598 599 static StringRef 600 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 601 const unsigned *Features, 602 unsigned *Type, unsigned *Subtype) { 603 auto testFeature = [&](unsigned F) { 604 return (Features[F / 32] & (1U << (F % 32))) != 0; 605 }; 606 607 StringRef CPU; 608 609 switch (Family) { 610 case 3: 611 CPU = "i386"; 612 break; 613 case 4: 614 CPU = "i486"; 615 break; 616 case 5: 617 if (testFeature(X86::FEATURE_MMX)) { 618 CPU = "pentium-mmx"; 619 break; 620 } 621 CPU = "pentium"; 622 break; 623 case 6: 624 switch (Model) { 625 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 626 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 627 // mobile processor, Intel Core 2 Extreme processor, Intel 628 // Pentium Dual-Core processor, Intel Xeon processor, model 629 // 0Fh. All processors are manufactured using the 65 nm process. 630 case 0x16: // Intel Celeron processor model 16h. All processors are 631 // manufactured using the 65 nm process 632 CPU = "core2"; 633 *Type = X86::INTEL_CORE2; 634 break; 635 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 636 // 17h. All processors are manufactured using the 45 nm process. 637 // 638 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 639 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 640 // the 45 nm process. 641 CPU = "penryn"; 642 *Type = X86::INTEL_CORE2; 643 break; 644 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 645 // processors are manufactured using the 45 nm process. 646 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 647 // As found in a Summer 2010 model iMac. 648 case 0x1f: 649 case 0x2e: // Nehalem EX 650 CPU = "nehalem"; 651 *Type = X86::INTEL_COREI7; 652 *Subtype = X86::INTEL_COREI7_NEHALEM; 653 break; 654 case 0x25: // Intel Core i7, laptop version. 655 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 656 // processors are manufactured using the 32 nm process. 657 case 0x2f: // Westmere EX 658 CPU = "westmere"; 659 *Type = X86::INTEL_COREI7; 660 *Subtype = X86::INTEL_COREI7_WESTMERE; 661 break; 662 case 0x2a: // Intel Core i7 processor. All processors are manufactured 663 // using the 32 nm process. 664 case 0x2d: 665 CPU = "sandybridge"; 666 *Type = X86::INTEL_COREI7; 667 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; 668 break; 669 case 0x3a: 670 case 0x3e: // Ivy Bridge EP 671 CPU = "ivybridge"; 672 *Type = X86::INTEL_COREI7; 673 *Subtype = X86::INTEL_COREI7_IVYBRIDGE; 674 break; 675 676 // Haswell: 677 case 0x3c: 678 case 0x3f: 679 case 0x45: 680 case 0x46: 681 CPU = "haswell"; 682 *Type = X86::INTEL_COREI7; 683 *Subtype = X86::INTEL_COREI7_HASWELL; 684 break; 685 686 // Broadwell: 687 case 0x3d: 688 case 0x47: 689 case 0x4f: 690 case 0x56: 691 CPU = "broadwell"; 692 *Type = X86::INTEL_COREI7; 693 *Subtype = X86::INTEL_COREI7_BROADWELL; 694 break; 695 696 // Skylake: 697 case 0x4e: // Skylake mobile 698 case 0x5e: // Skylake desktop 699 case 0x8e: // Kaby Lake mobile 700 case 0x9e: // Kaby Lake desktop 701 case 0xa5: // Comet Lake-H/S 702 case 0xa6: // Comet Lake-U 703 CPU = "skylake"; 704 *Type = X86::INTEL_COREI7; 705 *Subtype = X86::INTEL_COREI7_SKYLAKE; 706 break; 707 708 // Skylake Xeon: 709 case 0x55: 710 *Type = X86::INTEL_COREI7; 711 if (testFeature(X86::FEATURE_AVX512BF16)) { 712 CPU = "cooperlake"; 713 *Subtype = X86::INTEL_COREI7_COOPERLAKE; 714 } else if (testFeature(X86::FEATURE_AVX512VNNI)) { 715 CPU = "cascadelake"; 716 *Subtype = X86::INTEL_COREI7_CASCADELAKE; 717 } else { 718 CPU = "skylake-avx512"; 719 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; 720 } 721 break; 722 723 // Cannonlake: 724 case 0x66: 725 CPU = "cannonlake"; 726 *Type = X86::INTEL_COREI7; 727 *Subtype = X86::INTEL_COREI7_CANNONLAKE; 728 break; 729 730 // Icelake: 731 case 0x7d: 732 case 0x7e: 733 CPU = "icelake-client"; 734 *Type = X86::INTEL_COREI7; 735 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; 736 break; 737 738 // Icelake Xeon: 739 case 0x6a: 740 case 0x6c: 741 CPU = "icelake-server"; 742 *Type = X86::INTEL_COREI7; 743 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; 744 break; 745 746 // Sapphire Rapids: 747 case 0x8f: 748 CPU = "sapphirerapids"; 749 *Type = X86::INTEL_COREI7; 750 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS; 751 break; 752 753 case 0x1c: // Most 45 nm Intel Atom processors 754 case 0x26: // 45 nm Atom Lincroft 755 case 0x27: // 32 nm Atom Medfield 756 case 0x35: // 32 nm Atom Midview 757 case 0x36: // 32 nm Atom Midview 758 CPU = "bonnell"; 759 *Type = X86::INTEL_BONNELL; 760 break; 761 762 // Atom Silvermont codes from the Intel software optimization guide. 763 case 0x37: 764 case 0x4a: 765 case 0x4d: 766 case 0x5a: 767 case 0x5d: 768 case 0x4c: // really airmont 769 CPU = "silvermont"; 770 *Type = X86::INTEL_SILVERMONT; 771 break; 772 // Goldmont: 773 case 0x5c: // Apollo Lake 774 case 0x5f: // Denverton 775 CPU = "goldmont"; 776 *Type = X86::INTEL_GOLDMONT; 777 break; 778 case 0x7a: 779 CPU = "goldmont-plus"; 780 *Type = X86::INTEL_GOLDMONT_PLUS; 781 break; 782 case 0x86: 783 CPU = "tremont"; 784 *Type = X86::INTEL_TREMONT; 785 break; 786 787 // Xeon Phi (Knights Landing + Knights Mill): 788 case 0x57: 789 CPU = "knl"; 790 *Type = X86::INTEL_KNL; 791 break; 792 case 0x85: 793 CPU = "knm"; 794 *Type = X86::INTEL_KNM; 795 break; 796 797 default: // Unknown family 6 CPU, try to guess. 798 // Don't both with Type/Subtype here, they aren't used by the caller. 799 // They're used above to keep the code in sync with compiler-rt. 800 // TODO detect tigerlake host from model 801 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) { 802 CPU = "tigerlake"; 803 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) { 804 CPU = "icelake-client"; 805 } else if (testFeature(X86::FEATURE_AVX512VBMI)) { 806 CPU = "cannonlake"; 807 } else if (testFeature(X86::FEATURE_AVX512BF16)) { 808 CPU = "cooperlake"; 809 } else if (testFeature(X86::FEATURE_AVX512VNNI)) { 810 CPU = "cascadelake"; 811 } else if (testFeature(X86::FEATURE_AVX512VL)) { 812 CPU = "skylake-avx512"; 813 } else if (testFeature(X86::FEATURE_AVX512ER)) { 814 CPU = "knl"; 815 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) { 816 if (testFeature(X86::FEATURE_SHA)) 817 CPU = "goldmont"; 818 else 819 CPU = "skylake"; 820 } else if (testFeature(X86::FEATURE_ADX)) { 821 CPU = "broadwell"; 822 } else if (testFeature(X86::FEATURE_AVX2)) { 823 CPU = "haswell"; 824 } else if (testFeature(X86::FEATURE_AVX)) { 825 CPU = "sandybridge"; 826 } else if (testFeature(X86::FEATURE_SSE4_2)) { 827 if (testFeature(X86::FEATURE_MOVBE)) 828 CPU = "silvermont"; 829 else 830 CPU = "nehalem"; 831 } else if (testFeature(X86::FEATURE_SSE4_1)) { 832 CPU = "penryn"; 833 } else if (testFeature(X86::FEATURE_SSSE3)) { 834 if (testFeature(X86::FEATURE_MOVBE)) 835 CPU = "bonnell"; 836 else 837 CPU = "core2"; 838 } else if (testFeature(X86::FEATURE_64BIT)) { 839 CPU = "core2"; 840 } else if (testFeature(X86::FEATURE_SSE3)) { 841 CPU = "yonah"; 842 } else if (testFeature(X86::FEATURE_SSE2)) { 843 CPU = "pentium-m"; 844 } else if (testFeature(X86::FEATURE_SSE)) { 845 CPU = "pentium3"; 846 } else if (testFeature(X86::FEATURE_MMX)) { 847 CPU = "pentium2"; 848 } else { 849 CPU = "pentiumpro"; 850 } 851 break; 852 } 853 break; 854 case 15: { 855 if (testFeature(X86::FEATURE_64BIT)) { 856 CPU = "nocona"; 857 break; 858 } 859 if (testFeature(X86::FEATURE_SSE3)) { 860 CPU = "prescott"; 861 break; 862 } 863 CPU = "pentium4"; 864 break; 865 } 866 default: 867 break; // Unknown. 868 } 869 870 return CPU; 871 } 872 873 static StringRef 874 getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 875 const unsigned *Features, 876 unsigned *Type, unsigned *Subtype) { 877 auto testFeature = [&](unsigned F) { 878 return (Features[F / 32] & (1U << (F % 32))) != 0; 879 }; 880 881 StringRef CPU; 882 883 switch (Family) { 884 case 4: 885 CPU = "i486"; 886 break; 887 case 5: 888 CPU = "pentium"; 889 switch (Model) { 890 case 6: 891 case 7: 892 CPU = "k6"; 893 break; 894 case 8: 895 CPU = "k6-2"; 896 break; 897 case 9: 898 case 13: 899 CPU = "k6-3"; 900 break; 901 case 10: 902 CPU = "geode"; 903 break; 904 } 905 break; 906 case 6: 907 if (testFeature(X86::FEATURE_SSE)) { 908 CPU = "athlon-xp"; 909 break; 910 } 911 CPU = "athlon"; 912 break; 913 case 15: 914 if (testFeature(X86::FEATURE_SSE3)) { 915 CPU = "k8-sse3"; 916 break; 917 } 918 CPU = "k8"; 919 break; 920 case 16: 921 CPU = "amdfam10"; 922 *Type = X86::AMDFAM10H; // "amdfam10" 923 switch (Model) { 924 case 2: 925 *Subtype = X86::AMDFAM10H_BARCELONA; 926 break; 927 case 4: 928 *Subtype = X86::AMDFAM10H_SHANGHAI; 929 break; 930 case 8: 931 *Subtype = X86::AMDFAM10H_ISTANBUL; 932 break; 933 } 934 break; 935 case 20: 936 CPU = "btver1"; 937 *Type = X86::AMD_BTVER1; 938 break; 939 case 21: 940 CPU = "bdver1"; 941 *Type = X86::AMDFAM15H; 942 if (Model >= 0x60 && Model <= 0x7f) { 943 CPU = "bdver4"; 944 *Subtype = X86::AMDFAM15H_BDVER4; 945 break; // 60h-7Fh: Excavator 946 } 947 if (Model >= 0x30 && Model <= 0x3f) { 948 CPU = "bdver3"; 949 *Subtype = X86::AMDFAM15H_BDVER3; 950 break; // 30h-3Fh: Steamroller 951 } 952 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { 953 CPU = "bdver2"; 954 *Subtype = X86::AMDFAM15H_BDVER2; 955 break; // 02h, 10h-1Fh: Piledriver 956 } 957 if (Model <= 0x0f) { 958 *Subtype = X86::AMDFAM15H_BDVER1; 959 break; // 00h-0Fh: Bulldozer 960 } 961 break; 962 case 22: 963 CPU = "btver2"; 964 *Type = X86::AMD_BTVER2; 965 break; 966 case 23: 967 CPU = "znver1"; 968 *Type = X86::AMDFAM17H; 969 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) { 970 CPU = "znver2"; 971 *Subtype = X86::AMDFAM17H_ZNVER2; 972 break; // 30h-3fh, 71h: Zen2 973 } 974 if (Model <= 0x0f) { 975 *Subtype = X86::AMDFAM17H_ZNVER1; 976 break; // 00h-0Fh: Zen1 977 } 978 break; 979 case 25: 980 CPU = "znver3"; 981 *Type = X86::AMDFAM19H; 982 if (Model <= 0x0f) { 983 *Subtype = X86::AMDFAM19H_ZNVER3; 984 break; // 00h-0Fh: Zen3 985 } 986 break; 987 default: 988 break; // Unknown AMD CPU. 989 } 990 991 return CPU; 992 } 993 994 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 995 unsigned *Features) { 996 unsigned EAX, EBX; 997 998 auto setFeature = [&](unsigned F) { 999 Features[F / 32] |= 1U << (F % 32); 1000 }; 1001 1002 if ((EDX >> 15) & 1) 1003 setFeature(X86::FEATURE_CMOV); 1004 if ((EDX >> 23) & 1) 1005 setFeature(X86::FEATURE_MMX); 1006 if ((EDX >> 25) & 1) 1007 setFeature(X86::FEATURE_SSE); 1008 if ((EDX >> 26) & 1) 1009 setFeature(X86::FEATURE_SSE2); 1010 1011 if ((ECX >> 0) & 1) 1012 setFeature(X86::FEATURE_SSE3); 1013 if ((ECX >> 1) & 1) 1014 setFeature(X86::FEATURE_PCLMUL); 1015 if ((ECX >> 9) & 1) 1016 setFeature(X86::FEATURE_SSSE3); 1017 if ((ECX >> 12) & 1) 1018 setFeature(X86::FEATURE_FMA); 1019 if ((ECX >> 19) & 1) 1020 setFeature(X86::FEATURE_SSE4_1); 1021 if ((ECX >> 20) & 1) 1022 setFeature(X86::FEATURE_SSE4_2); 1023 if ((ECX >> 23) & 1) 1024 setFeature(X86::FEATURE_POPCNT); 1025 if ((ECX >> 25) & 1) 1026 setFeature(X86::FEATURE_AES); 1027 1028 if ((ECX >> 22) & 1) 1029 setFeature(X86::FEATURE_MOVBE); 1030 1031 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1032 // indicates that the AVX registers will be saved and restored on context 1033 // switch, then we have full AVX support. 1034 const unsigned AVXBits = (1 << 27) | (1 << 28); 1035 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 1036 ((EAX & 0x6) == 0x6); 1037 #if defined(__APPLE__) 1038 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1039 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1040 // set right now. 1041 bool HasAVX512Save = true; 1042 #else 1043 // AVX512 requires additional context to be saved by the OS. 1044 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 1045 #endif 1046 1047 if (HasAVX) 1048 setFeature(X86::FEATURE_AVX); 1049 1050 bool HasLeaf7 = 1051 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1052 1053 if (HasLeaf7 && ((EBX >> 3) & 1)) 1054 setFeature(X86::FEATURE_BMI); 1055 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 1056 setFeature(X86::FEATURE_AVX2); 1057 if (HasLeaf7 && ((EBX >> 8) & 1)) 1058 setFeature(X86::FEATURE_BMI2); 1059 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 1060 setFeature(X86::FEATURE_AVX512F); 1061 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 1062 setFeature(X86::FEATURE_AVX512DQ); 1063 if (HasLeaf7 && ((EBX >> 19) & 1)) 1064 setFeature(X86::FEATURE_ADX); 1065 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 1066 setFeature(X86::FEATURE_AVX512IFMA); 1067 if (HasLeaf7 && ((EBX >> 23) & 1)) 1068 setFeature(X86::FEATURE_CLFLUSHOPT); 1069 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 1070 setFeature(X86::FEATURE_AVX512PF); 1071 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 1072 setFeature(X86::FEATURE_AVX512ER); 1073 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 1074 setFeature(X86::FEATURE_AVX512CD); 1075 if (HasLeaf7 && ((EBX >> 29) & 1)) 1076 setFeature(X86::FEATURE_SHA); 1077 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 1078 setFeature(X86::FEATURE_AVX512BW); 1079 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 1080 setFeature(X86::FEATURE_AVX512VL); 1081 1082 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 1083 setFeature(X86::FEATURE_AVX512VBMI); 1084 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) 1085 setFeature(X86::FEATURE_AVX512VBMI2); 1086 if (HasLeaf7 && ((ECX >> 8) & 1)) 1087 setFeature(X86::FEATURE_GFNI); 1088 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) 1089 setFeature(X86::FEATURE_VPCLMULQDQ); 1090 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) 1091 setFeature(X86::FEATURE_AVX512VNNI); 1092 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) 1093 setFeature(X86::FEATURE_AVX512BITALG); 1094 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 1095 setFeature(X86::FEATURE_AVX512VPOPCNTDQ); 1096 1097 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 1098 setFeature(X86::FEATURE_AVX5124VNNIW); 1099 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 1100 setFeature(X86::FEATURE_AVX5124FMAPS); 1101 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) 1102 setFeature(X86::FEATURE_AVX512VP2INTERSECT); 1103 1104 bool HasLeaf7Subleaf1 = 1105 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1106 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save) 1107 setFeature(X86::FEATURE_AVX512BF16); 1108 1109 unsigned MaxExtLevel; 1110 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1111 1112 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1113 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1114 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1115 setFeature(X86::FEATURE_SSE4_A); 1116 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1117 setFeature(X86::FEATURE_XOP); 1118 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1119 setFeature(X86::FEATURE_FMA4); 1120 1121 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1122 setFeature(X86::FEATURE_64BIT); 1123 } 1124 1125 StringRef sys::getHostCPUName() { 1126 unsigned MaxLeaf = 0; 1127 const VendorSignatures Vendor = getVendorSignature(&MaxLeaf); 1128 if (Vendor == VendorSignatures::UNKNOWN) 1129 return "generic"; 1130 1131 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1132 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1133 1134 unsigned Family = 0, Model = 0; 1135 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}; 1136 detectX86FamilyModel(EAX, &Family, &Model); 1137 getAvailableFeatures(ECX, EDX, MaxLeaf, Features); 1138 1139 // These aren't consumed in this file, but we try to keep some source code the 1140 // same or similar to compiler-rt. 1141 unsigned Type = 0; 1142 unsigned Subtype = 0; 1143 1144 StringRef CPU; 1145 1146 if (Vendor == VendorSignatures::GENUINE_INTEL) { 1147 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type, 1148 &Subtype); 1149 } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) { 1150 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, 1151 &Subtype); 1152 } 1153 1154 if (!CPU.empty()) 1155 return CPU; 1156 1157 return "generic"; 1158 } 1159 1160 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1161 StringRef sys::getHostCPUName() { 1162 host_basic_info_data_t hostInfo; 1163 mach_msg_type_number_t infoCount; 1164 1165 infoCount = HOST_BASIC_INFO_COUNT; 1166 mach_port_t hostPort = mach_host_self(); 1167 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1168 &infoCount); 1169 mach_port_deallocate(mach_task_self(), hostPort); 1170 1171 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1172 return "generic"; 1173 1174 switch (hostInfo.cpu_subtype) { 1175 case CPU_SUBTYPE_POWERPC_601: 1176 return "601"; 1177 case CPU_SUBTYPE_POWERPC_602: 1178 return "602"; 1179 case CPU_SUBTYPE_POWERPC_603: 1180 return "603"; 1181 case CPU_SUBTYPE_POWERPC_603e: 1182 return "603e"; 1183 case CPU_SUBTYPE_POWERPC_603ev: 1184 return "603ev"; 1185 case CPU_SUBTYPE_POWERPC_604: 1186 return "604"; 1187 case CPU_SUBTYPE_POWERPC_604e: 1188 return "604e"; 1189 case CPU_SUBTYPE_POWERPC_620: 1190 return "620"; 1191 case CPU_SUBTYPE_POWERPC_750: 1192 return "750"; 1193 case CPU_SUBTYPE_POWERPC_7400: 1194 return "7400"; 1195 case CPU_SUBTYPE_POWERPC_7450: 1196 return "7450"; 1197 case CPU_SUBTYPE_POWERPC_970: 1198 return "970"; 1199 default:; 1200 } 1201 1202 return "generic"; 1203 } 1204 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1205 StringRef sys::getHostCPUName() { 1206 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1207 StringRef Content = P ? P->getBuffer() : ""; 1208 return detail::getHostCPUNameForPowerPC(Content); 1209 } 1210 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1211 StringRef sys::getHostCPUName() { 1212 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1213 StringRef Content = P ? P->getBuffer() : ""; 1214 return detail::getHostCPUNameForARM(Content); 1215 } 1216 #elif defined(__linux__) && defined(__s390x__) 1217 StringRef sys::getHostCPUName() { 1218 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1219 StringRef Content = P ? P->getBuffer() : ""; 1220 return detail::getHostCPUNameForS390x(Content); 1221 } 1222 #elif defined(__APPLE__) && defined(__aarch64__) 1223 StringRef sys::getHostCPUName() { 1224 return "cyclone"; 1225 } 1226 #elif defined(__APPLE__) && defined(__arm__) 1227 StringRef sys::getHostCPUName() { 1228 host_basic_info_data_t hostInfo; 1229 mach_msg_type_number_t infoCount; 1230 1231 infoCount = HOST_BASIC_INFO_COUNT; 1232 mach_port_t hostPort = mach_host_self(); 1233 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, 1234 &infoCount); 1235 mach_port_deallocate(mach_task_self(), hostPort); 1236 1237 if (hostInfo.cpu_type != CPU_TYPE_ARM) { 1238 assert(false && "CPUType not equal to ARM should not be possible on ARM"); 1239 return "generic"; 1240 } 1241 switch (hostInfo.cpu_subtype) { 1242 case CPU_SUBTYPE_ARM_V7S: 1243 return "swift"; 1244 default:; 1245 } 1246 1247 return "generic"; 1248 } 1249 #else 1250 StringRef sys::getHostCPUName() { return "generic"; } 1251 namespace llvm { 1252 namespace sys { 1253 namespace detail { 1254 namespace x86 { 1255 1256 VendorSignatures getVendorSignature(unsigned *MaxLeaf) { 1257 return VendorSignatures::UNKNOWN; 1258 } 1259 1260 } // namespace x86 1261 } // namespace detail 1262 } // namespace sys 1263 } // namespace llvm 1264 #endif 1265 1266 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) 1267 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1268 // using the number of unique physical/core id pairs. The following 1269 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1270 int computeHostNumPhysicalCores() { 1271 // Enabled represents the number of physical id/core id pairs with at least 1272 // one processor id enabled by the CPU affinity mask. 1273 cpu_set_t Affinity, Enabled; 1274 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) != 0) 1275 return -1; 1276 CPU_ZERO(&Enabled); 1277 1278 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1279 // mmapped because it appears to have 0 size. 1280 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1281 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1282 if (std::error_code EC = Text.getError()) { 1283 llvm::errs() << "Can't read " 1284 << "/proc/cpuinfo: " << EC.message() << "\n"; 1285 return -1; 1286 } 1287 SmallVector<StringRef, 8> strs; 1288 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1289 /*KeepEmpty=*/false); 1290 int CurProcessor = -1; 1291 int CurPhysicalId = -1; 1292 int CurSiblings = -1; 1293 int CurCoreId = -1; 1294 for (StringRef Line : strs) { 1295 std::pair<StringRef, StringRef> Data = Line.split(':'); 1296 auto Name = Data.first.trim(); 1297 auto Val = Data.second.trim(); 1298 // These fields are available if the kernel is configured with CONFIG_SMP. 1299 if (Name == "processor") 1300 Val.getAsInteger(10, CurProcessor); 1301 else if (Name == "physical id") 1302 Val.getAsInteger(10, CurPhysicalId); 1303 else if (Name == "siblings") 1304 Val.getAsInteger(10, CurSiblings); 1305 else if (Name == "core id") { 1306 Val.getAsInteger(10, CurCoreId); 1307 // The processor id corresponds to an index into cpu_set_t. 1308 if (CPU_ISSET(CurProcessor, &Affinity)) 1309 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &Enabled); 1310 } 1311 } 1312 return CPU_COUNT(&Enabled); 1313 } 1314 #elif defined(__linux__) && defined(__powerpc__) 1315 int computeHostNumPhysicalCores() { 1316 cpu_set_t Affinity; 1317 if (sched_getaffinity(0, sizeof(Affinity), &Affinity) == 0) 1318 return CPU_COUNT(&Affinity); 1319 1320 // The call to sched_getaffinity() may have failed because the Affinity 1321 // mask is too small for the number of CPU's on the system (i.e. the 1322 // system has more than 1024 CPUs). Allocate a mask large enough for 1323 // twice as many CPUs. 1324 cpu_set_t *DynAffinity; 1325 DynAffinity = CPU_ALLOC(2048); 1326 if (sched_getaffinity(0, CPU_ALLOC_SIZE(2048), DynAffinity) == 0) { 1327 int NumCPUs = CPU_COUNT(DynAffinity); 1328 CPU_FREE(DynAffinity); 1329 return NumCPUs; 1330 } 1331 return -1; 1332 } 1333 #elif defined(__linux__) && defined(__s390x__) 1334 int computeHostNumPhysicalCores() { return sysconf(_SC_NPROCESSORS_ONLN); } 1335 #elif defined(__APPLE__) && defined(__x86_64__) 1336 #include <sys/param.h> 1337 #include <sys/sysctl.h> 1338 1339 // Gets the number of *physical cores* on the machine. 1340 int computeHostNumPhysicalCores() { 1341 uint32_t count; 1342 size_t len = sizeof(count); 1343 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1344 if (count < 1) { 1345 int nm[2]; 1346 nm[0] = CTL_HW; 1347 nm[1] = HW_AVAILCPU; 1348 sysctl(nm, 2, &count, &len, NULL, 0); 1349 if (count < 1) 1350 return -1; 1351 } 1352 return count; 1353 } 1354 #elif defined(__MVS__) 1355 int computeHostNumPhysicalCores() { 1356 enum { 1357 // Byte offset of the pointer to the Communications Vector Table (CVT) in 1358 // the Prefixed Save Area (PSA). The table entry is a 31-bit pointer and 1359 // will be zero-extended to uintptr_t. 1360 FLCCVT = 16, 1361 // Byte offset of the pointer to the Common System Data Area (CSD) in the 1362 // CVT. The table entry is a 31-bit pointer and will be zero-extended to 1363 // uintptr_t. 1364 CVTCSD = 660, 1365 // Byte offset to the number of live CPs in the LPAR, stored as a signed 1366 // 32-bit value in the table. 1367 CSD_NUMBER_ONLINE_STANDARD_CPS = 264, 1368 }; 1369 char *PSA = 0; 1370 char *CVT = reinterpret_cast<char *>( 1371 static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(PSA[FLCCVT]))); 1372 char *CSD = reinterpret_cast<char *>( 1373 static_cast<uintptr_t>(reinterpret_cast<unsigned int &>(CVT[CVTCSD]))); 1374 return reinterpret_cast<int &>(CSD[CSD_NUMBER_ONLINE_STANDARD_CPS]); 1375 } 1376 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0 1377 // Defined in llvm/lib/Support/Windows/Threading.inc 1378 int computeHostNumPhysicalCores(); 1379 #else 1380 // On other systems, return -1 to indicate unknown. 1381 static int computeHostNumPhysicalCores() { return -1; } 1382 #endif 1383 1384 int sys::getHostNumPhysicalCores() { 1385 static int NumCores = computeHostNumPhysicalCores(); 1386 return NumCores; 1387 } 1388 1389 #if defined(__i386__) || defined(_M_IX86) || \ 1390 defined(__x86_64__) || defined(_M_X64) 1391 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1392 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1393 unsigned MaxLevel; 1394 1395 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1) 1396 return false; 1397 1398 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1399 1400 Features["cx8"] = (EDX >> 8) & 1; 1401 Features["cmov"] = (EDX >> 15) & 1; 1402 Features["mmx"] = (EDX >> 23) & 1; 1403 Features["fxsr"] = (EDX >> 24) & 1; 1404 Features["sse"] = (EDX >> 25) & 1; 1405 Features["sse2"] = (EDX >> 26) & 1; 1406 1407 Features["sse3"] = (ECX >> 0) & 1; 1408 Features["pclmul"] = (ECX >> 1) & 1; 1409 Features["ssse3"] = (ECX >> 9) & 1; 1410 Features["cx16"] = (ECX >> 13) & 1; 1411 Features["sse4.1"] = (ECX >> 19) & 1; 1412 Features["sse4.2"] = (ECX >> 20) & 1; 1413 Features["movbe"] = (ECX >> 22) & 1; 1414 Features["popcnt"] = (ECX >> 23) & 1; 1415 Features["aes"] = (ECX >> 25) & 1; 1416 Features["rdrnd"] = (ECX >> 30) & 1; 1417 1418 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1419 // indicates that the AVX registers will be saved and restored on context 1420 // switch, then we have full AVX support. 1421 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX); 1422 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6); 1423 #if defined(__APPLE__) 1424 // Darwin lazily saves the AVX512 context on first use: trust that the OS will 1425 // save the AVX512 context if we use AVX512 instructions, even the bit is not 1426 // set right now. 1427 bool HasAVX512Save = true; 1428 #else 1429 // AVX512 requires additional context to be saved by the OS. 1430 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1431 #endif 1432 // AMX requires additional context to be saved by the OS. 1433 const unsigned AMXBits = (1 << 17) | (1 << 18); 1434 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits); 1435 1436 Features["avx"] = HasAVXSave; 1437 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; 1438 // Only enable XSAVE if OS has enabled support for saving YMM state. 1439 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; 1440 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; 1441 1442 unsigned MaxExtLevel; 1443 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1444 1445 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1446 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1447 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); 1448 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1449 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1450 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1451 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1452 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1453 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1454 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1455 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1456 1457 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); 1458 1459 // Miscellaneous memory related features, detected by 1460 // using the 0x80000008 leaf of the CPUID instruction 1461 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1462 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); 1463 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1464 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); 1465 1466 bool HasLeaf7 = 1467 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1468 1469 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1470 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1471 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1472 // AVX2 is only supported if we have the OS save support from AVX. 1473 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; 1474 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1475 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); 1476 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1477 // AVX512 is only supported if the OS supports the context save for it. 1478 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1479 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1480 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1481 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1482 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1483 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1484 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1485 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1486 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1487 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1488 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1489 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1490 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1491 1492 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); 1493 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1494 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1495 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); 1496 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; 1497 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); 1498 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); 1499 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; 1500 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; 1501 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; 1502 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; 1503 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1504 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); 1505 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker 1506 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); 1507 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); 1508 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); 1509 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); 1510 1511 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1); 1512 Features["avx512vp2intersect"] = 1513 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save; 1514 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); 1515 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); 1516 // There are two CPUID leafs which information associated with the pconfig 1517 // instruction: 1518 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th 1519 // bit of EDX), while the EAX=0x1b leaf returns information on the 1520 // availability of specific pconfig leafs. 1521 // The target feature here only refers to the the first of these two. 1522 // Users might need to check for the availability of specific pconfig 1523 // leaves using cpuid, since that information is ignored while 1524 // detecting features using the "-march=native" flag. 1525 // For more info, see X86 ISA docs. 1526 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); 1527 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave; 1528 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave; 1529 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave; 1530 bool HasLeaf7Subleaf1 = 1531 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); 1532 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave; 1533 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; 1534 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1); 1535 1536 bool HasLeafD = MaxLevel >= 0xd && 1537 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1538 1539 // Only enable XSAVE if OS has enabled support for saving YMM state. 1540 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; 1541 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; 1542 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; 1543 1544 bool HasLeaf14 = MaxLevel >= 0x14 && 1545 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); 1546 1547 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); 1548 1549 bool HasLeaf19 = 1550 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX); 1551 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1); 1552 1553 return true; 1554 } 1555 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1556 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1557 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1558 if (!P) 1559 return false; 1560 1561 SmallVector<StringRef, 32> Lines; 1562 P->getBuffer().split(Lines, "\n"); 1563 1564 SmallVector<StringRef, 32> CPUFeatures; 1565 1566 // Look for the CPU features. 1567 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1568 if (Lines[I].startswith("Features")) { 1569 Lines[I].split(CPUFeatures, ' '); 1570 break; 1571 } 1572 1573 #if defined(__aarch64__) 1574 // Keep track of which crypto features we have seen 1575 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1576 uint32_t crypto = 0; 1577 #endif 1578 1579 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1580 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1581 #if defined(__aarch64__) 1582 .Case("asimd", "neon") 1583 .Case("fp", "fp-armv8") 1584 .Case("crc32", "crc") 1585 #else 1586 .Case("half", "fp16") 1587 .Case("neon", "neon") 1588 .Case("vfpv3", "vfp3") 1589 .Case("vfpv3d16", "d16") 1590 .Case("vfpv4", "vfp4") 1591 .Case("idiva", "hwdiv-arm") 1592 .Case("idivt", "hwdiv") 1593 #endif 1594 .Default(""); 1595 1596 #if defined(__aarch64__) 1597 // We need to check crypto separately since we need all of the crypto 1598 // extensions to enable the subtarget feature 1599 if (CPUFeatures[I] == "aes") 1600 crypto |= CAP_AES; 1601 else if (CPUFeatures[I] == "pmull") 1602 crypto |= CAP_PMULL; 1603 else if (CPUFeatures[I] == "sha1") 1604 crypto |= CAP_SHA1; 1605 else if (CPUFeatures[I] == "sha2") 1606 crypto |= CAP_SHA2; 1607 #endif 1608 1609 if (LLVMFeatureStr != "") 1610 Features[LLVMFeatureStr] = true; 1611 } 1612 1613 #if defined(__aarch64__) 1614 // If we have all crypto bits we can add the feature 1615 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1616 Features["crypto"] = true; 1617 #endif 1618 1619 return true; 1620 } 1621 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64)) 1622 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1623 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE)) 1624 Features["neon"] = true; 1625 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) 1626 Features["crc"] = true; 1627 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) 1628 Features["crypto"] = true; 1629 1630 return true; 1631 } 1632 #else 1633 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1634 #endif 1635 1636 std::string sys::getProcessTriple() { 1637 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1638 Triple PT(Triple::normalize(TargetTripleString)); 1639 1640 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1641 PT = PT.get64BitArchVariant(); 1642 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1643 PT = PT.get32BitArchVariant(); 1644 1645 return PT.str(); 1646 } 1647