1*0b57cec5SDimitry Andric //===-- RegisterContextOpenBSD_i386.cpp -----------------------------------===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===---------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric 9*0b57cec5SDimitry Andric #include "RegisterContextOpenBSD_i386.h" 10*0b57cec5SDimitry Andric #include "RegisterContextPOSIX_x86.h" 11*0b57cec5SDimitry Andric 12*0b57cec5SDimitry Andric using namespace lldb_private; 13*0b57cec5SDimitry Andric using namespace lldb; 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andric // /usr/include/machine/reg.h 16*0b57cec5SDimitry Andric struct GPR { 17*0b57cec5SDimitry Andric uint32_t eax; 18*0b57cec5SDimitry Andric uint32_t ecx; 19*0b57cec5SDimitry Andric uint32_t edx; 20*0b57cec5SDimitry Andric uint32_t ebx; 21*0b57cec5SDimitry Andric uint32_t esp; 22*0b57cec5SDimitry Andric uint32_t ebp; 23*0b57cec5SDimitry Andric uint32_t esi; 24*0b57cec5SDimitry Andric uint32_t edi; 25*0b57cec5SDimitry Andric uint32_t eip; 26*0b57cec5SDimitry Andric uint32_t eflags; 27*0b57cec5SDimitry Andric uint32_t cs; 28*0b57cec5SDimitry Andric uint32_t ss; 29*0b57cec5SDimitry Andric uint32_t ds; 30*0b57cec5SDimitry Andric uint32_t es; 31*0b57cec5SDimitry Andric uint32_t fs; 32*0b57cec5SDimitry Andric uint32_t gs; 33*0b57cec5SDimitry Andric }; 34*0b57cec5SDimitry Andric 35*0b57cec5SDimitry Andric struct dbreg { 36*0b57cec5SDimitry Andric uint32_t dr[8]; /* debug registers */ 37*0b57cec5SDimitry Andric /* Index 0-3: debug address registers */ 38*0b57cec5SDimitry Andric /* Index 4-5: reserved */ 39*0b57cec5SDimitry Andric /* Index 6: debug status */ 40*0b57cec5SDimitry Andric /* Index 7: debug control */ 41*0b57cec5SDimitry Andric }; 42*0b57cec5SDimitry Andric 43*0b57cec5SDimitry Andric using FPR_i386 = FXSAVE; 44*0b57cec5SDimitry Andric 45*0b57cec5SDimitry Andric struct UserArea { 46*0b57cec5SDimitry Andric GPR gpr; 47*0b57cec5SDimitry Andric FPR_i386 i387; 48*0b57cec5SDimitry Andric }; 49*0b57cec5SDimitry Andric 50*0b57cec5SDimitry Andric #define DR_SIZE sizeof(uint32_t) 51*0b57cec5SDimitry Andric #define DR_OFFSET(reg_index) (LLVM_EXTENSION offsetof(dbreg, dr[reg_index])) 52*0b57cec5SDimitry Andric 53*0b57cec5SDimitry Andric // Include RegisterInfos_i386 to declare our g_register_infos_i386 structure. 54*0b57cec5SDimitry Andric #define DECLARE_REGISTER_INFOS_I386_STRUCT 55*0b57cec5SDimitry Andric #include "RegisterInfos_i386.h" 56*0b57cec5SDimitry Andric #undef DECLARE_REGISTER_INFOS_I386_STRUCT 57*0b57cec5SDimitry Andric RegisterContextOpenBSD_i386(const ArchSpec & target_arch)58*0b57cec5SDimitry AndricRegisterContextOpenBSD_i386::RegisterContextOpenBSD_i386( 59*0b57cec5SDimitry Andric const ArchSpec &target_arch) 60*0b57cec5SDimitry Andric : RegisterInfoInterface(target_arch) {} 61*0b57cec5SDimitry Andric GetGPRSize() const62*0b57cec5SDimitry Andricsize_t RegisterContextOpenBSD_i386::GetGPRSize() const { return sizeof(GPR); } 63*0b57cec5SDimitry Andric GetRegisterInfo() const64*0b57cec5SDimitry Andricconst RegisterInfo *RegisterContextOpenBSD_i386::GetRegisterInfo() const { 65*0b57cec5SDimitry Andric switch (m_target_arch.GetMachine()) { 66*0b57cec5SDimitry Andric case llvm::Triple::x86: 67*0b57cec5SDimitry Andric return g_register_infos_i386; 68*0b57cec5SDimitry Andric default: 69*0b57cec5SDimitry Andric assert(false && "Unhandled target architecture."); 70*0b57cec5SDimitry Andric return nullptr; 71*0b57cec5SDimitry Andric } 72*0b57cec5SDimitry Andric } 73*0b57cec5SDimitry Andric GetRegisterCount() const74*0b57cec5SDimitry Andricuint32_t RegisterContextOpenBSD_i386::GetRegisterCount() const { 75*0b57cec5SDimitry Andric return static_cast<uint32_t>(sizeof(g_register_infos_i386) / 76*0b57cec5SDimitry Andric sizeof(g_register_infos_i386[0])); 77*0b57cec5SDimitry Andric } 78