15ffd83dbSDimitry Andric //===-- RegisterContextMach_arm.cpp ---------------------------------------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric 
90b57cec5SDimitry Andric #if defined(__APPLE__)
100b57cec5SDimitry Andric 
110b57cec5SDimitry Andric #include "RegisterContextMach_arm.h"
120b57cec5SDimitry Andric 
130b57cec5SDimitry Andric #include <mach/mach_types.h>
140b57cec5SDimitry Andric #include <mach/thread_act.h>
150b57cec5SDimitry Andric 
160b57cec5SDimitry Andric 
170b57cec5SDimitry Andric using namespace lldb;
180b57cec5SDimitry Andric using namespace lldb_private;
190b57cec5SDimitry Andric 
RegisterContextMach_arm(Thread & thread,uint32_t concrete_frame_idx)200b57cec5SDimitry Andric RegisterContextMach_arm::RegisterContextMach_arm(Thread &thread,
210b57cec5SDimitry Andric                                                  uint32_t concrete_frame_idx)
220b57cec5SDimitry Andric     : RegisterContextDarwin_arm(thread, concrete_frame_idx) {}
230b57cec5SDimitry Andric 
24*5f7ddb14SDimitry Andric RegisterContextMach_arm::~RegisterContextMach_arm() = default;
250b57cec5SDimitry Andric 
DoReadGPR(lldb::tid_t tid,int flavor,GPR & gpr)260b57cec5SDimitry Andric int RegisterContextMach_arm::DoReadGPR(lldb::tid_t tid, int flavor, GPR &gpr) {
270b57cec5SDimitry Andric   mach_msg_type_number_t count = GPRWordCount;
280b57cec5SDimitry Andric   return ::thread_get_state(tid, flavor, (thread_state_t)&gpr, &count);
290b57cec5SDimitry Andric }
300b57cec5SDimitry Andric 
DoReadFPU(lldb::tid_t tid,int flavor,FPU & fpu)310b57cec5SDimitry Andric int RegisterContextMach_arm::DoReadFPU(lldb::tid_t tid, int flavor, FPU &fpu) {
320b57cec5SDimitry Andric   mach_msg_type_number_t count = FPUWordCount;
330b57cec5SDimitry Andric   return ::thread_get_state(tid, flavor, (thread_state_t)&fpu, &count);
340b57cec5SDimitry Andric }
350b57cec5SDimitry Andric 
DoReadEXC(lldb::tid_t tid,int flavor,EXC & exc)360b57cec5SDimitry Andric int RegisterContextMach_arm::DoReadEXC(lldb::tid_t tid, int flavor, EXC &exc) {
370b57cec5SDimitry Andric   mach_msg_type_number_t count = EXCWordCount;
380b57cec5SDimitry Andric   return ::thread_get_state(tid, flavor, (thread_state_t)&exc, &count);
390b57cec5SDimitry Andric }
400b57cec5SDimitry Andric 
DoReadDBG(lldb::tid_t tid,int flavor,DBG & dbg)410b57cec5SDimitry Andric int RegisterContextMach_arm::DoReadDBG(lldb::tid_t tid, int flavor, DBG &dbg) {
420b57cec5SDimitry Andric   mach_msg_type_number_t count = DBGWordCount;
430b57cec5SDimitry Andric   return ::thread_get_state(tid, flavor, (thread_state_t)&dbg, &count);
440b57cec5SDimitry Andric }
450b57cec5SDimitry Andric 
DoWriteGPR(lldb::tid_t tid,int flavor,const GPR & gpr)460b57cec5SDimitry Andric int RegisterContextMach_arm::DoWriteGPR(lldb::tid_t tid, int flavor,
470b57cec5SDimitry Andric                                         const GPR &gpr) {
480b57cec5SDimitry Andric   return ::thread_set_state(
490b57cec5SDimitry Andric       tid, flavor, reinterpret_cast<thread_state_t>(const_cast<GPR *>(&gpr)),
500b57cec5SDimitry Andric       GPRWordCount);
510b57cec5SDimitry Andric }
520b57cec5SDimitry Andric 
DoWriteFPU(lldb::tid_t tid,int flavor,const FPU & fpu)530b57cec5SDimitry Andric int RegisterContextMach_arm::DoWriteFPU(lldb::tid_t tid, int flavor,
540b57cec5SDimitry Andric                                         const FPU &fpu) {
550b57cec5SDimitry Andric   return ::thread_set_state(
560b57cec5SDimitry Andric       tid, flavor, reinterpret_cast<thread_state_t>(const_cast<FPU *>(&fpu)),
570b57cec5SDimitry Andric       FPUWordCount);
580b57cec5SDimitry Andric }
590b57cec5SDimitry Andric 
DoWriteEXC(lldb::tid_t tid,int flavor,const EXC & exc)600b57cec5SDimitry Andric int RegisterContextMach_arm::DoWriteEXC(lldb::tid_t tid, int flavor,
610b57cec5SDimitry Andric                                         const EXC &exc) {
620b57cec5SDimitry Andric   return ::thread_set_state(
630b57cec5SDimitry Andric       tid, flavor, reinterpret_cast<thread_state_t>(const_cast<EXC *>(&exc)),
640b57cec5SDimitry Andric       EXCWordCount);
650b57cec5SDimitry Andric }
660b57cec5SDimitry Andric 
DoWriteDBG(lldb::tid_t tid,int flavor,const DBG & dbg)670b57cec5SDimitry Andric int RegisterContextMach_arm::DoWriteDBG(lldb::tid_t tid, int flavor,
680b57cec5SDimitry Andric                                         const DBG &dbg) {
690b57cec5SDimitry Andric   return ::thread_set_state(
700b57cec5SDimitry Andric       tid, flavor, reinterpret_cast<thread_state_t>(const_cast<DBG *>(&dbg)),
710b57cec5SDimitry Andric       DBGWordCount);
720b57cec5SDimitry Andric }
730b57cec5SDimitry Andric 
740b57cec5SDimitry Andric #endif
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